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review.blissroms.org / platform_bionic / 5e52226f02b7199fa7870a6195b3e5c0efb1c8d3 / . / libc / kernel / uapi / linux / serial_reg.h
blob: 71063ec93de2b0c651bc891d74b84dc0b4f2154e [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _LINUX_SERIAL_REG_H
20#define _LINUX_SERIAL_REG_H
21#define UART_RX 0
22#define UART_TX 0
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24#define UART_IER 1
25#define UART_IER_MSI 0x08
26#define UART_IER_RLSI 0x04
27#define UART_IER_THRI 0x02
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
29#define UART_IER_RDI 0x01
30#define UART_IERX_SLEEP 0x10
31#define UART_IIR 2
32#define UART_IIR_NO_INT 0x01
33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]34#define UART_IIR_ID 0x0e
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]35#define UART_IIR_MSI 0x00
36#define UART_IIR_THRI 0x02
37#define UART_IIR_RDI 0x04
38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
39#define UART_IIR_RLSI 0x06
40#define UART_IIR_BUSY 0x07
41#define UART_IIR_RX_TIMEOUT 0x0c
42#define UART_IIR_XOFF 0x10
43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
44#define UART_IIR_CTS_RTS_DSR 0x20
45#define UART_FCR 2
46#define UART_FCR_ENABLE_FIFO 0x01
47#define UART_FCR_CLEAR_RCVR 0x02
48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
49#define UART_FCR_CLEAR_XMIT 0x04
50#define UART_FCR_DMA_SELECT 0x08
51#define UART_FCR_R_TRIG_00 0x00
52#define UART_FCR_R_TRIG_01 0x40
53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
54#define UART_FCR_R_TRIG_10 0x80
55#define UART_FCR_R_TRIG_11 0xc0
56#define UART_FCR_T_TRIG_00 0x00
57#define UART_FCR_T_TRIG_01 0x10
58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
59#define UART_FCR_T_TRIG_10 0x20
60#define UART_FCR_T_TRIG_11 0x30
61#define UART_FCR_TRIGGER_MASK 0xC0
62#define UART_FCR_TRIGGER_1 0x00
63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
64#define UART_FCR_TRIGGER_4 0x40
65#define UART_FCR_TRIGGER_8 0x80
66#define UART_FCR_TRIGGER_14 0xC0
67#define UART_FCR6_R_TRIGGER_8 0x00
68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
69#define UART_FCR6_R_TRIGGER_16 0x40
70#define UART_FCR6_R_TRIGGER_24 0x80
71#define UART_FCR6_R_TRIGGER_28 0xC0
72#define UART_FCR6_T_TRIGGER_16 0x00
73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
74#define UART_FCR6_T_TRIGGER_8 0x10
75#define UART_FCR6_T_TRIGGER_24 0x20
76#define UART_FCR6_T_TRIGGER_30 0x30
77#define UART_FCR7_64BYTE 0x20
78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]79#define UART_FCR_R_TRIG_SHIFT 6
80#define UART_FCR_R_TRIG_BITS(x) (((x) & UART_FCR_TRIGGER_MASK) >> UART_FCR_R_TRIG_SHIFT)
81#define UART_FCR_R_TRIG_MAX_STATE 4
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]82#define UART_LCR 3
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]84#define UART_LCR_DLAB 0x80
85#define UART_LCR_SBC 0x40
86#define UART_LCR_SPAR 0x20
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]87#define UART_LCR_EPAR 0x10
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]89#define UART_LCR_PARITY 0x08
90#define UART_LCR_STOP 0x04
91#define UART_LCR_WLEN5 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]92#define UART_LCR_WLEN6 0x01
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]94#define UART_LCR_WLEN7 0x02
95#define UART_LCR_WLEN8 0x03
96#define UART_LCR_CONF_MODE_A UART_LCR_DLAB
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]97#define UART_LCR_CONF_MODE_B 0xBF
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]99#define UART_MCR 4
100#define UART_MCR_CLKSEL 0x80
101#define UART_MCR_TCRTLR 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]102#define UART_MCR_XONANY 0x20
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]104#define UART_MCR_AFE 0x20
105#define UART_MCR_LOOP 0x10
106#define UART_MCR_OUT2 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]107#define UART_MCR_OUT1 0x04
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]109#define UART_MCR_RTS 0x02
110#define UART_MCR_DTR 0x01
111#define UART_LSR 5
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]112#define UART_LSR_FIFOE 0x80
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]114#define UART_LSR_TEMT 0x40
115#define UART_LSR_THRE 0x20
116#define UART_LSR_BI 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]117#define UART_LSR_FE 0x08
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]119#define UART_LSR_PE 0x04
120#define UART_LSR_OE 0x02
121#define UART_LSR_DR 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]122#define UART_LSR_BRK_ERROR_BITS 0x1E
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]124#define UART_MSR 6
125#define UART_MSR_DCD 0x80
126#define UART_MSR_RI 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]127#define UART_MSR_DSR 0x20
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]129#define UART_MSR_CTS 0x10
130#define UART_MSR_DDCD 0x08
131#define UART_MSR_TERI 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]132#define UART_MSR_DDSR 0x02
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]134#define UART_MSR_DCTS 0x01
135#define UART_MSR_ANY_DELTA 0x0F
136#define UART_SCR 7
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]137#define UART_DLL 0
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]139#define UART_DLM 1
140#define UART_EFR 2
141#define UART_XR_EFR 9
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]142#define UART_EFR_CTS 0x80
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]144#define UART_EFR_RTS 0x40
145#define UART_EFR_SCD 0x20
146#define UART_EFR_ECB 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]147#define UART_XON1 4
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]149#define UART_XON2 5
150#define UART_XOFF1 6
151#define UART_XOFF2 7
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]152#define UART_TI752_TCR 6
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]154#define UART_TI752_TLR 7
155#define UART_TRG 0
156#define UART_TRG_1 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]157#define UART_TRG_4 0x04
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]159#define UART_TRG_8 0x08
160#define UART_TRG_16 0x10
161#define UART_TRG_32 0x20
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]162#define UART_TRG_64 0x40
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]164#define UART_TRG_96 0x60
165#define UART_TRG_120 0x78
166#define UART_TRG_128 0x80
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]167#define UART_FCTR 1
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]169#define UART_FCTR_RTS_NODELAY 0x00
170#define UART_FCTR_RTS_4DELAY 0x01
171#define UART_FCTR_RTS_6DELAY 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]172#define UART_FCTR_RTS_8DELAY 0x03
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]174#define UART_FCTR_IRDA 0x04
175#define UART_FCTR_TX_INT 0x08
176#define UART_FCTR_TRGA 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]177#define UART_FCTR_TRGB 0x10
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]179#define UART_FCTR_TRGC 0x20
180#define UART_FCTR_TRGD 0x30
181#define UART_FCTR_SCR_SWAP 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]182#define UART_FCTR_RX 0x00
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]184#define UART_FCTR_TX 0x80
185#define UART_EMSR 7
186#define UART_EMSR_FIFO_COUNT 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]187#define UART_EMSR_ALT_COUNT 0x02
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]189#define UART_IER_DMAE 0x80
190#define UART_IER_UUE 0x40
191#define UART_IER_NRZE 0x20
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]192#define UART_IER_RTOIE 0x10
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]194#define UART_IIR_TOD 0x08
195#define UART_FCR_PXAR1 0x00
196#define UART_FCR_PXAR8 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]197#define UART_FCR_PXAR16 0x80
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]199#define UART_FCR_PXAR32 0xc0
200#define UART_FCR_HSU_64_1B 0x00
201#define UART_FCR_HSU_64_16B 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]202#define UART_FCR_HSU_64_32B 0x80
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]204#define UART_FCR_HSU_64_56B 0xc0
205#define UART_FCR_HSU_16_1B 0x00
206#define UART_FCR_HSU_16_4B 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]207#define UART_FCR_HSU_16_8B 0x80
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]209#define UART_FCR_HSU_16_14B 0xc0
210#define UART_FCR_HSU_64B_FIFO 0x20
211#define UART_FCR_HSU_16B_FIFO 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]212#define UART_FCR_HALF_EMPT_TXI 0x00
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]214#define UART_FCR_FULL_EMPT_TXI 0x08
215#define UART_ASR 0x01
216#define UART_RFL 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]217#define UART_TFL 0x04
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]219#define UART_ICR 0x05
220#define UART_ACR 0x00
221#define UART_CPR 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]222#define UART_TCR 0x02
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]224#define UART_CKS 0x03
225#define UART_TTL 0x04
226#define UART_RTL 0x05
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]227#define UART_FCL 0x06
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]229#define UART_FCH 0x07
230#define UART_ID1 0x08
231#define UART_ID2 0x09
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]232#define UART_ID3 0x0A
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]234#define UART_REV 0x0B
235#define UART_CSR 0x0C
236#define UART_NMR 0x0D
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]237#define UART_CTR 0xFF
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]239#define UART_ACR_RXDIS 0x01
240#define UART_ACR_TXDIS 0x02
241#define UART_ACR_DSRFC 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]242#define UART_ACR_TLENB 0x20
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]244#define UART_ACR_ICRRD 0x40
245#define UART_ACR_ASREN 0x80
246#define UART_RSA_BASE (-8)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]247#define UART_RSA_MSR ((UART_RSA_BASE) + 0)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]249#define UART_RSA_MSR_SWAP (1 << 0)
250#define UART_RSA_MSR_FIFO (1 << 2)
251#define UART_RSA_MSR_FLOW (1 << 3)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]252#define UART_RSA_MSR_ITYP (1 << 4)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]254#define UART_RSA_IER ((UART_RSA_BASE) + 1)
255#define UART_RSA_IER_Rx_FIFO_H (1 << 0)
256#define UART_RSA_IER_Tx_FIFO_H (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]257#define UART_RSA_IER_Tx_FIFO_E (1 << 2)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]259#define UART_RSA_IER_Rx_TOUT (1 << 3)
260#define UART_RSA_IER_TIMER (1 << 4)
261#define UART_RSA_SRR ((UART_RSA_BASE) + 2)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]262#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]264#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1)
265#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2)
266#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]267#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]269#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5)
270#define UART_RSA_SRR_Rx_TOUT (1 << 6)
271#define UART_RSA_SRR_TIMER (1 << 7)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]272#define UART_RSA_FRR ((UART_RSA_BASE) + 2)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]274#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3)
275#define UART_RSA_TCR ((UART_RSA_BASE) + 4)
276#define UART_RSA_TCR_SWITCH (1 << 0)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]277#define SERIAL_RSA_BAUD_BASE (921600)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]279#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
280#define UART_OMAP_MDR1 0x08
281#define UART_OMAP_MDR2 0x09
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]282#define UART_OMAP_SCR 0x10
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]284#define UART_OMAP_SSR 0x11
285#define UART_OMAP_EBLR 0x12
286#define UART_OMAP_OSC_12M_SEL 0x13
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]287#define UART_OMAP_MVER 0x14
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]289#define UART_OMAP_SYSC 0x15
290#define UART_OMAP_SYSS 0x16
291#define UART_OMAP_WER 0x17
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]292#define UART_OMAP_MDR1_16X_MODE 0x00
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]294#define UART_OMAP_MDR1_SIR_MODE 0x01
295#define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02
296#define UART_OMAP_MDR1_13X_MODE 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]297#define UART_OMAP_MDR1_MIR_MODE 0x04
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]299#define UART_OMAP_MDR1_FIR_MODE 0x05
300#define UART_OMAP_MDR1_CIR_MODE 0x06
301#define UART_OMAP_MDR1_DISABLE 0x07
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]302#define UART_EXAR_8XMODE 0x88
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]304#define UART_EXAR_SLEEP 0x8b
305#define UART_EXAR_DVID 0x8d
306#define UART_EXAR_FCTR 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]307#define UART_FCTR_EXAR_IRDA 0x08
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]309#define UART_FCTR_EXAR_485 0x10
310#define UART_FCTR_EXAR_TRGA 0x00
311#define UART_FCTR_EXAR_TRGB 0x60
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]312#define UART_FCTR_EXAR_TRGC 0x80
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]314#define UART_FCTR_EXAR_TRGD 0xc0
315#define UART_EXAR_TXTRG 0x0a
316#define UART_EXAR_RXTRG 0x0b
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]317#endif
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */