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review.blissroms.org / platform_bionic / 654325de026a2ca5b76b8b40e576c959d8211fdc / . / libc / kernel / common / linux / spi / cpcap.h
blob: 8b729b0ff3356b0d917d650a0eab777c653bce15 [file] [log] [blame]
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _LINUX_SPI_CPCAP_H
20#define _LINUX_SPI_CPCAP_H
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]21#include <linux/ioctl.h>
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]22#define CPCAP_DEV_NAME "cpcap"
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]24#define CPCAP_NUM_REG_CPCAP (CPCAP_REG_END - CPCAP_REG_START + 1)
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]25#define CPCAP_IRQ_INT1_INDEX 0
26#define CPCAP_IRQ_INT2_INDEX 16
27#define CPCAP_IRQ_INT3_INDEX 32
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]29#define CPCAP_IRQ_INT4_INDEX 48
30#define CPCAP_IRQ_INT5_INDEX 64
Iliyan Malchevbb3bcbc2010-11-02 15:58:36 -0700[diff] [blame]31#define CPCAP_HWCFG_NUM 2
Iliyan Malchevbb3bcbc2010-11-02 15:58:36 -0700[diff] [blame]32#define CPCAP_HWCFG0_SEC_STBY_SW1 0x0001
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Iliyan Malchevbb3bcbc2010-11-02 15:58:36 -0700[diff] [blame]34#define CPCAP_HWCFG0_SEC_STBY_SW2 0x0002
35#define CPCAP_HWCFG0_SEC_STBY_SW3 0x0004
36#define CPCAP_HWCFG0_SEC_STBY_SW4 0x0008
37#define CPCAP_HWCFG0_SEC_STBY_SW5 0x0010
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Iliyan Malchevbb3bcbc2010-11-02 15:58:36 -0700[diff] [blame]39#define CPCAP_HWCFG0_SEC_STBY_VAUDIO 0x0020
40#define CPCAP_HWCFG0_SEC_STBY_VCAM 0x0040
41#define CPCAP_HWCFG0_SEC_STBY_VCSI 0x0080
42#define CPCAP_HWCFG0_SEC_STBY_VDAC 0x0100
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Iliyan Malchevbb3bcbc2010-11-02 15:58:36 -0700[diff] [blame]44#define CPCAP_HWCFG0_SEC_STBY_VDIG 0x0200
45#define CPCAP_HWCFG0_SEC_STBY_VHVIO 0x0400
46#define CPCAP_HWCFG0_SEC_STBY_VPLL 0x0800
47#define CPCAP_HWCFG0_SEC_STBY_VRF1 0x1000
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Iliyan Malchevbb3bcbc2010-11-02 15:58:36 -0700[diff] [blame]49#define CPCAP_HWCFG0_SEC_STBY_VRF2 0x2000
50#define CPCAP_HWCFG0_SEC_STBY_VRFREF 0x4000
51#define CPCAP_HWCFG0_SEC_STBY_VSDIO 0x8000
Iliyan Malchevbb3bcbc2010-11-02 15:58:36 -0700[diff] [blame]52#define CPCAP_HWCFG1_SEC_STBY_VWLAN1 0x0001
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Iliyan Malchevbb3bcbc2010-11-02 15:58:36 -0700[diff] [blame]54#define CPCAP_HWCFG1_SEC_STBY_VWLAN2 0x0002
55#define CPCAP_HWCFG1_SEC_STBY_VSIM 0x0004
56#define CPCAP_HWCFG1_SEC_STBY_VSIMCARD 0x0008
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]57#define CPCAP_WHISPER_MODE_PU 0x00000001
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]59#define CPCAP_WHISPER_ENABLE_UART 0x00000002
60#define CPCAP_WHISPER_ACCY_MASK 0xF8000000
61#define CPCAP_WHISPER_ACCY_SHFT 27
62#define CPCAP_WHISPER_ID_SIZE 16
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Iliyan Malchevbb3bcbc2010-11-02 15:58:36 -0700[diff] [blame]64#define CPCAP_WHISPER_PROP_SIZE 7
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]65enum cpcap_regulator_id {
66 CPCAP_SW2,
67 CPCAP_SW4,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]69 CPCAP_SW5,
70 CPCAP_VCAM,
71 CPCAP_VCSI,
72 CPCAP_VDAC,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]74 CPCAP_VDIG,
75 CPCAP_VFUSE,
76 CPCAP_VHVIO,
77 CPCAP_VSDIO,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]79 CPCAP_VPLL,
80 CPCAP_VRF1,
81 CPCAP_VRF2,
82 CPCAP_VRFREF,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]84 CPCAP_VWLAN1,
85 CPCAP_VWLAN2,
86 CPCAP_VSIM,
87 CPCAP_VSIMCARD,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]89 CPCAP_VVIB,
90 CPCAP_VUSB,
91 CPCAP_VAUDIO,
92 CPCAP_NUM_REGULATORS
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]94};
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]95enum cpcap_reg {
96 CPCAP_REG_START,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]97 CPCAP_REG_INT1 = CPCAP_REG_START,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]99 CPCAP_REG_INT2,
100 CPCAP_REG_INT3,
101 CPCAP_REG_INT4,
102 CPCAP_REG_INTM1,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]104 CPCAP_REG_INTM2,
105 CPCAP_REG_INTM3,
106 CPCAP_REG_INTM4,
107 CPCAP_REG_INTS1,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]109 CPCAP_REG_INTS2,
110 CPCAP_REG_INTS3,
111 CPCAP_REG_INTS4,
112 CPCAP_REG_ASSIGN1,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]114 CPCAP_REG_ASSIGN2,
115 CPCAP_REG_ASSIGN3,
116 CPCAP_REG_ASSIGN4,
117 CPCAP_REG_ASSIGN5,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]119 CPCAP_REG_ASSIGN6,
120 CPCAP_REG_VERSC1,
121 CPCAP_REG_VERSC2,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]122 CPCAP_REG_MI1,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]124 CPCAP_REG_MIM1,
125 CPCAP_REG_MI2,
126 CPCAP_REG_MIM2,
127 CPCAP_REG_UCC1,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]129 CPCAP_REG_UCC2,
130 CPCAP_REG_PC1,
131 CPCAP_REG_PC2,
132 CPCAP_REG_BPEOL,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]134 CPCAP_REG_PGC,
135 CPCAP_REG_MT1,
136 CPCAP_REG_MT2,
137 CPCAP_REG_MT3,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]139 CPCAP_REG_PF,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]140 CPCAP_REG_SCC,
141 CPCAP_REG_SW1,
142 CPCAP_REG_SW2,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]144 CPCAP_REG_UCTM,
145 CPCAP_REG_TOD1,
146 CPCAP_REG_TOD2,
147 CPCAP_REG_TODA1,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]149 CPCAP_REG_TODA2,
150 CPCAP_REG_DAY,
151 CPCAP_REG_DAYA,
152 CPCAP_REG_VAL1,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]154 CPCAP_REG_VAL2,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]155 CPCAP_REG_SDVSPLL,
156 CPCAP_REG_SI2CC1,
157 CPCAP_REG_Si2CC2,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]159 CPCAP_REG_S1C1,
160 CPCAP_REG_S1C2,
161 CPCAP_REG_S2C1,
162 CPCAP_REG_S2C2,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]164 CPCAP_REG_S3C,
165 CPCAP_REG_S4C1,
166 CPCAP_REG_S4C2,
167 CPCAP_REG_S5C,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]169 CPCAP_REG_S6C,
170 CPCAP_REG_VCAMC,
171 CPCAP_REG_VCSIC,
172 CPCAP_REG_VDACC,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]174 CPCAP_REG_VDIGC,
175 CPCAP_REG_VFUSEC,
176 CPCAP_REG_VHVIOC,
177 CPCAP_REG_VSDIOC,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]179 CPCAP_REG_VPLLC,
180 CPCAP_REG_VRF1C,
181 CPCAP_REG_VRF2C,
182 CPCAP_REG_VRFREFC,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]184 CPCAP_REG_VWLAN1C,
185 CPCAP_REG_VWLAN2C,
186 CPCAP_REG_VSIMC,
187 CPCAP_REG_VVIBC,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]189 CPCAP_REG_VUSBC,
190 CPCAP_REG_VUSBINT1C,
191 CPCAP_REG_VUSBINT2C,
192 CPCAP_REG_URT,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]194 CPCAP_REG_URM1,
195 CPCAP_REG_URM2,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]196 CPCAP_REG_VAUDIOC,
197 CPCAP_REG_CC,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]199 CPCAP_REG_CDI,
200 CPCAP_REG_SDAC,
201 CPCAP_REG_SDACDI,
202 CPCAP_REG_TXI,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]204 CPCAP_REG_TXMP,
205 CPCAP_REG_RXOA,
206 CPCAP_REG_RXVC,
207 CPCAP_REG_RXCOA,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]209 CPCAP_REG_RXSDOA,
210 CPCAP_REG_RXEPOA,
211 CPCAP_REG_RXLL,
212 CPCAP_REG_A2LA,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]214 CPCAP_REG_MIPIS1,
215 CPCAP_REG_MIPIS2,
216 CPCAP_REG_MIPIS3,
217 CPCAP_REG_LVAB,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]219 CPCAP_REG_CCC1,
220 CPCAP_REG_CRM,
221 CPCAP_REG_CCCC2,
222 CPCAP_REG_CCS1,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]224 CPCAP_REG_CCS2,
225 CPCAP_REG_CCA1,
226 CPCAP_REG_CCA2,
227 CPCAP_REG_CCM,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]229 CPCAP_REG_CCO,
230 CPCAP_REG_CCI,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]231 CPCAP_REG_ADCC1,
232 CPCAP_REG_ADCC2,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]234 CPCAP_REG_ADCD0,
235 CPCAP_REG_ADCD1,
236 CPCAP_REG_ADCD2,
237 CPCAP_REG_ADCD3,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]239 CPCAP_REG_ADCD4,
240 CPCAP_REG_ADCD5,
241 CPCAP_REG_ADCD6,
242 CPCAP_REG_ADCD7,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]244 CPCAP_REG_ADCAL1,
245 CPCAP_REG_ADCAL2,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]246 CPCAP_REG_USBC1,
247 CPCAP_REG_USBC2,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]249 CPCAP_REG_USBC3,
250 CPCAP_REG_UVIDL,
251 CPCAP_REG_UVIDH,
252 CPCAP_REG_UPIDL,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]254 CPCAP_REG_UPIDH,
255 CPCAP_REG_UFC1,
256 CPCAP_REG_UFC2,
257 CPCAP_REG_UFC3,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]259 CPCAP_REG_UIC1,
260 CPCAP_REG_UIC2,
261 CPCAP_REG_UIC3,
262 CPCAP_REG_USBOTG1,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]264 CPCAP_REG_USBOTG2,
265 CPCAP_REG_USBOTG3,
266 CPCAP_REG_UIER1,
267 CPCAP_REG_UIER2,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]269 CPCAP_REG_UIER3,
270 CPCAP_REG_UIEF1,
271 CPCAP_REG_UIEF2,
272 CPCAP_REG_UIEF3,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]274 CPCAP_REG_UIS,
275 CPCAP_REG_UIL,
276 CPCAP_REG_USBD,
277 CPCAP_REG_SCR1,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]279 CPCAP_REG_SCR2,
280 CPCAP_REG_SCR3,
281 CPCAP_REG_VMC,
282 CPCAP_REG_OWDC,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]284 CPCAP_REG_GPIO0,
285 CPCAP_REG_GPIO1,
286 CPCAP_REG_GPIO2,
287 CPCAP_REG_GPIO3,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]289 CPCAP_REG_GPIO4,
290 CPCAP_REG_GPIO5,
291 CPCAP_REG_GPIO6,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]292 CPCAP_REG_MDLC,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]294 CPCAP_REG_KLC,
295 CPCAP_REG_ADLC,
296 CPCAP_REG_REDC,
297 CPCAP_REG_GREENC,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]299 CPCAP_REG_BLUEC,
300 CPCAP_REG_CFC,
301 CPCAP_REG_ABC,
302 CPCAP_REG_BLEDC,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]304 CPCAP_REG_CLEDC,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]305 CPCAP_REG_OW1C,
306 CPCAP_REG_OW1D,
307 CPCAP_REG_OW1I,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]309 CPCAP_REG_OW1IE,
310 CPCAP_REG_OW1,
311 CPCAP_REG_OW2C,
312 CPCAP_REG_OW2D,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]314 CPCAP_REG_OW2I,
315 CPCAP_REG_OW2IE,
316 CPCAP_REG_OW2,
317 CPCAP_REG_OW3C,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]319 CPCAP_REG_OW3D,
320 CPCAP_REG_OW3I,
321 CPCAP_REG_OW3IE,
322 CPCAP_REG_OW3,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]324 CPCAP_REG_GCAIC,
325 CPCAP_REG_GCAIM,
326 CPCAP_REG_LGDIR,
327 CPCAP_REG_LGPU,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]329 CPCAP_REG_LGPIN,
330 CPCAP_REG_LGMASK,
331 CPCAP_REG_LDEB,
332 CPCAP_REG_LGDET,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]334 CPCAP_REG_LMISC,
335 CPCAP_REG_LMACE,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]336 CPCAP_REG_END = CPCAP_REG_LMACE,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]337 CPCAP_REG_MAX
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]339 = CPCAP_REG_END,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]340 CPCAP_REG_SIZE = CPCAP_REG_MAX + 1,
341 CPCAP_REG_UNUSED = CPCAP_REG_MAX + 2,
342};
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]344enum {
345 CPCAP_IOCTL_NUM_TEST__START,
346 CPCAP_IOCTL_NUM_TEST_READ_REG,
347 CPCAP_IOCTL_NUM_TEST_WRITE_REG,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]349 CPCAP_IOCTL_NUM_TEST__END,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]350 CPCAP_IOCTL_NUM_ADC__START,
351 CPCAP_IOCTL_NUM_ADC_PHASE,
352 CPCAP_IOCTL_NUM_ADC__END,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]354 CPCAP_IOCTL_NUM_BATT__START,
355 CPCAP_IOCTL_NUM_BATT_DISPLAY_UPDATE,
356 CPCAP_IOCTL_NUM_BATT_ATOD_ASYNC,
357 CPCAP_IOCTL_NUM_BATT_ATOD_SYNC,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]359 CPCAP_IOCTL_NUM_BATT_ATOD_READ,
360 CPCAP_IOCTL_NUM_BATT__END,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]361 CPCAP_IOCTL_NUM_UC__START,
362 CPCAP_IOCTL_NUM_UC_MACRO_START,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]364 CPCAP_IOCTL_NUM_UC_MACRO_STOP,
365 CPCAP_IOCTL_NUM_UC_GET_VENDOR,
366 CPCAP_IOCTL_NUM_UC_SET_TURBO_MODE,
367 CPCAP_IOCTL_NUM_UC__END,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]369 CPCAP_IOCTL_NUM_ACCY__START,
370 CPCAP_IOCTL_NUM_ACCY_WHISPER,
371 CPCAP_IOCTL_NUM_ACCY__END,
372};
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]374enum cpcap_irqs {
375 CPCAP_IRQ__START,
376 CPCAP_IRQ_HSCLK = CPCAP_IRQ_INT1_INDEX,
377 CPCAP_IRQ_PRIMAC,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]379 CPCAP_IRQ_SECMAC,
380 CPCAP_IRQ_LOWBPL,
381 CPCAP_IRQ_SEC2PRI,
382 CPCAP_IRQ_LOWBPH,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]384 CPCAP_IRQ_EOL,
385 CPCAP_IRQ_TS,
386 CPCAP_IRQ_ADCDONE,
387 CPCAP_IRQ_HS,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]389 CPCAP_IRQ_MB2,
390 CPCAP_IRQ_VBUSOV,
391 CPCAP_IRQ_RVRS_CHRG,
392 CPCAP_IRQ_CHRG_DET,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]394 CPCAP_IRQ_IDFLOAT,
395 CPCAP_IRQ_IDGND,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]396 CPCAP_IRQ_SE1 = CPCAP_IRQ_INT2_INDEX,
397 CPCAP_IRQ_SESSEND,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]399 CPCAP_IRQ_SESSVLD,
400 CPCAP_IRQ_VBUSVLD,
401 CPCAP_IRQ_CHRG_CURR1,
402 CPCAP_IRQ_CHRG_CURR2,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]404 CPCAP_IRQ_RVRS_MODE,
405 CPCAP_IRQ_ON,
406 CPCAP_IRQ_ON2,
407 CPCAP_IRQ_CLK,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]409 CPCAP_IRQ_1HZ,
410 CPCAP_IRQ_PTT,
411 CPCAP_IRQ_SE0CONN,
412 CPCAP_IRQ_CHRG_SE1B,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]414 CPCAP_IRQ_UART_ECHO_OVERRUN,
415 CPCAP_IRQ_EXTMEMHD,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]416 CPCAP_IRQ_WARM = CPCAP_IRQ_INT3_INDEX,
417 CPCAP_IRQ_SYSRSTR,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]419 CPCAP_IRQ_SOFTRST,
420 CPCAP_IRQ_DIEPWRDWN,
421 CPCAP_IRQ_DIETEMPH,
422 CPCAP_IRQ_PC,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]424 CPCAP_IRQ_OFLOWSW,
425 CPCAP_IRQ_TODA,
426 CPCAP_IRQ_OPT_SEL_DTCH,
427 CPCAP_IRQ_OPT_SEL_STATE,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]429 CPCAP_IRQ_ONEWIRE1,
430 CPCAP_IRQ_ONEWIRE2,
431 CPCAP_IRQ_ONEWIRE3,
432 CPCAP_IRQ_UCRESET,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]434 CPCAP_IRQ_PWRGOOD,
435 CPCAP_IRQ_USBDPLLCLK,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]436 CPCAP_IRQ_DPI = CPCAP_IRQ_INT4_INDEX,
437 CPCAP_IRQ_DMI,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]439 CPCAP_IRQ_UCBUSY,
440 CPCAP_IRQ_GCAI_CURR1,
441 CPCAP_IRQ_GCAI_CURR2,
442 CPCAP_IRQ_SB_MAX_RETRANSMIT_ERR,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]444 CPCAP_IRQ_BATTDETB,
445 CPCAP_IRQ_PRIHALT,
446 CPCAP_IRQ_SECHALT,
447 CPCAP_IRQ_CC_CAL,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]449 CPCAP_IRQ_UC_PRIROMR = CPCAP_IRQ_INT5_INDEX,
450 CPCAP_IRQ_UC_PRIRAMW,
451 CPCAP_IRQ_UC_PRIRAMR,
452 CPCAP_IRQ_UC_USEROFF,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]454 CPCAP_IRQ_UC_PRIMACRO_4,
455 CPCAP_IRQ_UC_PRIMACRO_5,
456 CPCAP_IRQ_UC_PRIMACRO_6,
457 CPCAP_IRQ_UC_PRIMACRO_7,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]459 CPCAP_IRQ_UC_PRIMACRO_8,
460 CPCAP_IRQ_UC_PRIMACRO_9,
461 CPCAP_IRQ_UC_PRIMACRO_10,
462 CPCAP_IRQ_UC_PRIMACRO_11,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]464 CPCAP_IRQ_UC_PRIMACRO_12,
465 CPCAP_IRQ_UC_PRIMACRO_13,
466 CPCAP_IRQ_UC_PRIMACRO_14,
467 CPCAP_IRQ_UC_PRIMACRO_15,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]469 CPCAP_IRQ__NUM
470};
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]471enum cpcap_adc_bank0 {
472 CPCAP_ADC_AD0_BATTDETB,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]474 CPCAP_ADC_BATTP,
475 CPCAP_ADC_VBUS,
476 CPCAP_ADC_AD3,
477 CPCAP_ADC_BPLUS_AD4,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]479 CPCAP_ADC_CHG_ISENSE,
480 CPCAP_ADC_BATTI_ADC,
481 CPCAP_ADC_USB_ID,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]482 CPCAP_ADC_BANK0_NUM,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]484};
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]485enum cpcap_adc_bank1 {
486 CPCAP_ADC_AD8,
487 CPCAP_ADC_AD9,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]489 CPCAP_ADC_LICELL,
490 CPCAP_ADC_HV_BATTP,
491 CPCAP_ADC_TSX1_AD12,
492 CPCAP_ADC_TSX2_AD13,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]494 CPCAP_ADC_TSY1_AD14,
495 CPCAP_ADC_TSY2_AD15,
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]496 CPCAP_ADC_BANK1_NUM,
497};
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]499enum cpcap_adc_format {
500 CPCAP_ADC_FORMAT_RAW,
501 CPCAP_ADC_FORMAT_PHASED,
502 CPCAP_ADC_FORMAT_CONVERTED,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]504};
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]505enum cpcap_adc_timing {
506 CPCAP_ADC_TIMING_IMM,
507 CPCAP_ADC_TIMING_IN,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]509 CPCAP_ADC_TIMING_OUT,
510};
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]511enum cpcap_adc_type {
512 CPCAP_ADC_TYPE_BANK_0,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]514 CPCAP_ADC_TYPE_BANK_1,
515 CPCAP_ADC_TYPE_BATT_PI,
516};
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]517enum cpcap_macro {
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]519 CPCAP_MACRO_ROMR,
520 CPCAP_MACRO_RAMW,
521 CPCAP_MACRO_RAMR,
522 CPCAP_MACRO_USEROFF,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]524 CPCAP_MACRO_4,
525 CPCAP_MACRO_5,
526 CPCAP_MACRO_6,
527 CPCAP_MACRO_7,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]529 CPCAP_MACRO_8,
530 CPCAP_MACRO_9,
531 CPCAP_MACRO_10,
532 CPCAP_MACRO_11,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]534 CPCAP_MACRO_12,
535 CPCAP_MACRO_13,
536 CPCAP_MACRO_14,
537 CPCAP_MACRO_15,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]539 CPCAP_MACRO__END,
540};
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]541enum cpcap_vendor {
542 CPCAP_VENDOR_ST,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]544 CPCAP_VENDOR_TI,
545};
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]546enum cpcap_revision {
547 CPCAP_REVISION_1_0 = 0x08,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]549 CPCAP_REVISION_1_1 = 0x09,
550 CPCAP_REVISION_2_0 = 0x10,
551 CPCAP_REVISION_2_1 = 0x11,
552};
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]554enum cpcap_batt_usb_model {
555 CPCAP_BATT_USB_MODEL_NONE,
556 CPCAP_BATT_USB_MODEL_USB,
557 CPCAP_BATT_USB_MODEL_FACTORY,
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]559};
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]560struct cpcap_spi_init_data {
561 enum cpcap_reg reg;
562 unsigned short data;
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]564};
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]565struct cpcap_adc_ato {
566 unsigned short ato_in;
567 unsigned short atox_in;
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]569 unsigned short adc_ps_factor_in;
570 unsigned short atox_ps_factor_in;
571 unsigned short ato_out;
572 unsigned short atox_out;
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]574 unsigned short adc_ps_factor_out;
575 unsigned short atox_ps_factor_out;
576};
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]577struct cpcap_batt_data {
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]579 int status;
580 int health;
581 int present;
582 int capacity;
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]584 int batt_volt;
585 int batt_temp;
586};
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]587struct cpcap_batt_ac_data {
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]589 int online;
590};
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]591struct cpcap_batt_usb_data {
592 int online;
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]594 int current_now;
595 enum cpcap_batt_usb_model model;
596};
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]597struct cpcap_device;
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]599struct cpcap_adc_us_request {
600 enum cpcap_adc_format format;
601 enum cpcap_adc_timing timing;
602 enum cpcap_adc_type type;
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]604 int status;
605 int result[CPCAP_ADC_BANK0_NUM];
606};
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]607struct cpcap_adc_phase {
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]609 signed char offset_batti;
610 unsigned char slope_batti;
611 signed char offset_chrgi;
612 unsigned char slope_chrgi;
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]614 signed char offset_battp;
615 unsigned char slope_battp;
616 signed char offset_bp;
617 unsigned char slope_bp;
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]619 signed char offset_battt;
620 unsigned char slope_battt;
621 signed char offset_chrgv;
622 unsigned char slope_chrgv;
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]624};
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]625struct cpcap_regacc {
626 unsigned short reg;
627 unsigned short value;
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]629 unsigned short mask;
630};
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]631struct cpcap_whisper_request {
632 unsigned int cmd;
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]634 char dock_id[CPCAP_WHISPER_ID_SIZE];
Iliyan Malchevbb3bcbc2010-11-02 15:58:36 -0700[diff] [blame]635 char dock_prop[CPCAP_WHISPER_PROP_SIZE];
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]636};
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]637#define CPCAP_IOCTL_TEST_READ_REG _IOWR(0, CPCAP_IOCTL_NUM_TEST_READ_REG, struct cpcap_regacc*)
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]639#define CPCAP_IOCTL_TEST_WRITE_REG _IOWR(0, CPCAP_IOCTL_NUM_TEST_WRITE_REG, struct cpcap_regacc*)
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]640#define CPCAP_IOCTL_ADC_PHASE _IOWR(0, CPCAP_IOCTL_NUM_ADC_PHASE, struct cpcap_adc_phase*)
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]641#define CPCAP_IOCTL_BATT_DISPLAY_UPDATE _IOW(0, CPCAP_IOCTL_NUM_BATT_DISPLAY_UPDATE, struct cpcap_batt_data*)
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]642#define CPCAP_IOCTL_BATT_ATOD_ASYNC _IOW(0, CPCAP_IOCTL_NUM_BATT_ATOD_ASYNC, struct cpcap_adc_us_request*)
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]643/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]644#define CPCAP_IOCTL_BATT_ATOD_SYNC _IOWR(0, CPCAP_IOCTL_NUM_BATT_ATOD_SYNC, struct cpcap_adc_us_request*)
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]645#define CPCAP_IOCTL_BATT_ATOD_READ _IOWR(0, CPCAP_IOCTL_NUM_BATT_ATOD_READ, struct cpcap_adc_us_request*)
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]646#define CPCAP_IOCTL_UC_MACRO_START _IOWR(0, CPCAP_IOCTL_NUM_UC_MACRO_START, enum cpcap_macro)
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]647#define CPCAP_IOCTL_UC_MACRO_STOP _IOWR(0, CPCAP_IOCTL_NUM_UC_MACRO_STOP, enum cpcap_macro)
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]648/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]649#define CPCAP_IOCTL_UC_GET_VENDOR _IOWR(0, CPCAP_IOCTL_NUM_UC_GET_VENDOR, enum cpcap_vendor)
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]650#define CPCAP_IOCTL_UC_SET_TURBO_MODE _IOW(0, CPCAP_IOCTL_NUM_UC_SET_TURBO_MODE, unsigned short)
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]651#define CPCAP_IOCTL_ACCY_WHISPER _IOW(0, CPCAP_IOCTL_NUM_ACCY_WHISPER, struct cpcap_whisper_request*)
Nick Pellyb3765b22010-08-16 15:31:01 -0700[diff] [blame]652#endif
Ben Cheng654325d2012-03-07 21:13:49 -0800[diff] [blame^]653/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */