| Raghu Gandham | 82fa43f | 2012-03-27 11:37:17 -0700 | [diff] [blame] | 1 | /**************************************************************************** |
| 2 | **************************************************************************** |
| 3 | *** |
| 4 | *** This header was automatically generated from a Linux kernel header |
| 5 | *** of the same name, to make information necessary for userspace to |
| 6 | *** call into the kernel available to libc. It contains only constants, |
| 7 | *** structures, and macros generated from the original header, and thus, |
| 8 | *** contains no copyrightable information. |
| 9 | *** |
| 10 | *** To edit the content of this header, modify the corresponding |
| 11 | *** source file (e.g. under external/kernel-headers/original/) then |
| 12 | *** run bionic/libc/kernel/tools/update_all.py |
| 13 | *** |
| 14 | *** Any manual change here will be lost the next time this script will |
| 15 | *** be run. You've been warned! |
| 16 | *** |
| 17 | **************************************************************************** |
| 18 | ****************************************************************************/ |
| 19 | #ifndef __ASM_MIPS_BOARDS_MALTA_H |
| 20 | #define __ASM_MIPS_BOARDS_MALTA_H |
| 21 | #include <asm/addrspace.h> |
| 22 | #include <asm/io.h> |
| 23 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 24 | #include <asm/mips-boards/msc01_pci.h> |
| 25 | #include <asm/gt64120.h> |
| 26 | #define MIPS_MSC01_IC_REG_BASE 0x1bc40000 |
| 27 | #define MIPS_SOCITSC_IC_REG_BASE 0x1ffa0000 |
| 28 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 29 | #define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS) |
| 30 | #define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0x10000)) |
| 31 | #define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL) |
| 32 | #define GCMP_BASE_ADDR 0x1fbf8000 |
| 33 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 34 | #define GCMP_ADDRSPACE_SZ (256 * 1024) |
| 35 | #define GIC_BASE_ADDR 0x1bdc0000 |
| 36 | #define GIC_ADDRSPACE_SZ (128 * 1024) |
| 37 | #define MSC01_BIU_REG_BASE 0x1bc80000 |
| 38 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 39 | #define MSC01_BIU_ADDRSPACE_SZ (256 * 1024) |
| 40 | #define MSC01_SC_CFG_OFS 0x0110 |
| 41 | #define MSC01_SC_CFG_GICPRES_MSK 0x00000004 |
| 42 | #define MSC01_SC_CFG_GICPRES_SHF 2 |
| 43 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 44 | #define MSC01_SC_CFG_GICENA_SHF 3 |
| 45 | #define MALTA_RTC_ADR_REG 0x70 |
| 46 | #define MALTA_RTC_DAT_REG 0x71 |
| 47 | #define SMSC_CONFIG_REG 0x3f0 |
| 48 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 49 | #define SMSC_DATA_REG 0x3f1 |
| 50 | #define SMSC_CONFIG_DEVNUM 0x7 |
| 51 | #define SMSC_CONFIG_ACTIVATE 0x30 |
| 52 | #define SMSC_CONFIG_ENTER 0x55 |
| 53 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 54 | #define SMSC_CONFIG_EXIT 0xaa |
| 55 | #define SMSC_CONFIG_DEVNUM_FLOPPY 0 |
| 56 | #define SMSC_CONFIG_ACTIVATE_ENABLE 1 |
| 57 | #define SMSC_WRITE(x, a) outb(x, a) |
| 58 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 59 | #define MALTA_JMPRS_REG 0x1f000210 |
| 60 | #endif |