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review.blissroms.org / platform_bionic / 73c04b32691cb344cb60289a646ded8fc551d09e / . / libc / arch-arm / bionic / strcpy.S
blob: 70c353f7902c4c3c5ac7e9e2ccc2c3abdbbe3452 [file] [log] [blame]
Jim Huang73c04b32010-08-10 17:23:39 +0800[diff] [blame^]1/*
2 * Copyright (C) 2010 The Android Open Source Project
3 * Copyright (c) 2008 ARM Ltd
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the company may not be used to endorse or promote
15 * products derived from this software without specific prior written
16 * permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
24 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
25 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
26 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Android adaptation and tweak by Jim Huang <jserv@0xlab.org>.
30 */
31
32#include <machine/cpu-features.h>
33
34 .text
35
36 .global strcpy
37 .type strcpy, %function
38 .align 4
39
40strcpy:
41 .fnstart
42 PLD(r1, #0)
43 eor r2, r0, r1
44 mov ip, r0
45 tst r2, #3
46 bne 4f
47 tst r1, #3
48 bne 3f
495:
50 str r5, [sp, #-4]!
51 mov r5, #0x01
52 orr r5, r5, r5, lsl #8
53 orr r5, r5, r5, lsl #16
54
55 str r4, [sp, #-4]!
56 tst r1, #4
57 ldr r3, [r1], #4
58 beq 2f
59 sub r2, r3, r5
60 bics r2, r2, r3
61 tst r2, r5, lsl #7
62 itt eq
63 streq r3, [ip], #4
64 ldreq r3, [r1], #4
65 bne 1f
66 /* Inner loop. We now know that r1 is 64-bit aligned, so we
67 can safely fetch up to two words. This allows us to avoid
68 load stalls. */
69 .p2align 2
702:
71 PLD(r1, #8)
72 ldr r4, [r1], #4
73 sub r2, r3, r5
74 bics r2, r2, r3
75 tst r2, r5, lsl #7
76 sub r2, r4, r5
77 bne 1f
78 str r3, [ip], #4
79 bics r2, r2, r4
80 tst r2, r5, lsl #7
81 itt eq
82 ldreq r3, [r1], #4
83 streq r4, [ip], #4
84 beq 2b
85 mov r3, r4
861:
87#ifdef __ARMEB__
88 rors r3, r3, #24
89#endif
90 strb r3, [ip], #1
91 tst r3, #0xff
92#ifdef __ARMEL__
93 ror r3, r3, #8
94#endif
95 bne 1b
96 ldr r4, [sp], #4
97 ldr r5, [sp], #4
98 bx lr
99
100 /* Strings have the same offset from word alignment, but it's
101 not zero. */
1023:
103 tst r1, #1
104 beq 1f
105 ldrb r2, [r1], #1
106 strb r2, [ip], #1
107 cmp r2, #0
108 it eq
109 bxeq lr
1101:
111 tst r1, #2
112 beq 5b
113 ldrh r2, [r1], #2
114#ifdef __ARMEB__
115 tst r2, #0xff00
116 iteet ne
117 strneh r2, [ip], #2
118 lsreq r2, r2, #8
119 streqb r2, [ip]
120 tstne r2, #0xff
121#else
122 tst r2, #0xff
123 itet ne
124 strneh r2, [ip], #2
125 streqb r2, [ip]
126 tstne r2, #0xff00
127#endif
128 bne 5b
129 bx lr
130
131 /* src and dst do not have a common word-alignement. Fall back to
132 byte copying. */
1334:
134 ldrb r2, [r1], #1
135 strb r2, [ip], #1
136 cmp r2, #0
137 bne 4b
138 bx lr