Gitiles
Code Review Sign In
review.blissroms.org / platform_bionic / 82d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0f / . / libc / kernel / uapi / drm / exynos_drm.h
blob: 85e7f0413442eb784e38470429d2c6cee030a544 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_EXYNOS_DRM_H_
20#define _UAPI_EXYNOS_DRM_H_
21#include <drm/drm.h>
22struct drm_exynos_gem_create {
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24 uint64_t size;
25 unsigned int flags;
26 unsigned int handle;
27};
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]29struct drm_exynos_gem_info {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]30 unsigned int handle;
31 unsigned int flags;
32 uint64_t size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]34};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]35struct drm_exynos_vidi_connection {
36 unsigned int connection;
37 unsigned int extensions;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]39 uint64_t edid;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]40};
41enum e_drm_exynos_gem_mem_type {
42 EXYNOS_BO_CONTIG = 0 << 0,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]44 EXYNOS_BO_NONCONTIG = 1 << 0,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]45 EXYNOS_BO_NONCACHABLE = 0 << 1,
46 EXYNOS_BO_CACHABLE = 1 << 1,
47 EXYNOS_BO_WC = 1 << 2,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]49 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]50 EXYNOS_BO_WC
51};
52struct drm_exynos_g2d_get_ver {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]54 __u32 major;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]55 __u32 minor;
56};
57struct drm_exynos_g2d_cmd {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]59 __u32 offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]60 __u32 data;
61};
62enum drm_exynos_g2d_buf_type {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]64 G2D_BUF_USERPTR = 1 << 31,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]65};
66enum drm_exynos_g2d_event_type {
67 G2D_EVENT_NOT,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]69 G2D_EVENT_NONSTOP,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]70 G2D_EVENT_STOP,
71};
72struct drm_exynos_g2d_userptr {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]74 unsigned long userptr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]75 unsigned long size;
76};
77struct drm_exynos_g2d_set_cmdlist {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]79 __u64 cmd;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]80 __u64 cmd_buf;
81 __u32 cmd_nr;
82 __u32 cmd_buf_nr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]84 __u64 event_type;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]85 __u64 user_data;
86};
87struct drm_exynos_g2d_exec {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]89 __u64 async;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]90};
91enum drm_exynos_ops_id {
92 EXYNOS_DRM_OPS_SRC,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]94 EXYNOS_DRM_OPS_DST,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]95 EXYNOS_DRM_OPS_MAX,
96};
97struct drm_exynos_sz {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]99 __u32 hsize;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]100 __u32 vsize;
101};
102struct drm_exynos_pos {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]104 __u32 x;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]105 __u32 y;
106 __u32 w;
107 __u32 h;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]109};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]110enum drm_exynos_flip {
111 EXYNOS_DRM_FLIP_NONE = (0 << 0),
112 EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]114 EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]115 EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL |
116 EXYNOS_DRM_FLIP_HORIZONTAL,
117};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]119enum drm_exynos_degree {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]120 EXYNOS_DRM_DEGREE_0,
121 EXYNOS_DRM_DEGREE_90,
122 EXYNOS_DRM_DEGREE_180,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]124 EXYNOS_DRM_DEGREE_270,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]125};
126enum drm_exynos_planer {
127 EXYNOS_DRM_PLANAR_Y,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]129 EXYNOS_DRM_PLANAR_CB,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]130 EXYNOS_DRM_PLANAR_CR,
131 EXYNOS_DRM_PLANAR_MAX,
132};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]134struct drm_exynos_ipp_prop_list {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]135 __u32 version;
136 __u32 ipp_id;
137 __u32 count;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]139 __u32 writeback;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]140 __u32 flip;
141 __u32 degree;
142 __u32 csc;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]144 __u32 crop;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]145 __u32 scale;
146 __u32 refresh_min;
147 __u32 refresh_max;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]149 __u32 reserved;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]150 struct drm_exynos_sz crop_min;
151 struct drm_exynos_sz crop_max;
152 struct drm_exynos_sz scale_min;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]154 struct drm_exynos_sz scale_max;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]155};
156struct drm_exynos_ipp_config {
157 enum drm_exynos_ops_id ops_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]159 enum drm_exynos_flip flip;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]160 enum drm_exynos_degree degree;
161 __u32 fmt;
162 struct drm_exynos_sz sz;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]164 struct drm_exynos_pos pos;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]165};
166enum drm_exynos_ipp_cmd {
167 IPP_CMD_NONE,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]169 IPP_CMD_M2M,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]170 IPP_CMD_WB,
171 IPP_CMD_OUTPUT,
172 IPP_CMD_MAX,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]174};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]175struct drm_exynos_ipp_property {
176 struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
177 enum drm_exynos_ipp_cmd cmd;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]179 __u32 ipp_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]180 __u32 prop_id;
181 __u32 refresh_rate;
182};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]184enum drm_exynos_ipp_buf_type {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]185 IPP_BUF_ENQUEUE,
186 IPP_BUF_DEQUEUE,
187};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]189struct drm_exynos_ipp_queue_buf {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]190 enum drm_exynos_ops_id ops_id;
191 enum drm_exynos_ipp_buf_type buf_type;
192 __u32 prop_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]194 __u32 buf_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]195 __u32 handle[EXYNOS_DRM_PLANAR_MAX];
196 __u32 reserved;
197 __u64 user_data;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]199};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]200enum drm_exynos_ipp_ctrl {
201 IPP_CTRL_PLAY,
202 IPP_CTRL_STOP,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]204 IPP_CTRL_PAUSE,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]205 IPP_CTRL_RESUME,
206 IPP_CTRL_MAX,
207};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]209struct drm_exynos_ipp_cmd_ctrl {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]210 __u32 prop_id;
211 enum drm_exynos_ipp_ctrl ctrl;
212};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]214#define DRM_EXYNOS_GEM_CREATE 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]215#define DRM_EXYNOS_GEM_GET 0x04
216#define DRM_EXYNOS_VIDI_CONNECTION 0x07
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]217#define DRM_EXYNOS_G2D_GET_VER 0x20
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]219#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
220#define DRM_EXYNOS_G2D_EXEC 0x22
221#define DRM_EXYNOS_IPP_GET_PROPERTY 0x30
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]222#define DRM_EXYNOS_IPP_SET_PROPERTY 0x31
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]224#define DRM_EXYNOS_IPP_QUEUE_BUF 0x32
225#define DRM_EXYNOS_IPP_CMD_CTRL 0x33
226#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]227#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]229#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]230#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
231#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
232#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]234#define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]235#define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
236#define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
237#define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]239#define DRM_EXYNOS_G2D_EVENT 0x80000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]240#define DRM_EXYNOS_IPP_EVENT 0x80000001
241struct drm_exynos_g2d_event {
242 struct drm_event base;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]244 __u64 user_data;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]245 __u32 tv_sec;
246 __u32 tv_usec;
247 __u32 cmdlist_no;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]249 __u32 reserved;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]250};
251struct drm_exynos_ipp_event {
252 struct drm_event base;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]254 __u64 user_data;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]255 __u32 tv_sec;
256 __u32 tv_usec;
257 __u32 prop_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]259 __u32 reserved;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]260 __u32 buf_id[EXYNOS_DRM_OPS_MAX];
261};
262#endif
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */