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review.blissroms.org / platform_bionic / 8cb52b056cfc302e05304d847c4228dff15715cf / . / libc / kernel / uapi / drm / tegra_drm.h
blob: 80dc67167849fa10db1f8214f24215b3652d3ab7 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_TEGRA_DRM_H_
20#define _UAPI_TEGRA_DRM_H_
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]21struct drm_tegra_gem_create {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]22 __u64 size;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]24 __u32 flags;
25 __u32 handle;
26};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]27struct drm_tegra_gem_mmap {
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]29 __u32 handle;
30 __u32 offset;
31};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]32struct drm_tegra_syncpt_read {
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]34 __u32 id;
35 __u32 value;
36};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]37struct drm_tegra_syncpt_incr {
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]39 __u32 id;
40 __u32 pad;
41};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]42struct drm_tegra_syncpt_wait {
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]44 __u32 id;
45 __u32 thresh;
46 __u32 timeout;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]47 __u32 value;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]49};
50#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
51struct drm_tegra_open_channel {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]52 __u32 client;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]54 __u32 pad;
55 __u64 context;
56};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]57struct drm_tegra_close_channel {
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]59 __u64 context;
60};
61struct drm_tegra_get_syncpt {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]62 __u64 context;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]64 __u32 index;
65 __u32 id;
66};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]67struct drm_tegra_syncpt {
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]69 __u32 id;
70 __u32 incrs;
71};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]72struct drm_tegra_cmdbuf {
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]74 __u32 handle;
75 __u32 offset;
76 __u32 words;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]77 __u32 pad;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]79};
80struct drm_tegra_reloc {
81 struct {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]82 __u32 handle;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]84 __u32 offset;
85 } cmdbuf;
86 struct {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]87 __u32 handle;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]89 __u32 offset;
90 } target;
91 __u32 shift;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]92 __u32 pad;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]94};
95struct drm_tegra_waitchk {
96 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]97 __u32 offset;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]99 __u32 syncpt;
100 __u32 thresh;
101};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]102struct drm_tegra_submit {
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]104 __u64 context;
105 __u32 num_syncpts;
106 __u32 num_cmdbufs;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]107 __u32 num_relocs;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]109 __u32 num_waitchks;
110 __u32 waitchk_mask;
111 __u32 timeout;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]112 __u32 pad;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]114 __u64 syncpts;
115 __u64 cmdbufs;
116 __u64 relocs;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]117 __u64 waitchks;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]119 __u32 fence;
120 __u32 reserved[5];
121};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]122#define DRM_TEGRA_GEM_CREATE 0x00
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]124#define DRM_TEGRA_GEM_MMAP 0x01
125#define DRM_TEGRA_SYNCPT_READ 0x02
126#define DRM_TEGRA_SYNCPT_INCR 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]127#define DRM_TEGRA_SYNCPT_WAIT 0x04
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]129#define DRM_TEGRA_OPEN_CHANNEL 0x05
130#define DRM_TEGRA_CLOSE_CHANNEL 0x06
131#define DRM_TEGRA_GET_SYNCPT 0x07
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]132#define DRM_TEGRA_SUBMIT 0x08
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]134#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
135#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
136#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]137#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]139#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
140#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
141#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]142#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame^]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]144#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
145#endif