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review.blissroms.org / platform_bionic / 8fbf8deb34d0bd1efc22d2b67d660ad32ecc4c5c / . / libc / kernel / arch-mips / asm / sn / ioc3.h
blob: 46ba4dddb9f619fe0ebfca1c8b515cd246431105 [file] [log] [blame]
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _IOC3_H
20#define _IOC3_H
21#include <linux/types.h>
22typedef volatile struct ioc3_uartregs {
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24 union {
25 volatile u8 rbr;
26 volatile u8 thr;
27 volatile u8 dll;
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
29 } u1;
30 union {
31 volatile u8 ier;
32 volatile u8 dlm;
33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
34 } u2;
35 union {
36 volatile u8 iir;
37 volatile u8 fcr;
38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
39 } u3;
40 volatile u8 iu_lcr;
41 volatile u8 iu_mcr;
42 volatile u8 iu_lsr;
43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
44 volatile u8 iu_msr;
45 volatile u8 iu_scr;
46} ioc3_uregs_t;
47#define iu_rbr u1.rbr
48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
49#define iu_thr u1.thr
50#define iu_dll u1.dll
51#define iu_ier u2.ier
52#define iu_dlm u2.dlm
53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
54#define iu_iir u3.iir
55#define iu_fcr u3.fcr
56struct ioc3_sioregs {
57 volatile u8 fill[0x141];
58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
59 volatile u8 uartc;
60 volatile u8 kbdcg;
61 volatile u8 fill0[0x150 - 0x142 - 1];
62 volatile u8 pp_data;
63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
64 volatile u8 pp_dsr;
65 volatile u8 pp_dcr;
66 volatile u8 fill1[0x158 - 0x152 - 1];
67 volatile u8 pp_fifa;
68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
69 volatile u8 pp_cfgb;
70 volatile u8 pp_ecr;
71 volatile u8 fill2[0x168 - 0x15a - 1];
72 volatile u8 rtcad;
73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
74 volatile u8 rtcdat;
75 volatile u8 fill3[0x170 - 0x169 - 1];
76 struct ioc3_uartregs uartb;
77 struct ioc3_uartregs uarta;
78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
79};
80struct ioc3 {
81 volatile u32 pad0[7];
82 volatile u32 sio_ir;
83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
84 volatile u32 sio_ies;
85 volatile u32 sio_iec;
86 volatile u32 sio_cr;
87 volatile u32 int_out;
88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
89 volatile u32 mcr;
90 volatile u32 gpcr_s;
91 volatile u32 gpcr_c;
92 volatile u32 gpdr;
93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
94 volatile u32 gppr_0;
95 volatile u32 gppr_1;
96 volatile u32 gppr_2;
97 volatile u32 gppr_3;
98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
99 volatile u32 gppr_4;
100 volatile u32 gppr_5;
101 volatile u32 gppr_6;
102 volatile u32 gppr_7;
103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
104 volatile u32 gppr_8;
105 volatile u32 gppr_9;
106 volatile u32 gppr_10;
107 volatile u32 gppr_11;
108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
109 volatile u32 gppr_12;
110 volatile u32 gppr_13;
111 volatile u32 gppr_14;
112 volatile u32 gppr_15;
113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
114 volatile u32 ppbr_h_a;
115 volatile u32 ppbr_l_a;
116 volatile u32 ppcr_a;
117 volatile u32 ppcr;
118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
119 volatile u32 ppbr_h_b;
120 volatile u32 ppbr_l_b;
121 volatile u32 ppcr_b;
122 volatile u32 km_csr;
123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
124 volatile u32 k_rd;
125 volatile u32 m_rd;
126 volatile u32 k_wd;
127 volatile u32 m_wd;
128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
129 volatile u32 sbbr_h;
130 volatile u32 sbbr_l;
131 volatile u32 sscr_a;
132 volatile u32 stpir_a;
133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
134 volatile u32 stcir_a;
135 volatile u32 srpir_a;
136 volatile u32 srcir_a;
137 volatile u32 srtr_a;
138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
139 volatile u32 shadow_a;
140 volatile u32 sscr_b;
141 volatile u32 stpir_b;
142 volatile u32 stcir_b;
143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
144 volatile u32 srpir_b;
145 volatile u32 srcir_b;
146 volatile u32 srtr_b;
147 volatile u32 shadow_b;
148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
149 volatile u32 emcr;
150 volatile u32 eisr;
151 volatile u32 eier;
152 volatile u32 ercsr;
153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
154 volatile u32 erbr_h;
155 volatile u32 erbr_l;
156 volatile u32 erbar;
157 volatile u32 ercir;
158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
159 volatile u32 erpir;
160 volatile u32 ertr;
161 volatile u32 etcsr;
162 volatile u32 ersr;
163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
164 volatile u32 etcdc;
165 volatile u32 ebir;
166 volatile u32 etbr_h;
167 volatile u32 etbr_l;
168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
169 volatile u32 etcir;
170 volatile u32 etpir;
171 volatile u32 emar_h;
172 volatile u32 emar_l;
173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
174 volatile u32 ehar_h;
175 volatile u32 ehar_l;
176 volatile u32 micr;
177 volatile u32 midr_r;
178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
179 volatile u32 midr_w;
180 volatile u32 pad1[(0x20000 - 0x00154) / 4];
181 struct ioc3_sioregs sregs;
182 volatile u32 pad2[(0x40000 - 0x20180) / 4];
183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
184 volatile u32 ssram[(0x80000 - 0x40000) / 4];
185};
186struct ioc3_erxbuf {
187 u32 w0;
188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
189 u32 err;
190};
191#define ERXBUF_IPCKSUM_MASK 0x0000ffff
192#define ERXBUF_BYTECNT_MASK 0x07ff0000
193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
194#define ERXBUF_BYTECNT_SHIFT 16
195#define ERXBUF_V 0x80000000
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]196#define ERXBUF_CRCERR 0x00000001
197#define ERXBUF_FRAMERR 0x00000002
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]199#define ERXBUF_CODERR 0x00000004
200#define ERXBUF_INVPREAMB 0x00000008
201#define ERXBUF_LOLEN 0x00007000
202#define ERXBUF_HILEN 0x03ff0000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]204#define ERXBUF_MULTICAST 0x04000000
205#define ERXBUF_BROADCAST 0x08000000
206#define ERXBUF_LONGEVENT 0x10000000
207#define ERXBUF_BADPKT 0x20000000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]209#define ERXBUF_GOODPKT 0x40000000
210#define ERXBUF_CARRIER 0x80000000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]211#define ETXD_DATALEN 104
212struct ioc3_etxd {
213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
214 u32 cmd;
215 u32 bufcnt;
216 u64 p1;
217 u64 p2;
218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
219 u8 data[ETXD_DATALEN];
220};
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]221#define ETXD_BYTECNT_MASK 0x000007ff
222#define ETXD_INTWHENDONE 0x00001000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]224#define ETXD_D0V 0x00010000
225#define ETXD_B1V 0x00020000
226#define ETXD_B2V 0x00040000
227#define ETXD_DOCHECKSUM 0x00080000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]229#define ETXD_CHKOFF_MASK 0x07f00000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]230#define ETXD_CHKOFF_SHIFT 20
231#define ETXD_D0CNT_MASK 0x0000007f
232#define ETXD_B1CNT_MASK 0x0007ff00
233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
234#define ETXD_B1CNT_SHIFT 8
235#define ETXD_B2CNT_MASK 0x7ff00000
236#define ETXD_B2CNT_SHIFT 20
237#define IOC3_BYTEBUS_DEV0 0x80000L
238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
239#define IOC3_BYTEBUS_DEV1 0xa0000L
240#define IOC3_BYTEBUS_DEV2 0xc0000L
241#define IOC3_BYTEBUS_DEV3 0xe0000L
242#define IOC3_SIO_BASE 0x20000
243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]244#define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141)
245#define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142)
246#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE)
247#define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168)
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]249#define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE)
250#define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE)
251#define IOC3_SSRAM IOC3_RAM_OFF
252#define IOC3_SSRAM_LEN 0x40000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]254#define IOC3_SSRAM_DM 0x0000ffff
255#define IOC3_SSRAM_PM 0x00010000
256#define PCI_SCR_PAR_RESP_EN 0x00000040
257#define PCI_SCR_SERR_EN 0x00000100
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]259#define PCI_SCR_DROP_MODE_EN 0x00008000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]260#define PCI_SCR_RX_SERR (0x1 << 16)
261#define PCI_SCR_DROP_MODE (0x1 << 17)
262#define PCI_SCR_SIG_PAR_ERR (0x1 << 24)
263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
264#define PCI_SCR_SIG_TAR_ABRT (0x1 << 27)
265#define PCI_SCR_RX_TAR_ABRT (0x1 << 28)
266#define PCI_SCR_SIG_MST_ABRT (0x1 << 29)
267#define PCI_SCR_SIG_SERR (0x1 << 30)
268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
269#define PCI_SCR_PAR_ERR (0x1 << 31)
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]270#define KM_CSR_K_WRT_PEND 0x00000001
271#define KM_CSR_M_WRT_PEND 0x00000002
272#define KM_CSR_K_LCB 0x00000004
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]274#define KM_CSR_M_LCB 0x00000008
275#define KM_CSR_K_DATA 0x00000010
276#define KM_CSR_K_CLK 0x00000020
277#define KM_CSR_K_PULL_DATA 0x00000040
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]279#define KM_CSR_K_PULL_CLK 0x00000080
280#define KM_CSR_M_DATA 0x00000100
281#define KM_CSR_M_CLK 0x00000200
282#define KM_CSR_M_PULL_DATA 0x00000400
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]284#define KM_CSR_M_PULL_CLK 0x00000800
285#define KM_CSR_EMM_MODE 0x00001000
286#define KM_CSR_SIM_MODE 0x00002000
287#define KM_CSR_K_SM_IDLE 0x00004000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]289#define KM_CSR_M_SM_IDLE 0x00008000
290#define KM_CSR_K_TO 0x00010000
291#define KM_CSR_M_TO 0x00020000
292#define KM_CSR_K_TO_EN 0x00040000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]294#define KM_CSR_M_TO_EN 0x00080000
295#define KM_CSR_K_CLAMP_ONE 0x00100000
296#define KM_CSR_M_CLAMP_ONE 0x00200000
297#define KM_CSR_K_CLAMP_THREE 0x00400000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]299#define KM_CSR_M_CLAMP_THREE 0x00800000
300#define KM_RD_DATA_2 0x000000ff
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]301#define KM_RD_DATA_2_SHIFT 0
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]302#define KM_RD_DATA_1 0x0000ff00
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
304#define KM_RD_DATA_1_SHIFT 8
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]305#define KM_RD_DATA_0 0x00ff0000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]306#define KM_RD_DATA_0_SHIFT 16
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]307#define KM_RD_FRAME_ERR_2 0x01000000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]309#define KM_RD_FRAME_ERR_1 0x02000000
310#define KM_RD_FRAME_ERR_0 0x04000000
311#define KM_RD_KBD_MSE 0x08000000
312#define KM_RD_OFLO 0x10000000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]314#define KM_RD_VALID_2 0x20000000
315#define KM_RD_VALID_1 0x40000000
316#define KM_RD_VALID_0 0x80000000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]317#define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2)
318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]319#define KM_WD_WRT_DATA 0x000000ff
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]320#define KM_WD_WRT_DATA_SHIFT 0
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]321#define RXSB_OVERRUN 0x01
322#define RXSB_PAR_ERR 0x02
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]324#define RXSB_FRAME_ERR 0x04
325#define RXSB_BREAK 0x08
326#define RXSB_CTS 0x10
327#define RXSB_DCD 0x20
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]329#define RXSB_MODEM_VALID 0x40
330#define RXSB_DATA_VALID 0x80
331#define TXCB_INT_WHEN_DONE 0x20
332#define TXCB_INVALID 0x00
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]334#define TXCB_VALID 0x40
335#define TXCB_MCR 0x80
336#define TXCB_DELAY 0xc0
337#define SBBR_L_SIZE 0x00000001
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]339#define SBBR_L_BASE 0xfffff000
340#define SSCR_RX_THRESHOLD 0x000001ff
341#define SSCR_TX_TIMER_BUSY 0x00010000
342#define SSCR_HFC_EN 0x00020000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]344#define SSCR_RX_RING_DCD 0x00040000
345#define SSCR_RX_RING_CTS 0x00080000
346#define SSCR_HIGH_SPD 0x00100000
347#define SSCR_DIAG 0x00200000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]349#define SSCR_RX_DRAIN 0x08000000
350#define SSCR_DMA_EN 0x10000000
351#define SSCR_DMA_PAUSE 0x20000000
352#define SSCR_PAUSE_STATE 0x40000000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]354#define SSCR_RESET 0x80000000
355#define PROD_CONS_PTR_4K 0x00000ff8
356#define PROD_CONS_PTR_1K 0x000003f8
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]357#define PROD_CONS_PTR_OFF 3
358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]359#define SRCIR_ARM 0x80000000
360#define SRPIR_BYTE_CNT 0x07000000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]361#define SRPIR_BYTE_CNT_SHIFT 24
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]362#define STCIR_BYTE_CNT 0x0f000000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
364#define STCIR_BYTE_CNT_SHIFT 24
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]365#define SHADOW_DR 0x00000001
366#define SHADOW_OE 0x00000002
367#define SHADOW_PE 0x00000004
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]369#define SHADOW_FE 0x00000008
370#define SHADOW_BI 0x00000010
371#define SHADOW_THRE 0x00000020
372#define SHADOW_TEMT 0x00000040
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]374#define SHADOW_RFCE 0x00000080
375#define SHADOW_DCTS 0x00010000
376#define SHADOW_DDCD 0x00080000
377#define SHADOW_CTS 0x00100000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]379#define SHADOW_DCD 0x00800000
380#define SHADOW_DTR 0x01000000
381#define SHADOW_RTS 0x02000000
382#define SHADOW_OUT1 0x04000000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]384#define SHADOW_OUT2 0x08000000
385#define SHADOW_LOOP 0x10000000
386#define SRTR_CNT 0x00000fff
387#define SRTR_CNT_VAL 0x0fff0000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
389#define SRTR_CNT_VAL_SHIFT 16
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]390#define SRTR_HZ 16000
391#define SIO_IR_SA_TX_MT 0x00000001
392#define SIO_IR_SA_RX_FULL 0x00000002
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]394#define SIO_IR_SA_RX_HIGH 0x00000004
395#define SIO_IR_SA_RX_TIMER 0x00000008
396#define SIO_IR_SA_DELTA_DCD 0x00000010
397#define SIO_IR_SA_DELTA_CTS 0x00000020
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]399#define SIO_IR_SA_INT 0x00000040
400#define SIO_IR_SA_TX_EXPLICIT 0x00000080
401#define SIO_IR_SA_MEMERR 0x00000100
402#define SIO_IR_SB_TX_MT 0x00000200
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]404#define SIO_IR_SB_RX_FULL 0x00000400
405#define SIO_IR_SB_RX_HIGH 0x00000800
406#define SIO_IR_SB_RX_TIMER 0x00001000
407#define SIO_IR_SB_DELTA_DCD 0x00002000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]409#define SIO_IR_SB_DELTA_CTS 0x00004000
410#define SIO_IR_SB_INT 0x00008000
411#define SIO_IR_SB_TX_EXPLICIT 0x00010000
412#define SIO_IR_SB_MEMERR 0x00020000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]414#define SIO_IR_PP_INT 0x00040000
415#define SIO_IR_PP_INTA 0x00080000
416#define SIO_IR_PP_INTB 0x00100000
417#define SIO_IR_PP_MEMERR 0x00200000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]419#define SIO_IR_KBD_INT 0x00400000
420#define SIO_IR_RT_INT 0x08000000
421#define SIO_IR_GEN_INT1 0x10000000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]422#define SIO_IR_GEN_INT_SHIFT 28
423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
424#define SIO_IR_SA (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | SIO_IR_SA_MEMERR)
425#define SIO_IR_SB (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | SIO_IR_SB_MEMERR)
426#define SIO_IR_PP (SIO_IR_PP_INT | SIO_IR_PP_INTA | SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
427#define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
429#define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & PCI_INW(&((mem)->sio_ies_ro)))
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]430#define SIO_CR_SIO_RESET 0x00000001
431#define SIO_CR_SER_A_BASE 0x000000fe
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]432#define SIO_CR_SER_A_BASE_SHIFT 1
433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]434#define SIO_CR_SER_B_BASE 0x00007f00
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]435#define SIO_CR_SER_B_BASE_SHIFT 8
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]436#define SIO_SR_CMD_PULSE 0x00078000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]437#define SIO_CR_CMD_PULSE_SHIFT 15
438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]439#define SIO_CR_ARB_DIAG 0x00380000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]440#define SIO_CR_ARB_DIAG_TXA 0x00000000
441#define SIO_CR_ARB_DIAG_RXA 0x00080000
442#define SIO_CR_ARB_DIAG_TXB 0x00100000
443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
444#define SIO_CR_ARB_DIAG_RXB 0x00180000
445#define SIO_CR_ARB_DIAG_PP 0x00200000
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]446#define SIO_CR_ARB_DIAG_IDLE 0x00400000
447#define INT_OUT_COUNT 0x0000ffff
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]449#define INT_OUT_MODE 0x00070000
450#define INT_OUT_MODE_0 0x00000000
451#define INT_OUT_MODE_1 0x00040000
452#define INT_OUT_MODE_1PULSE 0x00050000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]454#define INT_OUT_MODE_PULSES 0x00060000
455#define INT_OUT_MODE_SQW 0x00070000
456#define INT_OUT_DIAG 0x40000000
457#define INT_OUT_INT_OUT 0x80000000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]459#define INT_OUT_NS_PER_TICK (30 * 260)
460#define INT_OUT_TICKS_PER_PULSE 3
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]461#define INT_OUT_US_TO_COUNT(x) (((x) * 10 + INT_OUT_NS_PER_TICK / 200) * 100 / INT_OUT_NS_PER_TICK - 1)
462#define INT_OUT_COUNT_TO_US(x) (((x) + 1) * INT_OUT_NS_PER_TICK / 1000)
463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]464#define INT_OUT_MIN_TICKS 3
465#define INT_OUT_MAX_TICKS INT_OUT_COUNT
466#define GPCR_DIR 0x000000ff
467#define GPCR_DIR_PIN(x) (1<<(x))
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]469#define GPCR_EDGE 0x000f0000
470#define GPCR_EDGE_PIN(x) (1<<((x)+15))
471#define GPCR_INT_OUT_EN 0x00100000
472#define GPCR_MLAN_EN 0x00200000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]474#define GPCR_DIR_SERA_XCVR 0x00000080
475#define GPCR_DIR_SERB_XCVR 0x00000040
476#define GPCR_DIR_PHY_RST 0x00000020
477#define GPCR_PHY_RESET 0x20
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]479#define GPCR_UARTB_MODESEL 0x40
480#define GPCR_UARTA_MODESEL 0x80
481#define GPPR_PHY_RESET_PIN 5
482#define GPPR_UARTB_MODESEL_PIN 6
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]484#define GPPR_UARTA_MODESEL_PIN 7
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]485#define EMCR_DUPLEX 0x00000001
486#define EMCR_PROMISC 0x00000002
487#define EMCR_PADEN 0x00000004
488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
489#define EMCR_RXOFF_MASK 0x000001f8
490#define EMCR_RXOFF_SHIFT 3
491#define EMCR_RAMPAR 0x00000200
492#define EMCR_BADPAR 0x00000800
493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
494#define EMCR_BUFSIZ 0x00001000
495#define EMCR_TXDMAEN 0x00002000
496#define EMCR_TXEN 0x00004000
497#define EMCR_RXDMAEN 0x00008000
498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
499#define EMCR_RXEN 0x00010000
500#define EMCR_LOOPBACK 0x00020000
501#define EMCR_ARB_DIAG 0x001c0000
502#define EMCR_ARB_DIAG_IDLE 0x00200000
503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
504#define EMCR_RST 0x80000000
505#define EISR_RXTIMERINT 0x00000001
506#define EISR_RXTHRESHINT 0x00000002
507#define EISR_RXOFLO 0x00000004
508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
509#define EISR_RXBUFOFLO 0x00000008
510#define EISR_RXMEMERR 0x00000010
511#define EISR_RXPARERR 0x00000020
512#define EISR_TXEMPTY 0x00010000
513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
514#define EISR_TXRTRY 0x00020000
515#define EISR_TXEXDEF 0x00040000
516#define EISR_TXLCOL 0x00080000
517#define EISR_TXGIANT 0x00100000
518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
519#define EISR_TXBUFUFLO 0x00200000
520#define EISR_TXEXPLICIT 0x00400000
521#define EISR_TXCOLLWRAP 0x00800000
522#define EISR_TXDEFERWRAP 0x01000000
523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
524#define EISR_TXMEMERR 0x02000000
525#define EISR_TXPARERR 0x04000000
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]526#define ERCSR_THRESH_MASK 0x000001ff
527#define ERCSR_RX_TMR 0x40000000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]529#define ERCSR_DIAG_OFLO 0x80000000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]530#define ERBR_ALIGNMENT 4096
531#define ERBR_L_RXRINGBASE_MASK 0xfffff000
532#define ERBAR_BARRIER_BIT 0x0100
533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
534#define ERBAR_RXBARR_MASK 0xffff0000
535#define ERBAR_RXBARR_SHIFT 16
536#define ERCIR_RXCONSUME_MASK 0x00000fff
537#define ERPIR_RXPRODUCE_MASK 0x00000fff
538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
539#define ERPIR_ARM 0x80000000
540#define ERTR_CNT_MASK 0x000007ff
541#define ETCSR_IPGT_MASK 0x0000007f
542#define ETCSR_IPGR1_MASK 0x00007f00
543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
544#define ETCSR_IPGR1_SHIFT 8
545#define ETCSR_IPGR2_MASK 0x007f0000
546#define ETCSR_IPGR2_SHIFT 16
547#define ETCSR_NOTXCLK 0x80000000
548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
549#define ETCDC_COLLCNT_MASK 0x0000ffff
550#define ETCDC_DEFERCNT_MASK 0xffff0000
551#define ETCDC_DEFERCNT_SHIFT 16
552#define ETBR_ALIGNMENT (64*1024)
553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
554#define ETBR_L_RINGSZ_MASK 0x00000001
555#define ETBR_L_RINGSZ128 0
556#define ETBR_L_RINGSZ512 1
557#define ETBR_L_TXRINGBASE_MASK 0xffffc000
558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
559#define ETCIR_TXCONSUME_MASK 0x0000ffff
560#define ETCIR_IDLE 0x80000000
561#define ETPIR_TXPRODUCE_MASK 0x0000ffff
562#define EBIR_TXBUFPROD_MASK 0x0000001f
563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
564#define EBIR_TXBUFCONS_MASK 0x00001f00
565#define EBIR_TXBUFCONS_SHIFT 8
566#define EBIR_RXBUFPROD_MASK 0x007fc000
567#define EBIR_RXBUFPROD_SHIFT 14
568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
569#define EBIR_RXBUFCONS_MASK 0xff800000
570#define EBIR_RXBUFCONS_SHIFT 23
571#define MICR_REGADDR_MASK 0x0000001f
572#define MICR_PHYADDR_MASK 0x000003e0
573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
574#define MICR_PHYADDR_SHIFT 5
575#define MICR_READTRIG 0x00000400
576#define MICR_BUSY 0x00000800
577#define MIDR_DATA_MASK 0x0000ffff
578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
579#define ERXBUF_IPCKSUM_MASK 0x0000ffff
580#define ERXBUF_BYTECNT_MASK 0x07ff0000
581#define ERXBUF_BYTECNT_SHIFT 16
582#define ERXBUF_V 0x80000000
583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]584#define ERXBUF_CRCERR 0x00000001
585#define ERXBUF_FRAMERR 0x00000002
586#define ERXBUF_CODERR 0x00000004
587#define ERXBUF_INVPREAMB 0x00000008
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]589#define ERXBUF_LOLEN 0x00007000
590#define ERXBUF_HILEN 0x03ff0000
591#define ERXBUF_MULTICAST 0x04000000
592#define ERXBUF_BROADCAST 0x08000000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]594#define ERXBUF_LONGEVENT 0x10000000
595#define ERXBUF_BADPKT 0x20000000
596#define ERXBUF_GOODPKT 0x40000000
597#define ERXBUF_CARRIER 0x80000000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]599#define ETXD_BYTECNT_MASK 0x000007ff
600#define ETXD_INTWHENDONE 0x00001000
601#define ETXD_D0V 0x00010000
602#define ETXD_B1V 0x00020000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Elliott Hughesc95eb572013-01-29 18:15:55 -0800[diff] [blame]604#define ETXD_B2V 0x00040000
605#define ETXD_DOCHECKSUM 0x00080000
606#define ETXD_CHKOFF_MASK 0x07f00000
Raghu Gandham82fa43f2012-03-27 11:37:17 -0700[diff] [blame]607#define ETXD_CHKOFF_SHIFT 20
608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
609#define ETXD_D0CNT_MASK 0x0000007f
610#define ETXD_B1CNT_MASK 0x0007ff00
611#define ETXD_B1CNT_SHIFT 8
612#define ETXD_B2CNT_MASK 0x7ff00000
613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
614#define ETXD_B2CNT_SHIFT 20
615typedef enum ioc3_subdevs_e {
616 ioc3_subdev_ether,
617 ioc3_subdev_generic,
618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
619 ioc3_subdev_nic,
620 ioc3_subdev_kbms,
621 ioc3_subdev_ttya,
622 ioc3_subdev_ttyb,
623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
624 ioc3_subdev_ecpp,
625 ioc3_subdev_rt,
626 ioc3_nsubdevs
627} ioc3_subdev_t;
628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
629#define IOC3_SDB_ETHER (1<<ioc3_subdev_ether)
630#define IOC3_SDB_GENERIC (1<<ioc3_subdev_generic)
631#define IOC3_SDB_NIC (1<<ioc3_subdev_nic)
632#define IOC3_SDB_KBMS (1<<ioc3_subdev_kbms)
633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
634#define IOC3_SDB_TTYA (1<<ioc3_subdev_ttya)
635#define IOC3_SDB_TTYB (1<<ioc3_subdev_ttyb)
636#define IOC3_SDB_ECPP (1<<ioc3_subdev_ecpp)
637#define IOC3_SDB_RT (1<<ioc3_subdev_rt)
638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
639#define IOC3_ALL_SUBDEVS ((1<<ioc3_nsubdevs)-1)
640#define IOC3_SDB_SERIAL (IOC3_SDB_TTYA|IOC3_SDB_TTYB)
641#define IOC3_STD_SUBDEVS IOC3_ALL_SUBDEVS
642#define IOC3_INTA_SUBDEVS IOC3_SDB_ETHER
643/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
644#define IOC3_INTB_SUBDEVS (IOC3_SDB_GENERIC|IOC3_SDB_KBMS|IOC3_SDB_SERIAL|IOC3_SDB_ECPP|IOC3_SDB_RT)
645#endif