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Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI__ASM_PTRACE_H
20#define _UAPI__ASM_PTRACE_H
21#include <linux/types.h>
22#include <asm/hwcap.h>
Christopher Ferris934ec942018-01-31 15:29:16 -080023#include <asm/sigcontext.h>
Ben Cheng655a7c02013-10-16 16:09:24 -070024#define PSR_MODE_EL0t 0x00000000
25#define PSR_MODE_EL1t 0x00000004
26#define PSR_MODE_EL1h 0x00000005
27#define PSR_MODE_EL2t 0x00000008
Ben Cheng655a7c02013-10-16 16:09:24 -070028#define PSR_MODE_EL2h 0x00000009
29#define PSR_MODE_EL3t 0x0000000c
30#define PSR_MODE_EL3h 0x0000000d
31#define PSR_MODE_MASK 0x0000000f
Ben Cheng655a7c02013-10-16 16:09:24 -070032#define PSR_MODE32_BIT 0x00000010
33#define PSR_F_BIT 0x00000040
34#define PSR_I_BIT 0x00000080
35#define PSR_A_BIT 0x00000100
Ben Cheng655a7c02013-10-16 16:09:24 -070036#define PSR_D_BIT 0x00000200
Christopher Ferris05d08e92016-02-04 13:16:38 -080037#define PSR_PAN_BIT 0x00400000
Christopher Ferris106b3a82016-08-24 12:15:38 -070038#define PSR_UAO_BIT 0x00800000
Christopher Ferris106b3a82016-08-24 12:15:38 -070039#define PSR_V_BIT 0x10000000
Christopher Ferris05d08e92016-02-04 13:16:38 -080040#define PSR_C_BIT 0x20000000
Ben Cheng655a7c02013-10-16 16:09:24 -070041#define PSR_Z_BIT 0x40000000
42#define PSR_N_BIT 0x80000000
Christopher Ferris106b3a82016-08-24 12:15:38 -070043#define PSR_f 0xff000000
Christopher Ferris05d08e92016-02-04 13:16:38 -080044#define PSR_s 0x00ff0000
Ben Cheng655a7c02013-10-16 16:09:24 -070045#define PSR_x 0x0000ff00
46#define PSR_c 0x000000ff
Christopher Ferris106b3a82016-08-24 12:15:38 -070047#ifndef __ASSEMBLY__
Christopher Ferris934ec942018-01-31 15:29:16 -080048#include <linux/prctl.h>
Christopher Ferris05d08e92016-02-04 13:16:38 -080049struct user_pt_regs {
Tao Baod7db5942015-01-28 10:07:51 -080050 __u64 regs[31];
51 __u64 sp;
Christopher Ferris106b3a82016-08-24 12:15:38 -070052 __u64 pc;
Christopher Ferris05d08e92016-02-04 13:16:38 -080053 __u64 pstate;
Ben Cheng655a7c02013-10-16 16:09:24 -070054};
55struct user_fpsimd_state {
Christopher Ferris106b3a82016-08-24 12:15:38 -070056 __uint128_t vregs[32];
Christopher Ferris05d08e92016-02-04 13:16:38 -080057 __u32 fpsr;
Tao Baod7db5942015-01-28 10:07:51 -080058 __u32 fpcr;
Christopher Ferris351a7962017-01-27 10:49:48 -080059 __u32 __reserved[2];
Christopher Ferris351a7962017-01-27 10:49:48 -080060};
Christopher Ferris106b3a82016-08-24 12:15:38 -070061struct user_hwdebug_state {
Christopher Ferris05d08e92016-02-04 13:16:38 -080062 __u32 dbg_info;
Tao Baod7db5942015-01-28 10:07:51 -080063 __u32 pad;
Christopher Ferris351a7962017-01-27 10:49:48 -080064 struct {
Christopher Ferris106b3a82016-08-24 12:15:38 -070065 __u64 addr;
Christopher Ferris05d08e92016-02-04 13:16:38 -080066 __u32 ctrl;
Tao Baod7db5942015-01-28 10:07:51 -080067 __u32 pad;
Christopher Ferris351a7962017-01-27 10:49:48 -080068 } dbg_regs[16];
Christopher Ferris106b3a82016-08-24 12:15:38 -070069};
Christopher Ferris934ec942018-01-31 15:29:16 -080070struct user_sve_header {
71 __u32 size;
72 __u32 max_size;
73 __u16 vl;
74 __u16 max_vl;
75 __u16 flags;
76 __u16 __reserved;
77};
78#define SVE_PT_REGS_MASK (1 << 0)
79#define SVE_PT_REGS_FPSIMD 0
80#define SVE_PT_REGS_SVE SVE_PT_REGS_MASK
81#define SVE_PT_VL_INHERIT (PR_SVE_VL_INHERIT >> 16)
82#define SVE_PT_VL_ONEXEC (PR_SVE_SET_VL_ONEXEC >> 16)
83#define SVE_PT_REGS_OFFSET ((sizeof(struct sve_context) + (SVE_VQ_BYTES - 1)) / SVE_VQ_BYTES * SVE_VQ_BYTES)
84#define SVE_PT_FPSIMD_OFFSET SVE_PT_REGS_OFFSET
85#define SVE_PT_FPSIMD_SIZE(vq,flags) (sizeof(struct user_fpsimd_state))
86#define SVE_PT_SVE_ZREG_SIZE(vq) SVE_SIG_ZREG_SIZE(vq)
87#define SVE_PT_SVE_PREG_SIZE(vq) SVE_SIG_PREG_SIZE(vq)
88#define SVE_PT_SVE_FFR_SIZE(vq) SVE_SIG_FFR_SIZE(vq)
89#define SVE_PT_SVE_FPSR_SIZE sizeof(__u32)
90#define SVE_PT_SVE_FPCR_SIZE sizeof(__u32)
91#define __SVE_SIG_TO_PT(offset) ((offset) - SVE_SIG_REGS_OFFSET + SVE_PT_REGS_OFFSET)
92#define SVE_PT_SVE_OFFSET SVE_PT_REGS_OFFSET
93#define SVE_PT_SVE_ZREGS_OFFSET __SVE_SIG_TO_PT(SVE_SIG_ZREGS_OFFSET)
94#define SVE_PT_SVE_ZREG_OFFSET(vq,n) __SVE_SIG_TO_PT(SVE_SIG_ZREG_OFFSET(vq, n))
95#define SVE_PT_SVE_ZREGS_SIZE(vq) (SVE_PT_SVE_ZREG_OFFSET(vq, SVE_NUM_ZREGS) - SVE_PT_SVE_ZREGS_OFFSET)
96#define SVE_PT_SVE_PREGS_OFFSET(vq) __SVE_SIG_TO_PT(SVE_SIG_PREGS_OFFSET(vq))
97#define SVE_PT_SVE_PREG_OFFSET(vq,n) __SVE_SIG_TO_PT(SVE_SIG_PREG_OFFSET(vq, n))
98#define SVE_PT_SVE_PREGS_SIZE(vq) (SVE_PT_SVE_PREG_OFFSET(vq, SVE_NUM_PREGS) - SVE_PT_SVE_PREGS_OFFSET(vq))
99#define SVE_PT_SVE_FFR_OFFSET(vq) __SVE_SIG_TO_PT(SVE_SIG_FFR_OFFSET(vq))
100#define SVE_PT_SVE_FPSR_OFFSET(vq) ((SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq) + (SVE_VQ_BYTES - 1)) / SVE_VQ_BYTES * SVE_VQ_BYTES)
101#define SVE_PT_SVE_FPCR_OFFSET(vq) (SVE_PT_SVE_FPSR_OFFSET(vq) + SVE_PT_SVE_FPSR_SIZE)
102#define SVE_PT_SVE_SIZE(vq,flags) ((SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE - SVE_PT_SVE_OFFSET + (SVE_VQ_BYTES - 1)) / SVE_VQ_BYTES * SVE_VQ_BYTES)
103#define SVE_PT_SIZE(vq,flags) (((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE ? SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags) : SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags))
Ben Cheng655a7c02013-10-16 16:09:24 -0700104#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -0800105#endif