The Android Open Source Project | a27d2ba | 2008-10-21 07:00:00 -0700 | [diff] [blame^] | 1 | /**************************************************************************** |
| 2 | **************************************************************************** |
| 3 | *** |
| 4 | *** This header was automatically generated from a Linux kernel header |
| 5 | *** of the same name, to make information necessary for userspace to |
| 6 | *** call into the kernel available to libc. It contains only constants, |
| 7 | *** structures, and macros generated from the original header, and thus, |
| 8 | *** contains no copyrightable information. |
| 9 | *** |
| 10 | **************************************************************************** |
| 11 | ****************************************************************************/ |
| 12 | #ifndef __ASM_ARCH_MUX_H |
| 13 | #define __ASM_ARCH_MUX_H |
| 14 | |
| 15 | #define PU_PD_SEL_NA 0 |
| 16 | #define PULL_DWN_CTRL_NA 0 |
| 17 | |
| 18 | #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, .mask_offset = mode_offset, .mask = mode, |
| 19 | |
| 20 | #define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, .pull_bit = bit, .pull_val = status, |
| 21 | |
| 22 | #define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, .pu_pd_val = status, |
| 23 | |
| 24 | #define MUX_REG_730(reg, mode_offset, mode) .mux_reg = OMAP730_IO_CONF_##reg, .mask_offset = mode_offset, .mask = mode, |
| 25 | |
| 26 | #define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, .pull_bit = bit, .pull_val = status, |
| 27 | |
| 28 | #define MUX_CFG(desc, mux_reg, mode_offset, mode, pull_reg, pull_bit, pull_status, pu_pd_reg, pu_pd_status, debug_status) { .name = desc, .debug = debug_status, MUX_REG(mux_reg, mode_offset, mode) PULL_REG(pull_reg, pull_bit, !pull_status) PU_PD_REG(pu_pd_reg, pu_pd_status) }, |
| 29 | |
| 30 | #define MUX_CFG_730(desc, mux_reg, mode_offset, mode, pull_bit, pull_status, debug_status) { .name = desc, .debug = debug_status, MUX_REG_730(mux_reg, mode_offset, mode) PULL_REG_730(mux_reg, pull_bit, pull_status) PU_PD_REG(NA, 0) }, |
| 31 | |
| 32 | #define MUX_CFG_24XX(desc, reg_offset, mode, pull_en, pull_mode, dbg) { .name = desc, .debug = dbg, .mux_reg = reg_offset, .mask = mode, .pull_val = pull_en, .pu_pd_val = pull_mode, }, |
| 33 | |
| 34 | #define PULL_DISABLED 0 |
| 35 | #define PULL_ENABLED 1 |
| 36 | |
| 37 | #define PULL_DOWN 0 |
| 38 | #define PULL_UP 1 |
| 39 | |
| 40 | struct pin_config { |
| 41 | char *name; |
| 42 | unsigned char busy; |
| 43 | unsigned char debug; |
| 44 | |
| 45 | const char *mux_reg_name; |
| 46 | const unsigned int mux_reg; |
| 47 | const unsigned char mask_offset; |
| 48 | const unsigned char mask; |
| 49 | |
| 50 | const char *pull_name; |
| 51 | const unsigned int pull_reg; |
| 52 | const unsigned char pull_val; |
| 53 | const unsigned char pull_bit; |
| 54 | |
| 55 | const char *pu_pd_name; |
| 56 | const unsigned int pu_pd_reg; |
| 57 | const unsigned char pu_pd_val; |
| 58 | }; |
| 59 | |
| 60 | enum omap730_index { |
| 61 | |
| 62 | E2_730_KBR0, |
| 63 | J7_730_KBR1, |
| 64 | E1_730_KBR2, |
| 65 | F3_730_KBR3, |
| 66 | D2_730_KBR4, |
| 67 | AA20_730_KBR5, |
| 68 | V17_730_KBR6, |
| 69 | C2_730_KBC0, |
| 70 | D3_730_KBC1, |
| 71 | E4_730_KBC2, |
| 72 | F4_730_KBC3, |
| 73 | E3_730_KBC4, |
| 74 | |
| 75 | AA17_730_USB_DM, |
| 76 | W16_730_USB_PU_EN, |
| 77 | W17_730_USB_VBUSI, |
| 78 | |
| 79 | V19_730_GPIO_15, |
| 80 | M19_730_GPIO_77, |
| 81 | C21_730_GPIO_121_122, |
| 82 | K19_730_GPIO_126, |
| 83 | K15_730_GPIO_127, |
| 84 | |
| 85 | P15_730_GPIO_16_17, |
| 86 | |
| 87 | M15_730_GPIO_83, |
| 88 | N20_730_GPIO_82, |
| 89 | N18_730_GPIO_81, |
| 90 | N19_730_GPIO_80, |
| 91 | L15_730_GPIO_76, |
| 92 | |
| 93 | UART1_CTS_RTS, |
| 94 | OMAP_730_GPIOS_42_43, |
| 95 | UART1_TX_RX, |
| 96 | OMAP_730_GPIOS_40_41, |
| 97 | UART1_USB_RX_TX, |
| 98 | UART1_USB_RTS, |
| 99 | UART1_USB_CTS |
| 100 | }; |
| 101 | |
| 102 | enum omap1xxx_index { |
| 103 | |
| 104 | UART1_TX = 0, |
| 105 | UART1_RTS, |
| 106 | |
| 107 | UART2_TX, |
| 108 | UART2_RX, |
| 109 | UART2_CTS, |
| 110 | UART2_RTS, |
| 111 | |
| 112 | UART3_TX, |
| 113 | UART3_RX, |
| 114 | UART3_CTS, |
| 115 | UART3_RTS, |
| 116 | UART3_CLKREQ, |
| 117 | UART3_BCLK, |
| 118 | Y15_1610_UART3_RTS, |
| 119 | |
| 120 | PWT, |
| 121 | PWL, |
| 122 | |
| 123 | R18_USB_VBUS, |
| 124 | R18_1510_USB_GPIO0, |
| 125 | W4_USB_PUEN, |
| 126 | W4_USB_CLKO, |
| 127 | W4_USB_HIGHZ, |
| 128 | W4_GPIO58, |
| 129 | |
| 130 | USB1_SUSP, |
| 131 | USB1_SEO, |
| 132 | W13_1610_USB1_SE0, |
| 133 | USB1_TXEN, |
| 134 | USB1_TXD, |
| 135 | USB1_VP, |
| 136 | USB1_VM, |
| 137 | USB1_RCV, |
| 138 | USB1_SPEED, |
| 139 | R13_1610_USB1_SPEED, |
| 140 | R13_1710_USB1_SE0, |
| 141 | |
| 142 | USB2_SUSP, |
| 143 | USB2_VP, |
| 144 | USB2_TXEN, |
| 145 | USB2_VM, |
| 146 | USB2_RCV, |
| 147 | USB2_SEO, |
| 148 | USB2_TXD, |
| 149 | |
| 150 | R18_1510_GPIO0, |
| 151 | R19_1510_GPIO1, |
| 152 | M14_1510_GPIO2, |
| 153 | |
| 154 | P18_1610_GPIO3, |
| 155 | Y15_1610_GPIO17, |
| 156 | |
| 157 | R18_1710_GPIO0, |
| 158 | V2_1710_GPIO10, |
| 159 | N21_1710_GPIO14, |
| 160 | W15_1710_GPIO40, |
| 161 | |
| 162 | MPUIO2, |
| 163 | N15_1610_MPUIO2, |
| 164 | MPUIO4, |
| 165 | MPUIO5, |
| 166 | T20_1610_MPUIO5, |
| 167 | W11_1610_MPUIO6, |
| 168 | V10_1610_MPUIO7, |
| 169 | W11_1610_MPUIO9, |
| 170 | V10_1610_MPUIO10, |
| 171 | W10_1610_MPUIO11, |
| 172 | E20_1610_MPUIO13, |
| 173 | U20_1610_MPUIO14, |
| 174 | E19_1610_MPUIO15, |
| 175 | |
| 176 | MCBSP2_CLKR, |
| 177 | MCBSP2_CLKX, |
| 178 | MCBSP2_DR, |
| 179 | MCBSP2_DX, |
| 180 | MCBSP2_FSR, |
| 181 | MCBSP2_FSX, |
| 182 | |
| 183 | MCBSP3_CLKX, |
| 184 | |
| 185 | BALLOUT_V8_ARMIO3, |
| 186 | N20_HDQ, |
| 187 | |
| 188 | W8_1610_MMC2_DAT0, |
| 189 | V8_1610_MMC2_DAT1, |
| 190 | W15_1610_MMC2_DAT2, |
| 191 | R10_1610_MMC2_DAT3, |
| 192 | Y10_1610_MMC2_CLK, |
| 193 | Y8_1610_MMC2_CMD, |
| 194 | V9_1610_MMC2_CMDDIR, |
| 195 | V5_1610_MMC2_DATDIR0, |
| 196 | W19_1610_MMC2_DATDIR1, |
| 197 | R18_1610_MMC2_CLKIN, |
| 198 | |
| 199 | M19_1610_ETM_PSTAT0, |
| 200 | L15_1610_ETM_PSTAT1, |
| 201 | L18_1610_ETM_PSTAT2, |
| 202 | L19_1610_ETM_D0, |
| 203 | J19_1610_ETM_D6, |
| 204 | J18_1610_ETM_D7, |
| 205 | |
| 206 | P20_1610_GPIO4, |
| 207 | V9_1610_GPIO7, |
| 208 | W8_1610_GPIO9, |
| 209 | N20_1610_GPIO11, |
| 210 | N19_1610_GPIO13, |
| 211 | P10_1610_GPIO22, |
| 212 | V5_1610_GPIO24, |
| 213 | AA20_1610_GPIO_41, |
| 214 | W19_1610_GPIO48, |
| 215 | M7_1610_GPIO62, |
| 216 | V14_16XX_GPIO37, |
| 217 | R9_16XX_GPIO18, |
| 218 | L14_16XX_GPIO49, |
| 219 | |
| 220 | V19_1610_UWIRE_SCLK, |
| 221 | U18_1610_UWIRE_SDI, |
| 222 | W21_1610_UWIRE_SDO, |
| 223 | N14_1610_UWIRE_CS0, |
| 224 | P15_1610_UWIRE_CS3, |
| 225 | N15_1610_UWIRE_CS1, |
| 226 | |
| 227 | U19_1610_SPIF_SCK, |
| 228 | U18_1610_SPIF_DIN, |
| 229 | P20_1610_SPIF_DIN, |
| 230 | W21_1610_SPIF_DOUT, |
| 231 | R18_1610_SPIF_DOUT, |
| 232 | N14_1610_SPIF_CS0, |
| 233 | N15_1610_SPIF_CS1, |
| 234 | T19_1610_SPIF_CS2, |
| 235 | P15_1610_SPIF_CS3, |
| 236 | |
| 237 | L3_1610_FLASH_CS2B_OE, |
| 238 | M8_1610_FLASH_CS2B_WE, |
| 239 | |
| 240 | MMC_CMD, |
| 241 | MMC_DAT1, |
| 242 | MMC_DAT2, |
| 243 | MMC_DAT0, |
| 244 | MMC_CLK, |
| 245 | MMC_DAT3, |
| 246 | |
| 247 | M15_1710_MMC_CLKI, |
| 248 | P19_1710_MMC_CMDDIR, |
| 249 | P20_1710_MMC_DATDIR0, |
| 250 | |
| 251 | W9_USB0_TXEN, |
| 252 | AA9_USB0_VP, |
| 253 | Y5_USB0_RCV, |
| 254 | R9_USB0_VM, |
| 255 | V6_USB0_TXD, |
| 256 | W5_USB0_SE0, |
| 257 | V9_USB0_SPEED, |
| 258 | V9_USB0_SUSP, |
| 259 | |
| 260 | W9_USB2_TXEN, |
| 261 | AA9_USB2_VP, |
| 262 | Y5_USB2_RCV, |
| 263 | R9_USB2_VM, |
| 264 | V6_USB2_TXD, |
| 265 | W5_USB2_SE0, |
| 266 | |
| 267 | R13_1610_UART1_TX, |
| 268 | V14_16XX_UART1_RX, |
| 269 | R14_1610_UART1_CTS, |
| 270 | AA15_1610_UART1_RTS, |
| 271 | R9_16XX_UART2_RX, |
| 272 | L14_16XX_UART3_RX, |
| 273 | |
| 274 | I2C_SCL, |
| 275 | I2C_SDA, |
| 276 | |
| 277 | F18_1610_KBC0, |
| 278 | D20_1610_KBC1, |
| 279 | D19_1610_KBC2, |
| 280 | E18_1610_KBC3, |
| 281 | C21_1610_KBC4, |
| 282 | G18_1610_KBR0, |
| 283 | F19_1610_KBR1, |
| 284 | H14_1610_KBR2, |
| 285 | E20_1610_KBR3, |
| 286 | E19_1610_KBR4, |
| 287 | N19_1610_KBR5, |
| 288 | |
| 289 | T20_1610_LOW_PWR, |
| 290 | |
| 291 | V5_1710_MCLK_ON, |
| 292 | V5_1710_MCLK_OFF, |
| 293 | R10_1610_MCLK_ON, |
| 294 | R10_1610_MCLK_OFF, |
| 295 | |
| 296 | P11_1610_CF_CD2, |
| 297 | R11_1610_CF_IOIS16, |
| 298 | V10_1610_CF_IREQ, |
| 299 | W10_1610_CF_RESET, |
| 300 | W11_1610_CF_CD1, |
| 301 | }; |
| 302 | |
| 303 | enum omap24xx_index { |
| 304 | |
| 305 | M19_24XX_I2C1_SCL, |
| 306 | L15_24XX_I2C1_SDA, |
| 307 | J15_24XX_I2C2_SCL, |
| 308 | H19_24XX_I2C2_SDA, |
| 309 | |
| 310 | W19_24XX_SYS_NIRQ, |
| 311 | |
| 312 | W14_24XX_SYS_CLKOUT, |
| 313 | |
| 314 | L3_GPMC_WAIT0, |
| 315 | N7_GPMC_WAIT1, |
| 316 | M1_GPMC_WAIT2, |
| 317 | P1_GPMC_WAIT3, |
| 318 | |
| 319 | Y15_24XX_MCBSP2_CLKX, |
| 320 | R14_24XX_MCBSP2_FSX, |
| 321 | W15_24XX_MCBSP2_DR, |
| 322 | V15_24XX_MCBSP2_DX, |
| 323 | |
| 324 | M21_242X_GPIO11, |
| 325 | AA10_242X_GPIO13, |
| 326 | AA6_242X_GPIO14, |
| 327 | AA4_242X_GPIO15, |
| 328 | Y11_242X_GPIO16, |
| 329 | AA12_242X_GPIO17, |
| 330 | AA8_242X_GPIO58, |
| 331 | Y20_24XX_GPIO60, |
| 332 | W4__24XX_GPIO74, |
| 333 | M15_24XX_GPIO92, |
| 334 | V14_24XX_GPIO117, |
| 335 | |
| 336 | V4_242X_GPIO49, |
| 337 | W2_242X_GPIO50, |
| 338 | U4_242X_GPIO51, |
| 339 | V3_242X_GPIO52, |
| 340 | V2_242X_GPIO53, |
| 341 | V6_242X_GPIO53, |
| 342 | T4_242X_GPIO54, |
| 343 | Y4_242X_GPIO54, |
| 344 | T3_242X_GPIO55, |
| 345 | U2_242X_GPIO56, |
| 346 | |
| 347 | AA10_242X_DMAREQ0, |
| 348 | AA6_242X_DMAREQ1, |
| 349 | E4_242X_DMAREQ2, |
| 350 | G4_242X_DMAREQ3, |
| 351 | D3_242X_DMAREQ4, |
| 352 | E3_242X_DMAREQ5, |
| 353 | |
| 354 | P20_24XX_TSC_IRQ, |
| 355 | |
| 356 | K15_24XX_UART3_TX, |
| 357 | K14_24XX_UART3_RX, |
| 358 | |
| 359 | G19_24XX_MMC_CLKO, |
| 360 | H18_24XX_MMC_CMD, |
| 361 | F20_24XX_MMC_DAT0, |
| 362 | H14_24XX_MMC_DAT1, |
| 363 | E19_24XX_MMC_DAT2, |
| 364 | D19_24XX_MMC_DAT3, |
| 365 | F19_24XX_MMC_DAT_DIR0, |
| 366 | E20_24XX_MMC_DAT_DIR1, |
| 367 | F18_24XX_MMC_DAT_DIR2, |
| 368 | E18_24XX_MMC_DAT_DIR3, |
| 369 | G18_24XX_MMC_CMD_DIR, |
| 370 | H15_24XX_MMC_CLKI, |
| 371 | |
| 372 | T19_24XX_KBR0, |
| 373 | R19_24XX_KBR1, |
| 374 | V18_24XX_KBR2, |
| 375 | M21_24XX_KBR3, |
| 376 | E5__24XX_KBR4, |
| 377 | M18_24XX_KBR5, |
| 378 | R20_24XX_KBC0, |
| 379 | M14_24XX_KBC1, |
| 380 | H19_24XX_KBC2, |
| 381 | V17_24XX_KBC3, |
| 382 | P21_24XX_KBC4, |
| 383 | L14_24XX_KBC5, |
| 384 | N19_24XX_KBC6, |
| 385 | |
| 386 | B3__24XX_KBR5, |
| 387 | AA4_24XX_KBC2, |
| 388 | B13_24XX_KBC6, |
| 389 | }; |
| 390 | |
| 391 | #endif |