The Android Open Source Project | a27d2ba | 2008-10-21 07:00:00 -0700 | [diff] [blame^] | 1 | /**************************************************************************** |
| 2 | **************************************************************************** |
| 3 | *** |
| 4 | *** This header was automatically generated from a Linux kernel header |
| 5 | *** of the same name, to make information necessary for userspace to |
| 6 | *** call into the kernel available to libc. It contains only constants, |
| 7 | *** structures, and macros generated from the original header, and thus, |
| 8 | *** contains no copyrightable information. |
| 9 | *** |
| 10 | **************************************************************************** |
| 11 | ****************************************************************************/ |
| 12 | #ifndef _ASMARM_CACHEFLUSH_H |
| 13 | #define _ASMARM_CACHEFLUSH_H |
| 14 | |
| 15 | #include <linux/sched.h> |
| 16 | #include <linux/mm.h> |
| 17 | |
| 18 | #include <asm/glue.h> |
| 19 | #include <asm/shmparam.h> |
| 20 | |
| 21 | #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT) |
| 22 | |
| 23 | #undef _CACHE |
| 24 | #undef MULTI_CACHE |
| 25 | |
| 26 | #if !defined(_CACHE) && !defined(MULTI_CACHE) |
| 27 | #error Unknown cache maintainence model |
| 28 | #endif |
| 29 | |
| 30 | #define PG_dcache_dirty PG_arch_1 |
| 31 | |
| 32 | struct cpu_cache_fns { |
| 33 | void (*flush_kern_all)(void); |
| 34 | void (*flush_user_all)(void); |
| 35 | void (*flush_user_range)(unsigned long, unsigned long, unsigned int); |
| 36 | |
| 37 | void (*coherent_kern_range)(unsigned long, unsigned long); |
| 38 | void (*coherent_user_range)(unsigned long, unsigned long); |
| 39 | void (*flush_kern_dcache_page)(void *); |
| 40 | |
| 41 | void (*dma_inv_range)(unsigned long, unsigned long); |
| 42 | void (*dma_clean_range)(unsigned long, unsigned long); |
| 43 | void (*dma_flush_range)(unsigned long, unsigned long); |
| 44 | }; |
| 45 | |
| 46 | #ifdef MULTI_CACHE |
| 47 | |
| 48 | #define __cpuc_flush_kern_all cpu_cache.flush_kern_all |
| 49 | #define __cpuc_flush_user_all cpu_cache.flush_user_all |
| 50 | #define __cpuc_flush_user_range cpu_cache.flush_user_range |
| 51 | #define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range |
| 52 | #define __cpuc_coherent_user_range cpu_cache.coherent_user_range |
| 53 | #define __cpuc_flush_dcache_page cpu_cache.flush_kern_dcache_page |
| 54 | |
| 55 | #define dmac_inv_range cpu_cache.dma_inv_range |
| 56 | #define dmac_clean_range cpu_cache.dma_clean_range |
| 57 | #define dmac_flush_range cpu_cache.dma_flush_range |
| 58 | |
| 59 | #else |
| 60 | |
| 61 | #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) |
| 62 | #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all) |
| 63 | #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) |
| 64 | #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range) |
| 65 | #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) |
| 66 | #define __cpuc_flush_dcache_page __glue(_CACHE,_flush_kern_dcache_page) |
| 67 | |
| 68 | #define dmac_inv_range __glue(_CACHE,_dma_inv_range) |
| 69 | #define dmac_clean_range __glue(_CACHE,_dma_clean_range) |
| 70 | #define dmac_flush_range __glue(_CACHE,_dma_flush_range) |
| 71 | |
| 72 | #endif |
| 73 | |
| 74 | #define flush_cache_vmap(start, end) flush_cache_all() |
| 75 | #define flush_cache_vunmap(start, end) flush_cache_all() |
| 76 | |
| 77 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) do { memcpy(dst, src, len); flush_ptrace_access(vma, page, vaddr, dst, len, 1); } while (0) |
| 78 | |
| 79 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) do { memcpy(dst, src, len); } while (0) |
| 80 | |
| 81 | #define flush_cache_all() __cpuc_flush_kern_all() |
| 82 | #define flush_cache_user_range(vma,start,end) __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end)) |
| 83 | #define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e) |
| 84 | #define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size) |
| 85 | |
| 86 | #define flush_dcache_mmap_lock(mapping) write_lock_irq(&(mapping)->tree_lock) |
| 87 | #define flush_dcache_mmap_unlock(mapping) write_unlock_irq(&(mapping)->tree_lock) |
| 88 | |
| 89 | #define flush_icache_user_range(vma,page,addr,len) flush_dcache_page(page) |
| 90 | |
| 91 | #define flush_icache_page(vma,page) do { } while (0) |
| 92 | |
| 93 | #define __cacheid_present(val) (val != read_cpuid(CPUID_ID)) |
| 94 | #define __cacheid_vivt(val) ((val & (15 << 25)) != (14 << 25)) |
| 95 | #define __cacheid_vipt(val) ((val & (15 << 25)) == (14 << 25)) |
| 96 | #define __cacheid_vipt_nonaliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25)) |
| 97 | #define __cacheid_vipt_aliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23)) |
| 98 | |
| 99 | #define cache_is_vivt() ({ unsigned int __val = read_cpuid(CPUID_CACHETYPE); (!__cacheid_present(__val)) || __cacheid_vivt(__val); }) |
| 100 | |
| 101 | #define cache_is_vipt() ({ unsigned int __val = read_cpuid(CPUID_CACHETYPE); __cacheid_present(__val) && __cacheid_vipt(__val); }) |
| 102 | |
| 103 | #define cache_is_vipt_nonaliasing() ({ unsigned int __val = read_cpuid(CPUID_CACHETYPE); __cacheid_present(__val) && __cacheid_vipt_nonaliasing(__val); }) |
| 104 | |
| 105 | #define cache_is_vipt_aliasing() ({ unsigned int __val = read_cpuid(CPUID_CACHETYPE); __cacheid_present(__val) && __cacheid_vipt_aliasing(__val); }) |
| 106 | |
| 107 | #endif |