The Android Open Source Project | a27d2ba | 2008-10-21 07:00:00 -0700 | [diff] [blame^] | 1 | /**************************************************************************** |
| 2 | **************************************************************************** |
| 3 | *** |
| 4 | *** This header was automatically generated from a Linux kernel header |
| 5 | *** of the same name, to make information necessary for userspace to |
| 6 | *** call into the kernel available to libc. It contains only constants, |
| 7 | *** structures, and macros generated from the original header, and thus, |
| 8 | *** contains no copyrightable information. |
| 9 | *** |
| 10 | **************************************************************************** |
| 11 | ****************************************************************************/ |
| 12 | #ifndef _LINUX_SERIAL_REG_H |
| 13 | #define _LINUX_SERIAL_REG_H |
| 14 | |
| 15 | #define UART_RX 0 |
| 16 | #define UART_TX 0 |
| 17 | |
| 18 | #define UART_IER 1 |
| 19 | #define UART_IER_MSI 0x08 |
| 20 | #define UART_IER_RLSI 0x04 |
| 21 | #define UART_IER_THRI 0x02 |
| 22 | #define UART_IER_RDI 0x01 |
| 23 | |
| 24 | #define UART_IERX_SLEEP 0x10 |
| 25 | |
| 26 | #define UART_IIR 2 |
| 27 | #define UART_IIR_NO_INT 0x01 |
| 28 | #define UART_IIR_ID 0x06 |
| 29 | #define UART_IIR_MSI 0x00 |
| 30 | #define UART_IIR_THRI 0x02 |
| 31 | #define UART_IIR_RDI 0x04 |
| 32 | #define UART_IIR_RLSI 0x06 |
| 33 | |
| 34 | #define UART_FCR 2 |
| 35 | #define UART_FCR_ENABLE_FIFO 0x01 |
| 36 | #define UART_FCR_CLEAR_RCVR 0x02 |
| 37 | #define UART_FCR_CLEAR_XMIT 0x04 |
| 38 | #define UART_FCR_DMA_SELECT 0x08 |
| 39 | |
| 40 | #define UART_FCR_R_TRIG_00 0x00 |
| 41 | #define UART_FCR_R_TRIG_01 0x40 |
| 42 | #define UART_FCR_R_TRIG_10 0x80 |
| 43 | #define UART_FCR_R_TRIG_11 0xc0 |
| 44 | #define UART_FCR_T_TRIG_00 0x00 |
| 45 | #define UART_FCR_T_TRIG_01 0x10 |
| 46 | #define UART_FCR_T_TRIG_10 0x20 |
| 47 | #define UART_FCR_T_TRIG_11 0x30 |
| 48 | |
| 49 | #define UART_FCR_TRIGGER_MASK 0xC0 |
| 50 | #define UART_FCR_TRIGGER_1 0x00 |
| 51 | #define UART_FCR_TRIGGER_4 0x40 |
| 52 | #define UART_FCR_TRIGGER_8 0x80 |
| 53 | #define UART_FCR_TRIGGER_14 0xC0 |
| 54 | |
| 55 | #define UART_FCR6_R_TRIGGER_8 0x00 |
| 56 | #define UART_FCR6_R_TRIGGER_16 0x40 |
| 57 | #define UART_FCR6_R_TRIGGER_24 0x80 |
| 58 | #define UART_FCR6_R_TRIGGER_28 0xC0 |
| 59 | #define UART_FCR6_T_TRIGGER_16 0x00 |
| 60 | #define UART_FCR6_T_TRIGGER_8 0x10 |
| 61 | #define UART_FCR6_T_TRIGGER_24 0x20 |
| 62 | #define UART_FCR6_T_TRIGGER_30 0x30 |
| 63 | #define UART_FCR7_64BYTE 0x20 |
| 64 | |
| 65 | #define UART_LCR 3 |
| 66 | |
| 67 | #define UART_LCR_DLAB 0x80 |
| 68 | #define UART_LCR_SBC 0x40 |
| 69 | #define UART_LCR_SPAR 0x20 |
| 70 | #define UART_LCR_EPAR 0x10 |
| 71 | #define UART_LCR_PARITY 0x08 |
| 72 | #define UART_LCR_STOP 0x04 |
| 73 | #define UART_LCR_WLEN5 0x00 |
| 74 | #define UART_LCR_WLEN6 0x01 |
| 75 | #define UART_LCR_WLEN7 0x02 |
| 76 | #define UART_LCR_WLEN8 0x03 |
| 77 | |
| 78 | #define UART_MCR 4 |
| 79 | #define UART_MCR_CLKSEL 0x80 |
| 80 | #define UART_MCR_TCRTLR 0x40 |
| 81 | #define UART_MCR_XONANY 0x20 |
| 82 | #define UART_MCR_AFE 0x20 |
| 83 | #define UART_MCR_LOOP 0x10 |
| 84 | #define UART_MCR_OUT2 0x08 |
| 85 | #define UART_MCR_OUT1 0x04 |
| 86 | #define UART_MCR_RTS 0x02 |
| 87 | #define UART_MCR_DTR 0x01 |
| 88 | |
| 89 | #define UART_LSR 5 |
| 90 | #define UART_LSR_TEMT 0x40 |
| 91 | #define UART_LSR_THRE 0x20 |
| 92 | #define UART_LSR_BI 0x10 |
| 93 | #define UART_LSR_FE 0x08 |
| 94 | #define UART_LSR_PE 0x04 |
| 95 | #define UART_LSR_OE 0x02 |
| 96 | #define UART_LSR_DR 0x01 |
| 97 | |
| 98 | #define UART_MSR 6 |
| 99 | #define UART_MSR_DCD 0x80 |
| 100 | #define UART_MSR_RI 0x40 |
| 101 | #define UART_MSR_DSR 0x20 |
| 102 | #define UART_MSR_CTS 0x10 |
| 103 | #define UART_MSR_DDCD 0x08 |
| 104 | #define UART_MSR_TERI 0x04 |
| 105 | #define UART_MSR_DDSR 0x02 |
| 106 | #define UART_MSR_DCTS 0x01 |
| 107 | #define UART_MSR_ANY_DELTA 0x0F |
| 108 | |
| 109 | #define UART_SCR 7 |
| 110 | |
| 111 | #define UART_DLL 0 |
| 112 | #define UART_DLM 1 |
| 113 | |
| 114 | #define UART_EFR 2 |
| 115 | #define UART_EFR_CTS 0x80 |
| 116 | #define UART_EFR_RTS 0x40 |
| 117 | #define UART_EFR_SCD 0x20 |
| 118 | #define UART_EFR_ECB 0x10 |
| 119 | |
| 120 | #define UART_XON1 4 |
| 121 | #define UART_XON2 5 |
| 122 | #define UART_XOFF1 6 |
| 123 | #define UART_XOFF2 7 |
| 124 | |
| 125 | #define UART_TI752_TCR 6 |
| 126 | #define UART_TI752_TLR 7 |
| 127 | |
| 128 | #define UART_TRG 0 |
| 129 | |
| 130 | #define UART_TRG_1 0x01 |
| 131 | #define UART_TRG_4 0x04 |
| 132 | #define UART_TRG_8 0x08 |
| 133 | #define UART_TRG_16 0x10 |
| 134 | #define UART_TRG_32 0x20 |
| 135 | #define UART_TRG_64 0x40 |
| 136 | #define UART_TRG_96 0x60 |
| 137 | #define UART_TRG_120 0x78 |
| 138 | #define UART_TRG_128 0x80 |
| 139 | |
| 140 | #define UART_FCTR 1 |
| 141 | #define UART_FCTR_RTS_NODELAY 0x00 |
| 142 | #define UART_FCTR_RTS_4DELAY 0x01 |
| 143 | #define UART_FCTR_RTS_6DELAY 0x02 |
| 144 | #define UART_FCTR_RTS_8DELAY 0x03 |
| 145 | #define UART_FCTR_IRDA 0x04 |
| 146 | #define UART_FCTR_TX_INT 0x08 |
| 147 | #define UART_FCTR_TRGA 0x00 |
| 148 | #define UART_FCTR_TRGB 0x10 |
| 149 | #define UART_FCTR_TRGC 0x20 |
| 150 | #define UART_FCTR_TRGD 0x30 |
| 151 | #define UART_FCTR_SCR_SWAP 0x40 |
| 152 | #define UART_FCTR_RX 0x00 |
| 153 | #define UART_FCTR_TX 0x80 |
| 154 | |
| 155 | #define UART_EMSR 7 |
| 156 | #define UART_EMSR_FIFO_COUNT 0x01 |
| 157 | #define UART_EMSR_ALT_COUNT 0x02 |
| 158 | |
| 159 | #define UART_IER_DMAE 0x80 |
| 160 | #define UART_IER_UUE 0x40 |
| 161 | #define UART_IER_NRZE 0x20 |
| 162 | #define UART_IER_RTOIE 0x10 |
| 163 | |
| 164 | #define UART_IIR_TOD 0x08 |
| 165 | |
| 166 | #define UART_FCR_PXAR1 0x00 |
| 167 | #define UART_FCR_PXAR8 0x40 |
| 168 | #define UART_FCR_PXAR16 0x80 |
| 169 | #define UART_FCR_PXAR32 0xc0 |
| 170 | |
| 171 | #define UART_ASR 0x01 |
| 172 | #define UART_RFL 0x03 |
| 173 | #define UART_TFL 0x04 |
| 174 | #define UART_ICR 0x05 |
| 175 | |
| 176 | #define UART_ACR 0x00 |
| 177 | #define UART_CPR 0x01 |
| 178 | #define UART_TCR 0x02 |
| 179 | #define UART_CKS 0x03 |
| 180 | #define UART_TTL 0x04 |
| 181 | #define UART_RTL 0x05 |
| 182 | #define UART_FCL 0x06 |
| 183 | #define UART_FCH 0x07 |
| 184 | #define UART_ID1 0x08 |
| 185 | #define UART_ID2 0x09 |
| 186 | #define UART_ID3 0x0A |
| 187 | #define UART_REV 0x0B |
| 188 | #define UART_CSR 0x0C |
| 189 | #define UART_NMR 0x0D |
| 190 | #define UART_CTR 0xFF |
| 191 | |
| 192 | #define UART_ACR_RXDIS 0x01 |
| 193 | #define UART_ACR_TXDIS 0x02 |
| 194 | #define UART_ACR_DSRFC 0x04 |
| 195 | #define UART_ACR_TLENB 0x20 |
| 196 | #define UART_ACR_ICRRD 0x40 |
| 197 | #define UART_ACR_ASREN 0x80 |
| 198 | |
| 199 | #define UART_RSA_BASE (-8) |
| 200 | |
| 201 | #define UART_RSA_MSR ((UART_RSA_BASE) + 0) |
| 202 | |
| 203 | #define UART_RSA_MSR_SWAP (1 << 0) |
| 204 | #define UART_RSA_MSR_FIFO (1 << 2) |
| 205 | #define UART_RSA_MSR_FLOW (1 << 3) |
| 206 | #define UART_RSA_MSR_ITYP (1 << 4) |
| 207 | |
| 208 | #define UART_RSA_IER ((UART_RSA_BASE) + 1) |
| 209 | |
| 210 | #define UART_RSA_IER_Rx_FIFO_H (1 << 0) |
| 211 | #define UART_RSA_IER_Tx_FIFO_H (1 << 1) |
| 212 | #define UART_RSA_IER_Tx_FIFO_E (1 << 2) |
| 213 | #define UART_RSA_IER_Rx_TOUT (1 << 3) |
| 214 | #define UART_RSA_IER_TIMER (1 << 4) |
| 215 | |
| 216 | #define UART_RSA_SRR ((UART_RSA_BASE) + 2) |
| 217 | |
| 218 | #define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) |
| 219 | #define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) |
| 220 | #define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) |
| 221 | #define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) |
| 222 | #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) |
| 223 | #define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) |
| 224 | #define UART_RSA_SRR_Rx_TOUT (1 << 6) |
| 225 | #define UART_RSA_SRR_TIMER (1 << 7) |
| 226 | |
| 227 | #define UART_RSA_FRR ((UART_RSA_BASE) + 2) |
| 228 | |
| 229 | #define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) |
| 230 | |
| 231 | #define UART_RSA_TCR ((UART_RSA_BASE) + 4) |
| 232 | |
| 233 | #define UART_RSA_TCR_SWITCH (1 << 0) |
| 234 | |
| 235 | #define SERIAL_RSA_BAUD_BASE (921600) |
| 236 | #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8) |
| 237 | |
| 238 | #define UART_OMAP_MDR1 0x08 |
| 239 | #define UART_OMAP_MDR2 0x09 |
| 240 | #define UART_OMAP_SCR 0x10 |
| 241 | #define UART_OMAP_SSR 0x11 |
| 242 | #define UART_OMAP_EBLR 0x12 |
| 243 | #define UART_OMAP_OSC_12M_SEL 0x13 |
| 244 | #define UART_OMAP_MVER 0x14 |
| 245 | #define UART_OMAP_SYSC 0x15 |
| 246 | #define UART_OMAP_SYSS 0x16 |
| 247 | |
| 248 | #endif |
| 249 | |