blob: 4e6838108641e4cdc2aee16385fba0f41884183c [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __R128_DRM_H__
20#define __R128_DRM_H__
21#ifndef __R128_SAREA_DEFINES__
22#define __R128_SAREA_DEFINES__
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24#define R128_UPLOAD_CONTEXT 0x001
25#define R128_UPLOAD_SETUP 0x002
26#define R128_UPLOAD_TEX0 0x004
27#define R128_UPLOAD_TEX1 0x008
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
29#define R128_UPLOAD_TEX0IMAGES 0x010
30#define R128_UPLOAD_TEX1IMAGES 0x020
31#define R128_UPLOAD_CORE 0x040
32#define R128_UPLOAD_MASKS 0x080
33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
34#define R128_UPLOAD_WINDOW 0x100
35#define R128_UPLOAD_CLIPRECTS 0x200
36#define R128_REQUIRE_QUIESCENCE 0x400
37#define R128_UPLOAD_ALL 0x7ff
38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
39#define R128_FRONT 0x1
40#define R128_BACK 0x2
41#define R128_DEPTH 0x4
42#define R128_POINTS 0x1
43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
44#define R128_LINES 0x2
45#define R128_LINE_STRIP 0x3
46#define R128_TRIANGLES 0x4
47#define R128_TRIANGLE_FAN 0x5
48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
49#define R128_TRIANGLE_STRIP 0x6
50#define R128_BUFFER_SIZE 16384
51#define R128_INDEX_PRIM_OFFSET 20
52#define R128_HOSTDATA_BLIT_OFFSET 32
53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
54#define R128_NR_SAREA_CLIPRECTS 12
55#define R128_LOCAL_TEX_HEAP 0
56#define R128_AGP_TEX_HEAP 1
57#define R128_NR_TEX_HEAPS 2
58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
59#define R128_NR_TEX_REGIONS 64
60#define R128_LOG_TEX_GRANULARITY 16
61#define R128_NR_CONTEXT_REGS 12
62#define R128_MAX_TEXTURE_LEVELS 11
63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
64#define R128_MAX_TEXTURE_UNITS 2
65#endif
66typedef struct {
Tao Baod7db5942015-01-28 10:07:51 -080067 unsigned int dst_pitch_offset_c;
Ben Cheng655a7c02013-10-16 16:09:24 -070068/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -080069 unsigned int dp_gui_master_cntl_c;
70 unsigned int sc_top_left_c;
71 unsigned int sc_bottom_right_c;
72 unsigned int z_offset_c;
Ben Cheng655a7c02013-10-16 16:09:24 -070073/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -080074 unsigned int z_pitch_c;
75 unsigned int z_sten_cntl_c;
76 unsigned int tex_cntl_c;
77 unsigned int misc_3d_state_cntl_reg;
Ben Cheng655a7c02013-10-16 16:09:24 -070078/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -080079 unsigned int texture_clr_cmp_clr_c;
80 unsigned int texture_clr_cmp_msk_c;
81 unsigned int fog_color_c;
82 unsigned int tex_size_pitch_c;
Ben Cheng655a7c02013-10-16 16:09:24 -070083/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -080084 unsigned int constant_color_c;
85 unsigned int pm4_vc_fpu_setup;
86 unsigned int setup_cntl;
87 unsigned int dp_write_mask;
Ben Cheng655a7c02013-10-16 16:09:24 -070088/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -080089 unsigned int sten_ref_mask_c;
90 unsigned int plane_3d_mask_c;
91 unsigned int window_xy_offset;
92 unsigned int scale_3d_cntl;
Ben Cheng655a7c02013-10-16 16:09:24 -070093/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
94} drm_r128_context_regs_t;
95typedef struct {
Tao Baod7db5942015-01-28 10:07:51 -080096 unsigned int tex_cntl;
97 unsigned int tex_combine_cntl;
Ben Cheng655a7c02013-10-16 16:09:24 -070098/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -080099 unsigned int tex_size_pitch;
100 unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
101 unsigned int tex_border_color;
Ben Cheng655a7c02013-10-16 16:09:24 -0700102} drm_r128_texture_regs_t;
103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
104typedef struct drm_r128_sarea {
Tao Baod7db5942015-01-28 10:07:51 -0800105 drm_r128_context_regs_t context_state;
106 drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
107 unsigned int dirty;
Ben Cheng655a7c02013-10-16 16:09:24 -0700108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800109 unsigned int vertsize;
110 unsigned int vc_format;
111 struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS];
112 unsigned int nbox;
Ben Cheng655a7c02013-10-16 16:09:24 -0700113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800114 unsigned int last_frame;
115 unsigned int last_dispatch;
116 struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
117 unsigned int tex_age[R128_NR_TEX_HEAPS];
Ben Cheng655a7c02013-10-16 16:09:24 -0700118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800119 int ctx_owner;
120 int pfAllowPageFlip;
121 int pfCurrentPage;
Ben Cheng655a7c02013-10-16 16:09:24 -0700122} drm_r128_sarea_t;
123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
124#define DRM_R128_INIT 0x00
125#define DRM_R128_CCE_START 0x01
126#define DRM_R128_CCE_STOP 0x02
127#define DRM_R128_CCE_RESET 0x03
128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
129#define DRM_R128_CCE_IDLE 0x04
130#define DRM_R128_RESET 0x06
131#define DRM_R128_SWAP 0x07
132#define DRM_R128_CLEAR 0x08
133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
134#define DRM_R128_VERTEX 0x09
135#define DRM_R128_INDICES 0x0a
136#define DRM_R128_BLIT 0x0b
137#define DRM_R128_DEPTH 0x0c
138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
139#define DRM_R128_STIPPLE 0x0d
140#define DRM_R128_INDIRECT 0x0f
141#define DRM_R128_FULLSCREEN 0x10
142#define DRM_R128_CLEAR2 0x11
143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
144#define DRM_R128_GETPARAM 0x12
145#define DRM_R128_FLIP 0x13
Tao Baod7db5942015-01-28 10:07:51 -0800146#define DRM_IOCTL_R128_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t)
147#define DRM_IOCTL_R128_CCE_START DRM_IO(DRM_COMMAND_BASE + DRM_R128_CCE_START)
Ben Cheng655a7c02013-10-16 16:09:24 -0700148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800149#define DRM_IOCTL_R128_CCE_STOP DRM_IOW(DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t)
150#define DRM_IOCTL_R128_CCE_RESET DRM_IO(DRM_COMMAND_BASE + DRM_R128_CCE_RESET)
151#define DRM_IOCTL_R128_CCE_IDLE DRM_IO(DRM_COMMAND_BASE + DRM_R128_CCE_IDLE)
152#define DRM_IOCTL_R128_RESET DRM_IO(DRM_COMMAND_BASE + DRM_R128_RESET)
Ben Cheng655a7c02013-10-16 16:09:24 -0700153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800154#define DRM_IOCTL_R128_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_R128_SWAP)
155#define DRM_IOCTL_R128_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t)
156#define DRM_IOCTL_R128_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t)
157#define DRM_IOCTL_R128_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800159#define DRM_IOCTL_R128_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t)
160#define DRM_IOCTL_R128_DEPTH DRM_IOW(DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t)
161#define DRM_IOCTL_R128_STIPPLE DRM_IOW(DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700162#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t)
163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800164#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW(DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t)
165#define DRM_IOCTL_R128_CLEAR2 DRM_IOW(DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
166#define DRM_IOCTL_R128_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
167#define DRM_IOCTL_R128_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_R128_FLIP)
Ben Cheng655a7c02013-10-16 16:09:24 -0700168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
169typedef struct drm_r128_init {
Tao Baod7db5942015-01-28 10:07:51 -0800170 enum {
171 R128_INIT_CCE = 0x01,
172 R128_CLEANUP_CCE = 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -0700173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800174 } func;
175 unsigned long sarea_priv_offset;
176 int is_pci;
177 int cce_mode;
Ben Cheng655a7c02013-10-16 16:09:24 -0700178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800179 int cce_secure;
180 int ring_size;
181 int usec_timeout;
182 unsigned int fb_bpp;
Ben Cheng655a7c02013-10-16 16:09:24 -0700183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800184 unsigned int front_offset, front_pitch;
185 unsigned int back_offset, back_pitch;
186 unsigned int depth_bpp;
187 unsigned int depth_offset, depth_pitch;
Ben Cheng655a7c02013-10-16 16:09:24 -0700188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800189 unsigned int span_offset;
190 unsigned long fb_offset;
191 unsigned long mmio_offset;
192 unsigned long ring_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800194 unsigned long ring_rptr_offset;
195 unsigned long buffers_offset;
196 unsigned long agp_textures_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700197} drm_r128_init_t;
198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
199typedef struct drm_r128_cce_stop {
Tao Baod7db5942015-01-28 10:07:51 -0800200 int flush;
201 int idle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700202} drm_r128_cce_stop_t;
203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
204typedef struct drm_r128_clear {
Tao Baod7db5942015-01-28 10:07:51 -0800205 unsigned int flags;
206 unsigned int clear_color;
207 unsigned int clear_depth;
Ben Cheng655a7c02013-10-16 16:09:24 -0700208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800209 unsigned int color_mask;
210 unsigned int depth_mask;
Ben Cheng655a7c02013-10-16 16:09:24 -0700211} drm_r128_clear_t;
212typedef struct drm_r128_vertex {
213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800214 int prim;
215 int idx;
216 int count;
217 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
219} drm_r128_vertex_t;
220typedef struct drm_r128_indices {
Tao Baod7db5942015-01-28 10:07:51 -0800221 int prim;
222 int idx;
Ben Cheng655a7c02013-10-16 16:09:24 -0700223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800224 int start;
225 int end;
226 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700227} drm_r128_indices_t;
228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
229typedef struct drm_r128_blit {
Tao Baod7db5942015-01-28 10:07:51 -0800230 int idx;
231 int pitch;
232 int offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800234 int format;
235 unsigned short x, y;
236 unsigned short width, height;
Ben Cheng655a7c02013-10-16 16:09:24 -0700237} drm_r128_blit_t;
238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
239typedef struct drm_r128_depth {
Tao Baod7db5942015-01-28 10:07:51 -0800240 enum {
241 R128_WRITE_SPAN = 0x01,
242 R128_WRITE_PIXELS = 0x02,
Ben Cheng655a7c02013-10-16 16:09:24 -0700243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800244 R128_READ_SPAN = 0x03,
245 R128_READ_PIXELS = 0x04
246 } func;
247 int n;
Ben Cheng655a7c02013-10-16 16:09:24 -0700248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800249 int __user * x;
250 int __user * y;
251 unsigned int __user * buffer;
252 unsigned char __user * mask;
Ben Cheng655a7c02013-10-16 16:09:24 -0700253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
254} drm_r128_depth_t;
255typedef struct drm_r128_stipple {
Tao Baod7db5942015-01-28 10:07:51 -0800256 unsigned int __user * mask;
Ben Cheng655a7c02013-10-16 16:09:24 -0700257} drm_r128_stipple_t;
258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
259typedef struct drm_r128_indirect {
Tao Baod7db5942015-01-28 10:07:51 -0800260 int idx;
261 int start;
262 int end;
Ben Cheng655a7c02013-10-16 16:09:24 -0700263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800264 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700265} drm_r128_indirect_t;
266typedef struct drm_r128_fullscreen {
Tao Baod7db5942015-01-28 10:07:51 -0800267 enum {
Ben Cheng655a7c02013-10-16 16:09:24 -0700268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800269 R128_INIT_FULLSCREEN = 0x01,
270 R128_CLEANUP_FULLSCREEN = 0x02
271 } func;
Ben Cheng655a7c02013-10-16 16:09:24 -0700272} drm_r128_fullscreen_t;
273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
274#define R128_PARAM_IRQ_NR 1
275typedef struct drm_r128_getparam {
Tao Baod7db5942015-01-28 10:07:51 -0800276 int param;
277 void __user * value;
Ben Cheng655a7c02013-10-16 16:09:24 -0700278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
279} drm_r128_getparam_t;
280#endif