Jon West | 96501cc | 2021-04-06 13:09:18 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause |
| 2 | /* Copyright(c) 2018-2019 Realtek Corporation |
| 3 | */ |
| 4 | |
| 5 | #include <linux/iopoll.h> |
| 6 | |
| 7 | #include "main.h" |
| 8 | #include "efuse.h" |
| 9 | #include "reg.h" |
| 10 | #include "debug.h" |
| 11 | |
| 12 | #define RTW_EFUSE_BANK_WIFI 0x0 |
| 13 | |
| 14 | static void switch_efuse_bank(struct rtw_dev *rtwdev) |
| 15 | { |
| 16 | rtw_write32_mask(rtwdev, REG_LDO_EFUSE_CTRL, BIT_MASK_EFUSE_BANK_SEL, |
| 17 | RTW_EFUSE_BANK_WIFI); |
| 18 | } |
| 19 | |
| 20 | #define invalid_efuse_header(hdr1, hdr2) \ |
| 21 | ((hdr1) == 0xff || (((hdr1) & 0x1f) == 0xf && (hdr2) == 0xff)) |
| 22 | #define invalid_efuse_content(word_en, i) \ |
| 23 | (((word_en) & BIT(i)) != 0x0) |
| 24 | #define get_efuse_blk_idx_2_byte(hdr1, hdr2) \ |
| 25 | ((((hdr2) & 0xf0) >> 1) | (((hdr1) >> 5) & 0x07)) |
| 26 | #define get_efuse_blk_idx_1_byte(hdr1) \ |
| 27 | (((hdr1) & 0xf0) >> 4) |
| 28 | #define block_idx_to_logical_idx(blk_idx, i) \ |
| 29 | (((blk_idx) << 3) + ((i) << 1)) |
| 30 | |
| 31 | /* efuse header format |
| 32 | * |
| 33 | * | 7 5 4 0 | 7 4 3 0 | 15 8 7 0 | |
| 34 | * block[2:0] 0 1111 block[6:3] word_en[3:0] byte0 byte1 |
| 35 | * | header 1 (optional) | header 2 | word N | |
| 36 | * |
| 37 | * word_en: 4 bits each word. 0 -> write; 1 -> not write |
| 38 | * N: 1~4, depends on word_en |
| 39 | */ |
| 40 | static int rtw_dump_logical_efuse_map(struct rtw_dev *rtwdev, u8 *phy_map, |
| 41 | u8 *log_map) |
| 42 | { |
| 43 | u32 physical_size = rtwdev->efuse.physical_size; |
| 44 | u32 protect_size = rtwdev->efuse.protect_size; |
| 45 | u32 logical_size = rtwdev->efuse.logical_size; |
| 46 | u32 phy_idx, log_idx; |
| 47 | u8 hdr1, hdr2; |
| 48 | u8 blk_idx; |
| 49 | u8 word_en; |
| 50 | int i; |
| 51 | |
| 52 | for (phy_idx = 0; phy_idx < physical_size - protect_size;) { |
| 53 | hdr1 = phy_map[phy_idx]; |
| 54 | hdr2 = phy_map[phy_idx + 1]; |
| 55 | if (invalid_efuse_header(hdr1, hdr2)) |
| 56 | break; |
| 57 | |
| 58 | if ((hdr1 & 0x1f) == 0xf) { |
| 59 | /* 2-byte header format */ |
| 60 | blk_idx = get_efuse_blk_idx_2_byte(hdr1, hdr2); |
| 61 | word_en = hdr2 & 0xf; |
| 62 | phy_idx += 2; |
| 63 | } else { |
| 64 | /* 1-byte header format */ |
| 65 | blk_idx = get_efuse_blk_idx_1_byte(hdr1); |
| 66 | word_en = hdr1 & 0xf; |
| 67 | phy_idx += 1; |
| 68 | } |
| 69 | |
| 70 | for (i = 0; i < 4; i++) { |
| 71 | if (invalid_efuse_content(word_en, i)) |
| 72 | continue; |
| 73 | |
| 74 | log_idx = block_idx_to_logical_idx(blk_idx, i); |
| 75 | if (phy_idx + 1 > physical_size - protect_size || |
| 76 | log_idx + 1 > logical_size) |
| 77 | return -EINVAL; |
| 78 | |
| 79 | log_map[log_idx] = phy_map[phy_idx]; |
| 80 | log_map[log_idx + 1] = phy_map[phy_idx + 1]; |
| 81 | phy_idx += 2; |
| 82 | } |
| 83 | } |
| 84 | return 0; |
| 85 | } |
| 86 | |
| 87 | static int rtw_dump_physical_efuse_map(struct rtw_dev *rtwdev, u8 *map) |
| 88 | { |
| 89 | struct rtw_chip_info *chip = rtwdev->chip; |
| 90 | u32 size = rtwdev->efuse.physical_size; |
| 91 | u32 efuse_ctl; |
| 92 | u32 addr; |
| 93 | u32 cnt; |
| 94 | |
| 95 | rtw_chip_efuse_grant_on(rtwdev); |
| 96 | |
| 97 | switch_efuse_bank(rtwdev); |
| 98 | |
| 99 | /* disable 2.5V LDO */ |
| 100 | chip->ops->cfg_ldo25(rtwdev, false); |
| 101 | |
| 102 | efuse_ctl = rtw_read32(rtwdev, REG_EFUSE_CTRL); |
| 103 | |
| 104 | for (addr = 0; addr < size; addr++) { |
| 105 | efuse_ctl &= ~(BIT_MASK_EF_DATA | BITS_EF_ADDR); |
| 106 | efuse_ctl |= (addr & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR; |
| 107 | rtw_write32(rtwdev, REG_EFUSE_CTRL, efuse_ctl & (~BIT_EF_FLAG)); |
| 108 | |
| 109 | cnt = 1000000; |
| 110 | do { |
| 111 | udelay(1); |
| 112 | efuse_ctl = rtw_read32(rtwdev, REG_EFUSE_CTRL); |
| 113 | if (--cnt == 0) |
| 114 | return -EBUSY; |
| 115 | } while (!(efuse_ctl & BIT_EF_FLAG)); |
| 116 | |
| 117 | *(map + addr) = (u8)(efuse_ctl & BIT_MASK_EF_DATA); |
| 118 | } |
| 119 | |
| 120 | rtw_chip_efuse_grant_off(rtwdev); |
| 121 | |
| 122 | return 0; |
| 123 | } |
| 124 | |
| 125 | int rtw_read8_physical_efuse(struct rtw_dev *rtwdev, u16 addr, u8 *data) |
| 126 | { |
| 127 | u32 efuse_ctl; |
| 128 | int ret; |
| 129 | |
| 130 | rtw_write32_mask(rtwdev, REG_EFUSE_CTRL, 0x3ff00, addr); |
| 131 | rtw_write32_clr(rtwdev, REG_EFUSE_CTRL, BIT_EF_FLAG); |
| 132 | |
| 133 | ret = read_poll_timeout(rtw_read32, efuse_ctl, efuse_ctl & BIT_EF_FLAG, |
| 134 | 1000, 100000, false, rtwdev, REG_EFUSE_CTRL); |
| 135 | if (ret) { |
| 136 | *data = EFUSE_READ_FAIL; |
| 137 | return ret; |
| 138 | } |
| 139 | |
| 140 | *data = rtw_read8(rtwdev, REG_EFUSE_CTRL); |
| 141 | |
| 142 | return 0; |
| 143 | } |
| 144 | EXPORT_SYMBOL(rtw_read8_physical_efuse); |
| 145 | |
| 146 | int rtw_parse_efuse_map(struct rtw_dev *rtwdev) |
| 147 | { |
| 148 | struct rtw_chip_info *chip = rtwdev->chip; |
| 149 | struct rtw_efuse *efuse = &rtwdev->efuse; |
| 150 | u32 phy_size = efuse->physical_size; |
| 151 | u32 log_size = efuse->logical_size; |
| 152 | u8 *phy_map = NULL; |
| 153 | u8 *log_map = NULL; |
| 154 | int ret = 0; |
| 155 | |
| 156 | phy_map = kmalloc(phy_size, GFP_KERNEL); |
| 157 | log_map = kmalloc(log_size, GFP_KERNEL); |
| 158 | if (!phy_map || !log_map) { |
| 159 | ret = -ENOMEM; |
| 160 | goto out_free; |
| 161 | } |
| 162 | |
| 163 | ret = rtw_dump_physical_efuse_map(rtwdev, phy_map); |
| 164 | if (ret) { |
| 165 | rtw_err(rtwdev, "failed to dump efuse physical map\n"); |
| 166 | goto out_free; |
| 167 | } |
| 168 | |
| 169 | memset(log_map, 0xff, log_size); |
| 170 | ret = rtw_dump_logical_efuse_map(rtwdev, phy_map, log_map); |
| 171 | if (ret) { |
| 172 | rtw_err(rtwdev, "failed to dump efuse logical map\n"); |
| 173 | goto out_free; |
| 174 | } |
| 175 | |
| 176 | ret = chip->ops->read_efuse(rtwdev, log_map); |
| 177 | if (ret) { |
| 178 | rtw_err(rtwdev, "failed to read efuse map\n"); |
| 179 | goto out_free; |
| 180 | } |
| 181 | |
| 182 | out_free: |
| 183 | kfree(log_map); |
| 184 | kfree(phy_map); |
| 185 | |
| 186 | return ret; |
| 187 | } |