Jon West | 96501cc | 2021-04-06 13:09:18 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause |
| 2 | /* Copyright(c) 2018-2019 Realtek Corporation |
| 3 | */ |
| 4 | |
| 5 | #include "main.h" |
| 6 | #include "regd.h" |
| 7 | #include "fw.h" |
| 8 | #include "ps.h" |
| 9 | #include "sec.h" |
| 10 | #include "mac.h" |
| 11 | #include "coex.h" |
| 12 | #include "phy.h" |
| 13 | #include "reg.h" |
| 14 | #include "efuse.h" |
| 15 | #include "tx.h" |
| 16 | #include "debug.h" |
| 17 | #include "bf.h" |
| 18 | |
| 19 | bool rtw_disable_lps_deep_mode; |
| 20 | EXPORT_SYMBOL(rtw_disable_lps_deep_mode); |
| 21 | bool rtw_bf_support = true; |
| 22 | unsigned int rtw_debug_mask; |
| 23 | EXPORT_SYMBOL(rtw_debug_mask); |
| 24 | |
| 25 | module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644); |
| 26 | module_param_named(support_bf, rtw_bf_support, bool, 0644); |
| 27 | module_param_named(debug_mask, rtw_debug_mask, uint, 0644); |
| 28 | |
| 29 | MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS"); |
| 30 | MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support"); |
| 31 | MODULE_PARM_DESC(debug_mask, "Debugging mask"); |
| 32 | |
| 33 | static struct ieee80211_channel rtw_channeltable_2g[] = { |
| 34 | {.center_freq = 2412, .hw_value = 1,}, |
| 35 | {.center_freq = 2417, .hw_value = 2,}, |
| 36 | {.center_freq = 2422, .hw_value = 3,}, |
| 37 | {.center_freq = 2427, .hw_value = 4,}, |
| 38 | {.center_freq = 2432, .hw_value = 5,}, |
| 39 | {.center_freq = 2437, .hw_value = 6,}, |
| 40 | {.center_freq = 2442, .hw_value = 7,}, |
| 41 | {.center_freq = 2447, .hw_value = 8,}, |
| 42 | {.center_freq = 2452, .hw_value = 9,}, |
| 43 | {.center_freq = 2457, .hw_value = 10,}, |
| 44 | {.center_freq = 2462, .hw_value = 11,}, |
| 45 | {.center_freq = 2467, .hw_value = 12,}, |
| 46 | {.center_freq = 2472, .hw_value = 13,}, |
| 47 | {.center_freq = 2484, .hw_value = 14,}, |
| 48 | }; |
| 49 | |
| 50 | static struct ieee80211_channel rtw_channeltable_5g[] = { |
| 51 | {.center_freq = 5180, .hw_value = 36,}, |
| 52 | {.center_freq = 5200, .hw_value = 40,}, |
| 53 | {.center_freq = 5220, .hw_value = 44,}, |
| 54 | {.center_freq = 5240, .hw_value = 48,}, |
| 55 | {.center_freq = 5260, .hw_value = 52,}, |
| 56 | {.center_freq = 5280, .hw_value = 56,}, |
| 57 | {.center_freq = 5300, .hw_value = 60,}, |
| 58 | {.center_freq = 5320, .hw_value = 64,}, |
| 59 | {.center_freq = 5500, .hw_value = 100,}, |
| 60 | {.center_freq = 5520, .hw_value = 104,}, |
| 61 | {.center_freq = 5540, .hw_value = 108,}, |
| 62 | {.center_freq = 5560, .hw_value = 112,}, |
| 63 | {.center_freq = 5580, .hw_value = 116,}, |
| 64 | {.center_freq = 5600, .hw_value = 120,}, |
| 65 | {.center_freq = 5620, .hw_value = 124,}, |
| 66 | {.center_freq = 5640, .hw_value = 128,}, |
| 67 | {.center_freq = 5660, .hw_value = 132,}, |
| 68 | {.center_freq = 5680, .hw_value = 136,}, |
| 69 | {.center_freq = 5700, .hw_value = 140,}, |
| 70 | {.center_freq = 5720, .hw_value = 144,}, |
| 71 | {.center_freq = 5745, .hw_value = 149,}, |
| 72 | {.center_freq = 5765, .hw_value = 153,}, |
| 73 | {.center_freq = 5785, .hw_value = 157,}, |
| 74 | {.center_freq = 5805, .hw_value = 161,}, |
| 75 | {.center_freq = 5825, .hw_value = 165, |
| 76 | .flags = IEEE80211_CHAN_NO_HT40MINUS}, |
| 77 | }; |
| 78 | |
| 79 | static struct ieee80211_rate rtw_ratetable[] = { |
| 80 | {.bitrate = 10, .hw_value = 0x00,}, |
| 81 | {.bitrate = 20, .hw_value = 0x01,}, |
| 82 | {.bitrate = 55, .hw_value = 0x02,}, |
| 83 | {.bitrate = 110, .hw_value = 0x03,}, |
| 84 | {.bitrate = 60, .hw_value = 0x04,}, |
| 85 | {.bitrate = 90, .hw_value = 0x05,}, |
| 86 | {.bitrate = 120, .hw_value = 0x06,}, |
| 87 | {.bitrate = 180, .hw_value = 0x07,}, |
| 88 | {.bitrate = 240, .hw_value = 0x08,}, |
| 89 | {.bitrate = 360, .hw_value = 0x09,}, |
| 90 | {.bitrate = 480, .hw_value = 0x0a,}, |
| 91 | {.bitrate = 540, .hw_value = 0x0b,}, |
| 92 | }; |
| 93 | |
| 94 | u16 rtw_desc_to_bitrate(u8 desc_rate) |
| 95 | { |
| 96 | struct ieee80211_rate rate; |
| 97 | |
| 98 | if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n")) |
| 99 | return 0; |
| 100 | |
| 101 | rate = rtw_ratetable[desc_rate]; |
| 102 | |
| 103 | return rate.bitrate; |
| 104 | } |
| 105 | |
| 106 | static struct ieee80211_supported_band rtw_band_2ghz = { |
| 107 | .band = NL80211_BAND_2GHZ, |
| 108 | |
| 109 | .channels = rtw_channeltable_2g, |
| 110 | .n_channels = ARRAY_SIZE(rtw_channeltable_2g), |
| 111 | |
| 112 | .bitrates = rtw_ratetable, |
| 113 | .n_bitrates = ARRAY_SIZE(rtw_ratetable), |
| 114 | |
| 115 | .ht_cap = {0}, |
| 116 | .vht_cap = {0}, |
| 117 | }; |
| 118 | |
| 119 | static struct ieee80211_supported_band rtw_band_5ghz = { |
| 120 | .band = NL80211_BAND_5GHZ, |
| 121 | |
| 122 | .channels = rtw_channeltable_5g, |
| 123 | .n_channels = ARRAY_SIZE(rtw_channeltable_5g), |
| 124 | |
| 125 | /* 5G has no CCK rates */ |
| 126 | .bitrates = rtw_ratetable + 4, |
| 127 | .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4, |
| 128 | |
| 129 | .ht_cap = {0}, |
| 130 | .vht_cap = {0}, |
| 131 | }; |
| 132 | |
| 133 | struct rtw_watch_dog_iter_data { |
| 134 | struct rtw_dev *rtwdev; |
| 135 | struct rtw_vif *rtwvif; |
| 136 | }; |
| 137 | |
| 138 | static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif) |
| 139 | { |
| 140 | struct rtw_bf_info *bf_info = &rtwdev->bf_info; |
| 141 | u8 fix_rate_enable = 0; |
| 142 | u8 new_csi_rate_idx; |
| 143 | |
| 144 | if (rtwvif->bfee.role != RTW_BFEE_SU && |
| 145 | rtwvif->bfee.role != RTW_BFEE_MU) |
| 146 | return; |
| 147 | |
| 148 | rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, |
| 149 | bf_info->cur_csi_rpt_rate, |
| 150 | fix_rate_enable, &new_csi_rate_idx); |
| 151 | |
| 152 | if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) |
| 153 | bf_info->cur_csi_rpt_rate = new_csi_rate_idx; |
| 154 | } |
| 155 | |
| 156 | static void rtw_vif_watch_dog_iter(void *data, u8 *mac, |
| 157 | struct ieee80211_vif *vif) |
| 158 | { |
| 159 | struct rtw_watch_dog_iter_data *iter_data = data; |
| 160 | struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; |
| 161 | |
| 162 | if (vif->type == NL80211_IFTYPE_STATION) |
| 163 | if (vif->bss_conf.assoc) |
| 164 | iter_data->rtwvif = rtwvif; |
| 165 | |
| 166 | rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif); |
| 167 | |
| 168 | rtwvif->stats.tx_unicast = 0; |
| 169 | rtwvif->stats.rx_unicast = 0; |
| 170 | rtwvif->stats.tx_cnt = 0; |
| 171 | rtwvif->stats.rx_cnt = 0; |
| 172 | } |
| 173 | |
| 174 | /* process TX/RX statistics periodically for hardware, |
| 175 | * the information helps hardware to enhance performance |
| 176 | */ |
| 177 | static void rtw_watch_dog_work(struct work_struct *work) |
| 178 | { |
| 179 | struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, |
| 180 | watch_dog_work.work); |
| 181 | struct rtw_traffic_stats *stats = &rtwdev->stats; |
| 182 | struct rtw_watch_dog_iter_data data = {}; |
| 183 | bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); |
| 184 | bool ps_active; |
| 185 | |
| 186 | mutex_lock(&rtwdev->mutex); |
| 187 | |
| 188 | if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags)) |
| 189 | goto unlock; |
| 190 | |
| 191 | ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, |
| 192 | RTW_WATCH_DOG_DELAY_TIME); |
| 193 | |
| 194 | if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100) |
| 195 | set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); |
| 196 | else |
| 197 | clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); |
| 198 | |
| 199 | if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags)) |
| 200 | rtw_coex_wl_status_change_notify(rtwdev, 0); |
| 201 | |
| 202 | if (stats->tx_cnt > RTW_LPS_THRESHOLD || |
| 203 | stats->rx_cnt > RTW_LPS_THRESHOLD) |
| 204 | ps_active = true; |
| 205 | else |
| 206 | ps_active = false; |
| 207 | |
| 208 | ewma_tp_add(&stats->tx_ewma_tp, |
| 209 | (u32)(stats->tx_unicast >> RTW_TP_SHIFT)); |
| 210 | ewma_tp_add(&stats->rx_ewma_tp, |
| 211 | (u32)(stats->rx_unicast >> RTW_TP_SHIFT)); |
| 212 | stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); |
| 213 | stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); |
| 214 | |
| 215 | /* reset tx/rx statictics */ |
| 216 | stats->tx_unicast = 0; |
| 217 | stats->rx_unicast = 0; |
| 218 | stats->tx_cnt = 0; |
| 219 | stats->rx_cnt = 0; |
| 220 | |
| 221 | if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) |
| 222 | goto unlock; |
| 223 | |
| 224 | /* make sure BB/RF is working for dynamic mech */ |
| 225 | rtw_leave_lps(rtwdev); |
| 226 | |
| 227 | rtw_phy_dynamic_mechanism(rtwdev); |
| 228 | |
| 229 | data.rtwdev = rtwdev; |
| 230 | /* use atomic version to avoid taking local->iflist_mtx mutex */ |
| 231 | rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data); |
| 232 | |
| 233 | /* fw supports only one station associated to enter lps, if there are |
| 234 | * more than two stations associated to the AP, then we can not enter |
| 235 | * lps, because fw does not handle the overlapped beacon interval |
| 236 | * |
| 237 | * mac80211 should iterate vifs and determine if driver can enter |
| 238 | * ps by passing IEEE80211_CONF_PS to us, all we need to do is to |
| 239 | * get that vif and check if device is having traffic more than the |
| 240 | * threshold. |
| 241 | */ |
| 242 | if (rtwdev->ps_enabled && data.rtwvif && !ps_active) |
| 243 | rtw_enter_lps(rtwdev, data.rtwvif->port); |
| 244 | |
| 245 | rtwdev->watch_dog_cnt++; |
| 246 | |
| 247 | unlock: |
| 248 | mutex_unlock(&rtwdev->mutex); |
| 249 | } |
| 250 | |
| 251 | static void rtw_c2h_work(struct work_struct *work) |
| 252 | { |
| 253 | struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work); |
| 254 | struct sk_buff *skb, *tmp; |
| 255 | |
| 256 | skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { |
| 257 | skb_unlink(skb, &rtwdev->c2h_queue); |
| 258 | rtw_fw_c2h_cmd_handle(rtwdev, skb); |
| 259 | dev_kfree_skb_any(skb); |
| 260 | } |
| 261 | } |
| 262 | |
| 263 | static u8 rtw_acquire_macid(struct rtw_dev *rtwdev) |
| 264 | { |
| 265 | unsigned long mac_id; |
| 266 | |
| 267 | mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM); |
| 268 | if (mac_id < RTW_MAX_MAC_ID_NUM) |
| 269 | set_bit(mac_id, rtwdev->mac_id_map); |
| 270 | |
| 271 | return mac_id; |
| 272 | } |
| 273 | |
| 274 | int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, |
| 275 | struct ieee80211_vif *vif) |
| 276 | { |
| 277 | struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; |
| 278 | int i; |
| 279 | |
| 280 | si->mac_id = rtw_acquire_macid(rtwdev); |
| 281 | if (si->mac_id >= RTW_MAX_MAC_ID_NUM) |
| 282 | return -ENOSPC; |
| 283 | |
| 284 | si->sta = sta; |
| 285 | si->vif = vif; |
| 286 | si->init_ra_lv = 1; |
| 287 | ewma_rssi_init(&si->avg_rssi); |
| 288 | for (i = 0; i < ARRAY_SIZE(sta->txq); i++) |
| 289 | rtw_txq_init(rtwdev, sta->txq[i]); |
| 290 | |
| 291 | rtw_update_sta_info(rtwdev, si); |
| 292 | rtw_fw_media_status_report(rtwdev, si->mac_id, true); |
| 293 | |
| 294 | rtwdev->sta_cnt++; |
| 295 | rtw_info(rtwdev, "sta %pM joined with macid %d\n", |
| 296 | sta->addr, si->mac_id); |
| 297 | |
| 298 | return 0; |
| 299 | } |
| 300 | |
| 301 | void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, |
| 302 | bool fw_exist) |
| 303 | { |
| 304 | struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; |
| 305 | int i; |
| 306 | |
| 307 | rtw_release_macid(rtwdev, si->mac_id); |
| 308 | if (fw_exist) |
| 309 | rtw_fw_media_status_report(rtwdev, si->mac_id, false); |
| 310 | |
| 311 | for (i = 0; i < ARRAY_SIZE(sta->txq); i++) |
| 312 | rtw_txq_cleanup(rtwdev, sta->txq[i]); |
| 313 | |
| 314 | kfree(si->mask); |
| 315 | |
| 316 | rtwdev->sta_cnt--; |
| 317 | rtw_info(rtwdev, "sta %pM with macid %d left\n", |
| 318 | sta->addr, si->mac_id); |
| 319 | } |
| 320 | |
| 321 | static bool rtw_fw_dump_crash_log(struct rtw_dev *rtwdev) |
| 322 | { |
| 323 | u32 size = rtwdev->chip->fw_rxff_size; |
| 324 | u32 *buf; |
| 325 | u8 seq; |
| 326 | bool ret = true; |
| 327 | |
| 328 | buf = vmalloc(size); |
| 329 | if (!buf) |
| 330 | goto exit; |
| 331 | |
| 332 | if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) { |
| 333 | rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n"); |
| 334 | goto free_buf; |
| 335 | } |
| 336 | |
| 337 | if (GET_FW_DUMP_LEN(buf) == 0) { |
| 338 | rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n"); |
| 339 | goto free_buf; |
| 340 | } |
| 341 | |
| 342 | seq = GET_FW_DUMP_SEQ(buf); |
| 343 | if (seq > 0 && seq != (rtwdev->fw.prev_dump_seq + 1)) { |
| 344 | rtw_dbg(rtwdev, RTW_DBG_FW, |
| 345 | "fw crash dump's seq is wrong: %d\n", seq); |
| 346 | goto free_buf; |
| 347 | } |
| 348 | if (seq == 0 && |
| 349 | (GET_FW_DUMP_TLV_TYPE(buf) != FW_CD_TYPE || |
| 350 | GET_FW_DUMP_TLV_LEN(buf) != FW_CD_LEN || |
| 351 | GET_FW_DUMP_TLV_VAL(buf) != FW_CD_VAL)) { |
| 352 | rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's tlv is wrong\n"); |
| 353 | goto free_buf; |
| 354 | } |
| 355 | |
| 356 | print_hex_dump_bytes("rtw88 fw dump: ", DUMP_PREFIX_OFFSET, buf, size); |
| 357 | |
| 358 | if (GET_FW_DUMP_MORE(buf) == 1) { |
| 359 | rtwdev->fw.prev_dump_seq = seq; |
| 360 | ret = false; |
| 361 | } |
| 362 | |
| 363 | free_buf: |
| 364 | vfree(buf); |
| 365 | exit: |
| 366 | rtw_write8(rtwdev, REG_MCU_TST_CFG, 0); |
| 367 | |
| 368 | return ret; |
| 369 | } |
| 370 | |
| 371 | void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, |
| 372 | struct ieee80211_bss_conf *conf) |
| 373 | { |
| 374 | if (conf && conf->assoc) { |
| 375 | rtwvif->aid = conf->aid; |
| 376 | rtwvif->net_type = RTW_NET_MGD_LINKED; |
| 377 | } else { |
| 378 | rtwvif->aid = 0; |
| 379 | rtwvif->net_type = RTW_NET_NO_LINK; |
| 380 | } |
| 381 | } |
| 382 | |
| 383 | static void rtw_reset_key_iter(struct ieee80211_hw *hw, |
| 384 | struct ieee80211_vif *vif, |
| 385 | struct ieee80211_sta *sta, |
| 386 | struct ieee80211_key_conf *key, |
| 387 | void *data) |
| 388 | { |
| 389 | struct rtw_dev *rtwdev = (struct rtw_dev *)data; |
| 390 | struct rtw_sec_desc *sec = &rtwdev->sec; |
| 391 | |
| 392 | rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx); |
| 393 | } |
| 394 | |
| 395 | static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta) |
| 396 | { |
| 397 | struct rtw_dev *rtwdev = (struct rtw_dev *)data; |
| 398 | |
| 399 | if (rtwdev->sta_cnt == 0) { |
| 400 | rtw_warn(rtwdev, "sta count before reset should not be 0\n"); |
| 401 | return; |
| 402 | } |
| 403 | rtw_sta_remove(rtwdev, sta, false); |
| 404 | } |
| 405 | |
| 406 | static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
| 407 | { |
| 408 | struct rtw_dev *rtwdev = (struct rtw_dev *)data; |
| 409 | struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; |
| 410 | |
| 411 | rtw_bf_disassoc(rtwdev, vif, NULL); |
| 412 | rtw_vif_assoc_changed(rtwvif, NULL); |
| 413 | rtw_txq_cleanup(rtwdev, vif->txq); |
| 414 | } |
| 415 | |
| 416 | void rtw_fw_recovery(struct rtw_dev *rtwdev) |
| 417 | { |
| 418 | if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags)) |
| 419 | ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work); |
| 420 | } |
| 421 | |
| 422 | static void rtw_fw_recovery_work(struct work_struct *work) |
| 423 | { |
| 424 | struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, |
| 425 | fw_recovery_work); |
| 426 | |
| 427 | /* rtw_fw_dump_crash_log() returns false indicates that there are |
| 428 | * still more log to dump. Driver set 0x1cf[7:0] = 0x1 to tell firmware |
| 429 | * to dump the remaining part of the log, and firmware will trigger an |
| 430 | * IMR_C2HCMD interrupt to inform driver the log is ready. |
| 431 | */ |
| 432 | if (!rtw_fw_dump_crash_log(rtwdev)) { |
| 433 | rtw_write8(rtwdev, REG_HRCV_MSG, 1); |
| 434 | return; |
| 435 | } |
| 436 | rtwdev->fw.prev_dump_seq = 0; |
| 437 | |
| 438 | WARN(1, "firmware crash, start reset and recover\n"); |
| 439 | |
| 440 | mutex_lock(&rtwdev->mutex); |
| 441 | |
| 442 | set_bit(RTW_FLAG_RESTARTING, rtwdev->flags); |
| 443 | rcu_read_lock(); |
| 444 | rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev); |
| 445 | rcu_read_unlock(); |
| 446 | rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev); |
| 447 | rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev); |
| 448 | rtw_enter_ips(rtwdev); |
| 449 | |
| 450 | mutex_unlock(&rtwdev->mutex); |
| 451 | |
| 452 | ieee80211_restart_hw(rtwdev->hw); |
| 453 | } |
| 454 | |
| 455 | struct rtw_txq_ba_iter_data { |
| 456 | }; |
| 457 | |
| 458 | static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta) |
| 459 | { |
| 460 | struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; |
| 461 | int ret; |
| 462 | u8 tid; |
| 463 | |
| 464 | tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); |
| 465 | while (tid != IEEE80211_NUM_TIDS) { |
| 466 | clear_bit(tid, si->tid_ba); |
| 467 | ret = ieee80211_start_tx_ba_session(sta, tid, 0); |
| 468 | if (ret == -EINVAL) { |
| 469 | struct ieee80211_txq *txq; |
| 470 | struct rtw_txq *rtwtxq; |
| 471 | |
| 472 | txq = sta->txq[tid]; |
| 473 | rtwtxq = (struct rtw_txq *)txq->drv_priv; |
| 474 | set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags); |
| 475 | } |
| 476 | |
| 477 | tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); |
| 478 | } |
| 479 | } |
| 480 | |
| 481 | static void rtw_txq_ba_work(struct work_struct *work) |
| 482 | { |
| 483 | struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work); |
| 484 | struct rtw_txq_ba_iter_data data; |
| 485 | |
| 486 | rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data); |
| 487 | } |
| 488 | |
| 489 | void rtw_get_channel_params(struct cfg80211_chan_def *chandef, |
| 490 | struct rtw_channel_params *chan_params) |
| 491 | { |
| 492 | struct ieee80211_channel *channel = chandef->chan; |
| 493 | enum nl80211_chan_width width = chandef->width; |
| 494 | u8 *cch_by_bw = chan_params->cch_by_bw; |
| 495 | u32 primary_freq, center_freq; |
| 496 | u8 center_chan; |
| 497 | u8 bandwidth = RTW_CHANNEL_WIDTH_20; |
| 498 | u8 primary_chan_idx = 0; |
| 499 | u8 i; |
| 500 | |
| 501 | center_chan = channel->hw_value; |
| 502 | primary_freq = channel->center_freq; |
| 503 | center_freq = chandef->center_freq1; |
| 504 | |
| 505 | /* assign the center channel used while 20M bw is selected */ |
| 506 | cch_by_bw[RTW_CHANNEL_WIDTH_20] = channel->hw_value; |
| 507 | |
| 508 | switch (width) { |
| 509 | case NL80211_CHAN_WIDTH_20_NOHT: |
| 510 | case NL80211_CHAN_WIDTH_20: |
| 511 | bandwidth = RTW_CHANNEL_WIDTH_20; |
| 512 | primary_chan_idx = RTW_SC_DONT_CARE; |
| 513 | break; |
| 514 | case NL80211_CHAN_WIDTH_40: |
| 515 | bandwidth = RTW_CHANNEL_WIDTH_40; |
| 516 | if (primary_freq > center_freq) { |
| 517 | primary_chan_idx = RTW_SC_20_UPPER; |
| 518 | center_chan -= 2; |
| 519 | } else { |
| 520 | primary_chan_idx = RTW_SC_20_LOWER; |
| 521 | center_chan += 2; |
| 522 | } |
| 523 | break; |
| 524 | case NL80211_CHAN_WIDTH_80: |
| 525 | bandwidth = RTW_CHANNEL_WIDTH_80; |
| 526 | if (primary_freq > center_freq) { |
| 527 | if (primary_freq - center_freq == 10) { |
| 528 | primary_chan_idx = RTW_SC_20_UPPER; |
| 529 | center_chan -= 2; |
| 530 | } else { |
| 531 | primary_chan_idx = RTW_SC_20_UPMOST; |
| 532 | center_chan -= 6; |
| 533 | } |
| 534 | /* assign the center channel used |
| 535 | * while 40M bw is selected |
| 536 | */ |
| 537 | cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan + 4; |
| 538 | } else { |
| 539 | if (center_freq - primary_freq == 10) { |
| 540 | primary_chan_idx = RTW_SC_20_LOWER; |
| 541 | center_chan += 2; |
| 542 | } else { |
| 543 | primary_chan_idx = RTW_SC_20_LOWEST; |
| 544 | center_chan += 6; |
| 545 | } |
| 546 | /* assign the center channel used |
| 547 | * while 40M bw is selected |
| 548 | */ |
| 549 | cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan - 4; |
| 550 | } |
| 551 | break; |
| 552 | default: |
| 553 | center_chan = 0; |
| 554 | break; |
| 555 | } |
| 556 | |
| 557 | chan_params->center_chan = center_chan; |
| 558 | chan_params->bandwidth = bandwidth; |
| 559 | chan_params->primary_chan_idx = primary_chan_idx; |
| 560 | |
| 561 | /* assign the center channel used while current bw is selected */ |
| 562 | cch_by_bw[bandwidth] = center_chan; |
| 563 | |
| 564 | for (i = bandwidth + 1; i <= RTW_MAX_CHANNEL_WIDTH; i++) |
| 565 | cch_by_bw[i] = 0; |
| 566 | } |
| 567 | |
| 568 | void rtw_set_channel(struct rtw_dev *rtwdev) |
| 569 | { |
| 570 | struct ieee80211_hw *hw = rtwdev->hw; |
| 571 | struct rtw_hal *hal = &rtwdev->hal; |
| 572 | struct rtw_chip_info *chip = rtwdev->chip; |
| 573 | struct rtw_channel_params ch_param; |
| 574 | u8 center_chan, bandwidth, primary_chan_idx; |
| 575 | u8 i; |
| 576 | |
| 577 | rtw_get_channel_params(&hw->conf.chandef, &ch_param); |
| 578 | if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) |
| 579 | return; |
| 580 | |
| 581 | center_chan = ch_param.center_chan; |
| 582 | bandwidth = ch_param.bandwidth; |
| 583 | primary_chan_idx = ch_param.primary_chan_idx; |
| 584 | |
| 585 | hal->current_band_width = bandwidth; |
| 586 | hal->current_channel = center_chan; |
| 587 | hal->current_band_type = center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G; |
| 588 | |
| 589 | for (i = RTW_CHANNEL_WIDTH_20; i <= RTW_MAX_CHANNEL_WIDTH; i++) |
| 590 | hal->cch_by_bw[i] = ch_param.cch_by_bw[i]; |
| 591 | |
| 592 | chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx); |
| 593 | |
| 594 | if (hal->current_band_type == RTW_BAND_5G) { |
| 595 | rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G); |
| 596 | } else { |
| 597 | if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) |
| 598 | rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G); |
| 599 | else |
| 600 | rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN); |
| 601 | } |
| 602 | |
| 603 | rtw_phy_set_tx_power_level(rtwdev, center_chan); |
| 604 | |
| 605 | /* if the channel isn't set for scanning, we will do RF calibration |
| 606 | * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration |
| 607 | * during scanning on each channel takes too long. |
| 608 | */ |
| 609 | if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) |
| 610 | rtwdev->need_rfk = true; |
| 611 | } |
| 612 | |
| 613 | void rtw_chip_prepare_tx(struct rtw_dev *rtwdev) |
| 614 | { |
| 615 | struct rtw_chip_info *chip = rtwdev->chip; |
| 616 | |
| 617 | if (rtwdev->need_rfk) { |
| 618 | rtwdev->need_rfk = false; |
| 619 | chip->ops->phy_calibration(rtwdev); |
| 620 | } |
| 621 | } |
| 622 | |
| 623 | static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr) |
| 624 | { |
| 625 | int i; |
| 626 | |
| 627 | for (i = 0; i < ETH_ALEN; i++) |
| 628 | rtw_write8(rtwdev, start + i, addr[i]); |
| 629 | } |
| 630 | |
| 631 | void rtw_vif_port_config(struct rtw_dev *rtwdev, |
| 632 | struct rtw_vif *rtwvif, |
| 633 | u32 config) |
| 634 | { |
| 635 | u32 addr, mask; |
| 636 | |
| 637 | if (config & PORT_SET_MAC_ADDR) { |
| 638 | addr = rtwvif->conf->mac_addr.addr; |
| 639 | rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr); |
| 640 | } |
| 641 | if (config & PORT_SET_BSSID) { |
| 642 | addr = rtwvif->conf->bssid.addr; |
| 643 | rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid); |
| 644 | } |
| 645 | if (config & PORT_SET_NET_TYPE) { |
| 646 | addr = rtwvif->conf->net_type.addr; |
| 647 | mask = rtwvif->conf->net_type.mask; |
| 648 | rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); |
| 649 | } |
| 650 | if (config & PORT_SET_AID) { |
| 651 | addr = rtwvif->conf->aid.addr; |
| 652 | mask = rtwvif->conf->aid.mask; |
| 653 | rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); |
| 654 | } |
| 655 | if (config & PORT_SET_BCN_CTRL) { |
| 656 | addr = rtwvif->conf->bcn_ctrl.addr; |
| 657 | mask = rtwvif->conf->bcn_ctrl.mask; |
| 658 | rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); |
| 659 | } |
| 660 | } |
| 661 | |
| 662 | static u8 hw_bw_cap_to_bitamp(u8 bw_cap) |
| 663 | { |
| 664 | u8 bw = 0; |
| 665 | |
| 666 | switch (bw_cap) { |
| 667 | case EFUSE_HW_CAP_IGNORE: |
| 668 | case EFUSE_HW_CAP_SUPP_BW80: |
| 669 | bw |= BIT(RTW_CHANNEL_WIDTH_80); |
| 670 | fallthrough; |
| 671 | case EFUSE_HW_CAP_SUPP_BW40: |
| 672 | bw |= BIT(RTW_CHANNEL_WIDTH_40); |
| 673 | fallthrough; |
| 674 | default: |
| 675 | bw |= BIT(RTW_CHANNEL_WIDTH_20); |
| 676 | break; |
| 677 | } |
| 678 | |
| 679 | return bw; |
| 680 | } |
| 681 | |
| 682 | static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) |
| 683 | { |
| 684 | struct rtw_hal *hal = &rtwdev->hal; |
| 685 | struct rtw_chip_info *chip = rtwdev->chip; |
| 686 | |
| 687 | if (hw_ant_num == EFUSE_HW_CAP_IGNORE || |
| 688 | hw_ant_num >= hal->rf_path_num) |
| 689 | return; |
| 690 | |
| 691 | switch (hw_ant_num) { |
| 692 | case 1: |
| 693 | hal->rf_type = RF_1T1R; |
| 694 | hal->rf_path_num = 1; |
| 695 | if (!chip->fix_rf_phy_num) |
| 696 | hal->rf_phy_num = hal->rf_path_num; |
| 697 | hal->antenna_tx = BB_PATH_A; |
| 698 | hal->antenna_rx = BB_PATH_A; |
| 699 | break; |
| 700 | default: |
| 701 | WARN(1, "invalid hw configuration from efuse\n"); |
| 702 | break; |
| 703 | } |
| 704 | } |
| 705 | |
| 706 | static u64 get_vht_ra_mask(struct ieee80211_sta *sta) |
| 707 | { |
| 708 | u64 ra_mask = 0; |
| 709 | u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map); |
| 710 | u8 vht_mcs_cap; |
| 711 | int i, nss; |
| 712 | |
| 713 | /* 4SS, every two bits for MCS7/8/9 */ |
| 714 | for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) { |
| 715 | vht_mcs_cap = mcs_map & 0x3; |
| 716 | switch (vht_mcs_cap) { |
| 717 | case 2: /* MCS9 */ |
| 718 | ra_mask |= 0x3ffULL << nss; |
| 719 | break; |
| 720 | case 1: /* MCS8 */ |
| 721 | ra_mask |= 0x1ffULL << nss; |
| 722 | break; |
| 723 | case 0: /* MCS7 */ |
| 724 | ra_mask |= 0x0ffULL << nss; |
| 725 | break; |
| 726 | default: |
| 727 | break; |
| 728 | } |
| 729 | } |
| 730 | |
| 731 | return ra_mask; |
| 732 | } |
| 733 | |
| 734 | static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num) |
| 735 | { |
| 736 | u8 rate_id = 0; |
| 737 | |
| 738 | switch (wireless_set) { |
| 739 | case WIRELESS_CCK: |
| 740 | rate_id = RTW_RATEID_B_20M; |
| 741 | break; |
| 742 | case WIRELESS_OFDM: |
| 743 | rate_id = RTW_RATEID_G; |
| 744 | break; |
| 745 | case WIRELESS_CCK | WIRELESS_OFDM: |
| 746 | rate_id = RTW_RATEID_BG; |
| 747 | break; |
| 748 | case WIRELESS_OFDM | WIRELESS_HT: |
| 749 | if (tx_num == 1) |
| 750 | rate_id = RTW_RATEID_GN_N1SS; |
| 751 | else if (tx_num == 2) |
| 752 | rate_id = RTW_RATEID_GN_N2SS; |
| 753 | else if (tx_num == 3) |
| 754 | rate_id = RTW_RATEID_ARFR5_N_3SS; |
| 755 | break; |
| 756 | case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT: |
| 757 | if (bw_mode == RTW_CHANNEL_WIDTH_40) { |
| 758 | if (tx_num == 1) |
| 759 | rate_id = RTW_RATEID_BGN_40M_1SS; |
| 760 | else if (tx_num == 2) |
| 761 | rate_id = RTW_RATEID_BGN_40M_2SS; |
| 762 | else if (tx_num == 3) |
| 763 | rate_id = RTW_RATEID_ARFR5_N_3SS; |
| 764 | else if (tx_num == 4) |
| 765 | rate_id = RTW_RATEID_ARFR7_N_4SS; |
| 766 | } else { |
| 767 | if (tx_num == 1) |
| 768 | rate_id = RTW_RATEID_BGN_20M_1SS; |
| 769 | else if (tx_num == 2) |
| 770 | rate_id = RTW_RATEID_BGN_20M_2SS; |
| 771 | else if (tx_num == 3) |
| 772 | rate_id = RTW_RATEID_ARFR5_N_3SS; |
| 773 | else if (tx_num == 4) |
| 774 | rate_id = RTW_RATEID_ARFR7_N_4SS; |
| 775 | } |
| 776 | break; |
| 777 | case WIRELESS_OFDM | WIRELESS_VHT: |
| 778 | if (tx_num == 1) |
| 779 | rate_id = RTW_RATEID_ARFR1_AC_1SS; |
| 780 | else if (tx_num == 2) |
| 781 | rate_id = RTW_RATEID_ARFR0_AC_2SS; |
| 782 | else if (tx_num == 3) |
| 783 | rate_id = RTW_RATEID_ARFR4_AC_3SS; |
| 784 | else if (tx_num == 4) |
| 785 | rate_id = RTW_RATEID_ARFR6_AC_4SS; |
| 786 | break; |
| 787 | case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT: |
| 788 | if (bw_mode >= RTW_CHANNEL_WIDTH_80) { |
| 789 | if (tx_num == 1) |
| 790 | rate_id = RTW_RATEID_ARFR1_AC_1SS; |
| 791 | else if (tx_num == 2) |
| 792 | rate_id = RTW_RATEID_ARFR0_AC_2SS; |
| 793 | else if (tx_num == 3) |
| 794 | rate_id = RTW_RATEID_ARFR4_AC_3SS; |
| 795 | else if (tx_num == 4) |
| 796 | rate_id = RTW_RATEID_ARFR6_AC_4SS; |
| 797 | } else { |
| 798 | if (tx_num == 1) |
| 799 | rate_id = RTW_RATEID_ARFR2_AC_2G_1SS; |
| 800 | else if (tx_num == 2) |
| 801 | rate_id = RTW_RATEID_ARFR3_AC_2G_2SS; |
| 802 | else if (tx_num == 3) |
| 803 | rate_id = RTW_RATEID_ARFR4_AC_3SS; |
| 804 | else if (tx_num == 4) |
| 805 | rate_id = RTW_RATEID_ARFR6_AC_4SS; |
| 806 | } |
| 807 | break; |
| 808 | default: |
| 809 | break; |
| 810 | } |
| 811 | |
| 812 | return rate_id; |
| 813 | } |
| 814 | |
| 815 | #define RA_MASK_CCK_RATES 0x0000f |
| 816 | #define RA_MASK_OFDM_RATES 0x00ff0 |
| 817 | #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0) |
| 818 | #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8) |
| 819 | #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16) |
| 820 | #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \ |
| 821 | RA_MASK_HT_RATES_2SS | \ |
| 822 | RA_MASK_HT_RATES_3SS) |
| 823 | #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0) |
| 824 | #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10) |
| 825 | #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20) |
| 826 | #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \ |
| 827 | RA_MASK_VHT_RATES_2SS | \ |
| 828 | RA_MASK_VHT_RATES_3SS) |
| 829 | #define RA_MASK_CCK_IN_HT 0x00005 |
| 830 | #define RA_MASK_CCK_IN_VHT 0x00005 |
| 831 | #define RA_MASK_OFDM_IN_VHT 0x00010 |
| 832 | #define RA_MASK_OFDM_IN_HT_2G 0x00010 |
| 833 | #define RA_MASK_OFDM_IN_HT_5G 0x00030 |
| 834 | |
| 835 | static u64 rtw_update_rate_mask(struct rtw_dev *rtwdev, |
| 836 | struct rtw_sta_info *si, |
| 837 | u64 ra_mask, bool is_vht_enable, |
| 838 | u8 wireless_set) |
| 839 | { |
| 840 | struct rtw_hal *hal = &rtwdev->hal; |
| 841 | const struct cfg80211_bitrate_mask *mask = si->mask; |
| 842 | u64 cfg_mask = GENMASK_ULL(63, 0); |
| 843 | u8 rssi_level, band; |
| 844 | |
| 845 | if (wireless_set != WIRELESS_CCK) { |
| 846 | rssi_level = si->rssi_level; |
| 847 | if (rssi_level == 0) |
| 848 | ra_mask &= 0xffffffffffffffffULL; |
| 849 | else if (rssi_level == 1) |
| 850 | ra_mask &= 0xfffffffffffffff0ULL; |
| 851 | else if (rssi_level == 2) |
| 852 | ra_mask &= 0xffffffffffffefe0ULL; |
| 853 | else if (rssi_level == 3) |
| 854 | ra_mask &= 0xffffffffffffcfc0ULL; |
| 855 | else if (rssi_level == 4) |
| 856 | ra_mask &= 0xffffffffffff8f80ULL; |
| 857 | else if (rssi_level >= 5) |
| 858 | ra_mask &= 0xffffffffffff0f00ULL; |
| 859 | } |
| 860 | |
| 861 | if (!si->use_cfg_mask) |
| 862 | return ra_mask; |
| 863 | |
| 864 | band = hal->current_band_type; |
| 865 | if (band == RTW_BAND_2G) { |
| 866 | band = NL80211_BAND_2GHZ; |
| 867 | cfg_mask = mask->control[band].legacy; |
| 868 | } else if (band == RTW_BAND_5G) { |
| 869 | band = NL80211_BAND_5GHZ; |
| 870 | cfg_mask = u64_encode_bits(mask->control[band].legacy, |
| 871 | RA_MASK_OFDM_RATES); |
| 872 | } |
| 873 | |
| 874 | if (!is_vht_enable) { |
| 875 | if (ra_mask & RA_MASK_HT_RATES_1SS) |
| 876 | cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], |
| 877 | RA_MASK_HT_RATES_1SS); |
| 878 | if (ra_mask & RA_MASK_HT_RATES_2SS) |
| 879 | cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], |
| 880 | RA_MASK_HT_RATES_2SS); |
| 881 | } else { |
| 882 | if (ra_mask & RA_MASK_VHT_RATES_1SS) |
| 883 | cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], |
| 884 | RA_MASK_VHT_RATES_1SS); |
| 885 | if (ra_mask & RA_MASK_VHT_RATES_2SS) |
| 886 | cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], |
| 887 | RA_MASK_VHT_RATES_2SS); |
| 888 | } |
| 889 | |
| 890 | ra_mask &= cfg_mask; |
| 891 | |
| 892 | return ra_mask; |
| 893 | } |
| 894 | |
| 895 | void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si) |
| 896 | { |
| 897 | struct rtw_dm_info *dm_info = &rtwdev->dm_info; |
| 898 | struct ieee80211_sta *sta = si->sta; |
| 899 | struct rtw_efuse *efuse = &rtwdev->efuse; |
| 900 | struct rtw_hal *hal = &rtwdev->hal; |
| 901 | u8 wireless_set; |
| 902 | u8 bw_mode; |
| 903 | u8 rate_id; |
| 904 | u8 rf_type = RF_1T1R; |
| 905 | u8 stbc_en = 0; |
| 906 | u8 ldpc_en = 0; |
| 907 | u8 tx_num = 1; |
| 908 | u64 ra_mask = 0; |
| 909 | bool is_vht_enable = false; |
| 910 | bool is_support_sgi = false; |
| 911 | |
| 912 | if (sta->vht_cap.vht_supported) { |
| 913 | is_vht_enable = true; |
| 914 | ra_mask |= get_vht_ra_mask(sta); |
| 915 | if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) |
| 916 | stbc_en = VHT_STBC_EN; |
| 917 | if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) |
| 918 | ldpc_en = VHT_LDPC_EN; |
| 919 | } else if (sta->ht_cap.ht_supported) { |
| 920 | ra_mask |= (sta->ht_cap.mcs.rx_mask[1] << 20) | |
| 921 | (sta->ht_cap.mcs.rx_mask[0] << 12); |
| 922 | if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) |
| 923 | stbc_en = HT_STBC_EN; |
| 924 | if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) |
| 925 | ldpc_en = HT_LDPC_EN; |
| 926 | } |
| 927 | |
| 928 | if (efuse->hw_cap.nss == 1) |
| 929 | ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; |
| 930 | |
| 931 | if (hal->current_band_type == RTW_BAND_5G) { |
| 932 | ra_mask |= (u64)sta->supp_rates[NL80211_BAND_5GHZ] << 4; |
| 933 | if (sta->vht_cap.vht_supported) { |
| 934 | ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; |
| 935 | wireless_set = WIRELESS_OFDM | WIRELESS_VHT; |
| 936 | } else if (sta->ht_cap.ht_supported) { |
| 937 | ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G; |
| 938 | wireless_set = WIRELESS_OFDM | WIRELESS_HT; |
| 939 | } else { |
| 940 | wireless_set = WIRELESS_OFDM; |
| 941 | } |
| 942 | dm_info->rrsr_val_init = RRSR_INIT_5G; |
| 943 | } else if (hal->current_band_type == RTW_BAND_2G) { |
| 944 | ra_mask |= sta->supp_rates[NL80211_BAND_2GHZ]; |
| 945 | if (sta->vht_cap.vht_supported) { |
| 946 | ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT | |
| 947 | RA_MASK_OFDM_IN_VHT; |
| 948 | wireless_set = WIRELESS_CCK | WIRELESS_OFDM | |
| 949 | WIRELESS_HT | WIRELESS_VHT; |
| 950 | } else if (sta->ht_cap.ht_supported) { |
| 951 | ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT | |
| 952 | RA_MASK_OFDM_IN_HT_2G; |
| 953 | wireless_set = WIRELESS_CCK | WIRELESS_OFDM | |
| 954 | WIRELESS_HT; |
| 955 | } else if (sta->supp_rates[0] <= 0xf) { |
| 956 | wireless_set = WIRELESS_CCK; |
| 957 | } else { |
| 958 | wireless_set = WIRELESS_CCK | WIRELESS_OFDM; |
| 959 | } |
| 960 | dm_info->rrsr_val_init = RRSR_INIT_2G; |
| 961 | } else { |
| 962 | rtw_err(rtwdev, "Unknown band type\n"); |
| 963 | wireless_set = 0; |
| 964 | } |
| 965 | |
| 966 | switch (sta->bandwidth) { |
| 967 | case IEEE80211_STA_RX_BW_80: |
| 968 | bw_mode = RTW_CHANNEL_WIDTH_80; |
| 969 | is_support_sgi = sta->vht_cap.vht_supported && |
| 970 | (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); |
| 971 | break; |
| 972 | case IEEE80211_STA_RX_BW_40: |
| 973 | bw_mode = RTW_CHANNEL_WIDTH_40; |
| 974 | is_support_sgi = sta->ht_cap.ht_supported && |
| 975 | (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40); |
| 976 | break; |
| 977 | default: |
| 978 | bw_mode = RTW_CHANNEL_WIDTH_20; |
| 979 | is_support_sgi = sta->ht_cap.ht_supported && |
| 980 | (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20); |
| 981 | break; |
| 982 | } |
| 983 | |
| 984 | if (sta->vht_cap.vht_supported && ra_mask & 0xffc00000) { |
| 985 | tx_num = 2; |
| 986 | rf_type = RF_2T2R; |
| 987 | } else if (sta->ht_cap.ht_supported && ra_mask & 0xfff00000) { |
| 988 | tx_num = 2; |
| 989 | rf_type = RF_2T2R; |
| 990 | } |
| 991 | |
| 992 | rate_id = get_rate_id(wireless_set, bw_mode, tx_num); |
| 993 | |
| 994 | ra_mask = rtw_update_rate_mask(rtwdev, si, ra_mask, is_vht_enable, |
| 995 | wireless_set); |
| 996 | |
| 997 | si->bw_mode = bw_mode; |
| 998 | si->stbc_en = stbc_en; |
| 999 | si->ldpc_en = ldpc_en; |
| 1000 | si->rf_type = rf_type; |
| 1001 | si->wireless_set = wireless_set; |
| 1002 | si->sgi_enable = is_support_sgi; |
| 1003 | si->vht_enable = is_vht_enable; |
| 1004 | si->ra_mask = ra_mask; |
| 1005 | si->rate_id = rate_id; |
| 1006 | |
| 1007 | rtw_fw_send_ra_info(rtwdev, si); |
| 1008 | } |
| 1009 | |
| 1010 | static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev) |
| 1011 | { |
| 1012 | struct rtw_chip_info *chip = rtwdev->chip; |
| 1013 | struct rtw_fw_state *fw; |
| 1014 | |
| 1015 | fw = &rtwdev->fw; |
| 1016 | wait_for_completion(&fw->completion); |
| 1017 | if (!fw->firmware) |
| 1018 | return -EINVAL; |
| 1019 | |
| 1020 | if (chip->wow_fw_name) { |
| 1021 | fw = &rtwdev->wow_fw; |
| 1022 | wait_for_completion(&fw->completion); |
| 1023 | if (!fw->firmware) |
| 1024 | return -EINVAL; |
| 1025 | } |
| 1026 | |
| 1027 | return 0; |
| 1028 | } |
| 1029 | |
| 1030 | static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev, |
| 1031 | struct rtw_fw_state *fw) |
| 1032 | { |
| 1033 | struct rtw_chip_info *chip = rtwdev->chip; |
| 1034 | |
| 1035 | if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported || |
| 1036 | !fw->feature) |
| 1037 | return LPS_DEEP_MODE_NONE; |
| 1038 | |
| 1039 | if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) && |
| 1040 | (fw->feature & FW_FEATURE_PG)) |
| 1041 | return LPS_DEEP_MODE_PG; |
| 1042 | |
| 1043 | if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) && |
| 1044 | (fw->feature & FW_FEATURE_LCLK)) |
| 1045 | return LPS_DEEP_MODE_LCLK; |
| 1046 | |
| 1047 | return LPS_DEEP_MODE_NONE; |
| 1048 | } |
| 1049 | |
| 1050 | static int rtw_power_on(struct rtw_dev *rtwdev) |
| 1051 | { |
| 1052 | struct rtw_chip_info *chip = rtwdev->chip; |
| 1053 | struct rtw_fw_state *fw = &rtwdev->fw; |
| 1054 | bool wifi_only; |
| 1055 | int ret; |
| 1056 | |
| 1057 | ret = rtw_hci_setup(rtwdev); |
| 1058 | if (ret) { |
| 1059 | rtw_err(rtwdev, "failed to setup hci\n"); |
| 1060 | goto err; |
| 1061 | } |
| 1062 | |
| 1063 | /* power on MAC before firmware downloaded */ |
| 1064 | ret = rtw_mac_power_on(rtwdev); |
| 1065 | if (ret) { |
| 1066 | rtw_err(rtwdev, "failed to power on mac\n"); |
| 1067 | goto err; |
| 1068 | } |
| 1069 | |
| 1070 | ret = rtw_wait_firmware_completion(rtwdev); |
| 1071 | if (ret) { |
| 1072 | rtw_err(rtwdev, "failed to wait firmware completion\n"); |
| 1073 | goto err_off; |
| 1074 | } |
| 1075 | |
| 1076 | ret = rtw_download_firmware(rtwdev, fw); |
| 1077 | if (ret) { |
| 1078 | rtw_err(rtwdev, "failed to download firmware\n"); |
| 1079 | goto err_off; |
| 1080 | } |
| 1081 | |
| 1082 | /* config mac after firmware downloaded */ |
| 1083 | ret = rtw_mac_init(rtwdev); |
| 1084 | if (ret) { |
| 1085 | rtw_err(rtwdev, "failed to configure mac\n"); |
| 1086 | goto err_off; |
| 1087 | } |
| 1088 | |
| 1089 | chip->ops->phy_set_param(rtwdev); |
| 1090 | |
| 1091 | ret = rtw_hci_start(rtwdev); |
| 1092 | if (ret) { |
| 1093 | rtw_err(rtwdev, "failed to start hci\n"); |
| 1094 | goto err_off; |
| 1095 | } |
| 1096 | |
| 1097 | /* send H2C after HCI has started */ |
| 1098 | rtw_fw_send_general_info(rtwdev); |
| 1099 | rtw_fw_send_phydm_info(rtwdev); |
| 1100 | |
| 1101 | wifi_only = !rtwdev->efuse.btcoex; |
| 1102 | rtw_coex_power_on_setting(rtwdev); |
| 1103 | rtw_coex_init_hw_config(rtwdev, wifi_only); |
| 1104 | |
| 1105 | return 0; |
| 1106 | |
| 1107 | err_off: |
| 1108 | rtw_mac_power_off(rtwdev); |
| 1109 | |
| 1110 | err: |
| 1111 | return ret; |
| 1112 | } |
| 1113 | |
| 1114 | int rtw_core_start(struct rtw_dev *rtwdev) |
| 1115 | { |
| 1116 | int ret; |
| 1117 | |
| 1118 | ret = rtw_power_on(rtwdev); |
| 1119 | if (ret) |
| 1120 | return ret; |
| 1121 | |
| 1122 | rtw_sec_enable_sec_engine(rtwdev); |
| 1123 | |
| 1124 | rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw); |
| 1125 | rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw); |
| 1126 | |
| 1127 | /* rcr reset after powered on */ |
| 1128 | rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr); |
| 1129 | |
| 1130 | ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, |
| 1131 | RTW_WATCH_DOG_DELAY_TIME); |
| 1132 | |
| 1133 | set_bit(RTW_FLAG_RUNNING, rtwdev->flags); |
| 1134 | |
| 1135 | return 0; |
| 1136 | } |
| 1137 | |
| 1138 | static void rtw_power_off(struct rtw_dev *rtwdev) |
| 1139 | { |
| 1140 | rtw_hci_stop(rtwdev); |
| 1141 | rtw_coex_power_off_setting(rtwdev); |
| 1142 | rtw_mac_power_off(rtwdev); |
| 1143 | } |
| 1144 | |
| 1145 | void rtw_core_stop(struct rtw_dev *rtwdev) |
| 1146 | { |
| 1147 | struct rtw_coex *coex = &rtwdev->coex; |
| 1148 | |
| 1149 | clear_bit(RTW_FLAG_RUNNING, rtwdev->flags); |
| 1150 | clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); |
| 1151 | |
| 1152 | mutex_unlock(&rtwdev->mutex); |
| 1153 | |
| 1154 | cancel_work_sync(&rtwdev->c2h_work); |
| 1155 | cancel_delayed_work_sync(&rtwdev->watch_dog_work); |
| 1156 | cancel_delayed_work_sync(&coex->bt_relink_work); |
| 1157 | cancel_delayed_work_sync(&coex->bt_reenable_work); |
| 1158 | cancel_delayed_work_sync(&coex->defreeze_work); |
| 1159 | cancel_delayed_work_sync(&coex->wl_remain_work); |
| 1160 | cancel_delayed_work_sync(&coex->bt_remain_work); |
| 1161 | cancel_delayed_work_sync(&coex->wl_connecting_work); |
| 1162 | cancel_delayed_work_sync(&coex->bt_multi_link_remain_work); |
| 1163 | cancel_delayed_work_sync(&coex->wl_ccklock_work); |
| 1164 | |
| 1165 | mutex_lock(&rtwdev->mutex); |
| 1166 | |
| 1167 | rtw_power_off(rtwdev); |
| 1168 | } |
| 1169 | |
| 1170 | static void rtw_init_ht_cap(struct rtw_dev *rtwdev, |
| 1171 | struct ieee80211_sta_ht_cap *ht_cap) |
| 1172 | { |
| 1173 | struct rtw_efuse *efuse = &rtwdev->efuse; |
| 1174 | |
| 1175 | ht_cap->ht_supported = true; |
| 1176 | ht_cap->cap = 0; |
| 1177 | ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | |
| 1178 | IEEE80211_HT_CAP_MAX_AMSDU | |
| 1179 | (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); |
| 1180 | |
| 1181 | if (rtw_chip_has_rx_ldpc(rtwdev)) |
| 1182 | ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; |
| 1183 | |
| 1184 | if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) |
| 1185 | ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | |
| 1186 | IEEE80211_HT_CAP_DSSSCCK40 | |
| 1187 | IEEE80211_HT_CAP_SGI_40; |
| 1188 | ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; |
| 1189 | ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; |
| 1190 | ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; |
| 1191 | if (efuse->hw_cap.nss > 1) { |
| 1192 | ht_cap->mcs.rx_mask[0] = 0xFF; |
| 1193 | ht_cap->mcs.rx_mask[1] = 0xFF; |
| 1194 | ht_cap->mcs.rx_mask[4] = 0x01; |
| 1195 | ht_cap->mcs.rx_highest = cpu_to_le16(300); |
| 1196 | } else { |
| 1197 | ht_cap->mcs.rx_mask[0] = 0xFF; |
| 1198 | ht_cap->mcs.rx_mask[1] = 0x00; |
| 1199 | ht_cap->mcs.rx_mask[4] = 0x01; |
| 1200 | ht_cap->mcs.rx_highest = cpu_to_le16(150); |
| 1201 | } |
| 1202 | } |
| 1203 | |
| 1204 | static void rtw_init_vht_cap(struct rtw_dev *rtwdev, |
| 1205 | struct ieee80211_sta_vht_cap *vht_cap) |
| 1206 | { |
| 1207 | struct rtw_efuse *efuse = &rtwdev->efuse; |
| 1208 | u16 mcs_map; |
| 1209 | __le16 highest; |
| 1210 | |
| 1211 | if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && |
| 1212 | efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT) |
| 1213 | return; |
| 1214 | |
| 1215 | vht_cap->vht_supported = true; |
| 1216 | vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | |
| 1217 | IEEE80211_VHT_CAP_SHORT_GI_80 | |
| 1218 | IEEE80211_VHT_CAP_RXSTBC_1 | |
| 1219 | IEEE80211_VHT_CAP_HTC_VHT | |
| 1220 | IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | |
| 1221 | 0; |
| 1222 | if (rtwdev->hal.rf_path_num > 1) |
| 1223 | vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; |
| 1224 | vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | |
| 1225 | IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; |
| 1226 | vht_cap->cap |= (rtwdev->hal.bfee_sts_cap << |
| 1227 | IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); |
| 1228 | |
| 1229 | if (rtw_chip_has_rx_ldpc(rtwdev)) |
| 1230 | vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; |
| 1231 | |
| 1232 | mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | |
| 1233 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | |
| 1234 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | |
| 1235 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | |
| 1236 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | |
| 1237 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | |
| 1238 | IEEE80211_VHT_MCS_NOT_SUPPORTED << 14; |
| 1239 | if (efuse->hw_cap.nss > 1) { |
| 1240 | highest = cpu_to_le16(780); |
| 1241 | mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2; |
| 1242 | } else { |
| 1243 | highest = cpu_to_le16(390); |
| 1244 | mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2; |
| 1245 | } |
| 1246 | |
| 1247 | vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); |
| 1248 | vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); |
| 1249 | vht_cap->vht_mcs.rx_highest = highest; |
| 1250 | vht_cap->vht_mcs.tx_highest = highest; |
| 1251 | } |
| 1252 | |
| 1253 | static void rtw_set_supported_band(struct ieee80211_hw *hw, |
| 1254 | struct rtw_chip_info *chip) |
| 1255 | { |
| 1256 | struct rtw_dev *rtwdev = hw->priv; |
| 1257 | struct ieee80211_supported_band *sband; |
| 1258 | |
| 1259 | if (chip->band & RTW_BAND_2G) { |
| 1260 | sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL); |
| 1261 | if (!sband) |
| 1262 | goto err_out; |
| 1263 | if (chip->ht_supported) |
| 1264 | rtw_init_ht_cap(rtwdev, &sband->ht_cap); |
| 1265 | hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; |
| 1266 | } |
| 1267 | |
| 1268 | if (chip->band & RTW_BAND_5G) { |
| 1269 | sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL); |
| 1270 | if (!sband) |
| 1271 | goto err_out; |
| 1272 | if (chip->ht_supported) |
| 1273 | rtw_init_ht_cap(rtwdev, &sband->ht_cap); |
| 1274 | if (chip->vht_supported) |
| 1275 | rtw_init_vht_cap(rtwdev, &sband->vht_cap); |
| 1276 | hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; |
| 1277 | } |
| 1278 | |
| 1279 | return; |
| 1280 | |
| 1281 | err_out: |
| 1282 | rtw_err(rtwdev, "failed to set supported band\n"); |
| 1283 | } |
| 1284 | |
| 1285 | static void rtw_unset_supported_band(struct ieee80211_hw *hw, |
| 1286 | struct rtw_chip_info *chip) |
| 1287 | { |
| 1288 | kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); |
| 1289 | kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); |
| 1290 | } |
| 1291 | |
| 1292 | static void __update_firmware_feature(struct rtw_dev *rtwdev, |
| 1293 | struct rtw_fw_state *fw) |
| 1294 | { |
| 1295 | u32 feature; |
| 1296 | const struct rtw_fw_hdr *fw_hdr = |
| 1297 | (const struct rtw_fw_hdr *)fw->firmware->data; |
| 1298 | |
| 1299 | feature = le32_to_cpu(fw_hdr->feature); |
| 1300 | fw->feature = feature & FW_FEATURE_SIG ? feature : 0; |
| 1301 | } |
| 1302 | |
| 1303 | static void __update_firmware_info(struct rtw_dev *rtwdev, |
| 1304 | struct rtw_fw_state *fw) |
| 1305 | { |
| 1306 | const struct rtw_fw_hdr *fw_hdr = |
| 1307 | (const struct rtw_fw_hdr *)fw->firmware->data; |
| 1308 | |
| 1309 | fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver); |
| 1310 | fw->version = le16_to_cpu(fw_hdr->version); |
| 1311 | fw->sub_version = fw_hdr->subversion; |
| 1312 | fw->sub_index = fw_hdr->subindex; |
| 1313 | |
| 1314 | __update_firmware_feature(rtwdev, fw); |
| 1315 | } |
| 1316 | |
| 1317 | static void __update_firmware_info_legacy(struct rtw_dev *rtwdev, |
| 1318 | struct rtw_fw_state *fw) |
| 1319 | { |
| 1320 | struct rtw_fw_hdr_legacy *legacy = |
| 1321 | (struct rtw_fw_hdr_legacy *)fw->firmware->data; |
| 1322 | |
| 1323 | fw->h2c_version = 0; |
| 1324 | fw->version = le16_to_cpu(legacy->version); |
| 1325 | fw->sub_version = legacy->subversion1; |
| 1326 | fw->sub_index = legacy->subversion2; |
| 1327 | } |
| 1328 | |
| 1329 | static void update_firmware_info(struct rtw_dev *rtwdev, |
| 1330 | struct rtw_fw_state *fw) |
| 1331 | { |
| 1332 | if (rtw_chip_wcpu_11n(rtwdev)) |
| 1333 | __update_firmware_info_legacy(rtwdev, fw); |
| 1334 | else |
| 1335 | __update_firmware_info(rtwdev, fw); |
| 1336 | } |
| 1337 | |
| 1338 | static void rtw_load_firmware_cb(const struct firmware *firmware, void *context) |
| 1339 | { |
| 1340 | struct rtw_fw_state *fw = context; |
| 1341 | struct rtw_dev *rtwdev = fw->rtwdev; |
| 1342 | |
| 1343 | if (!firmware || !firmware->data) { |
| 1344 | rtw_err(rtwdev, "failed to request firmware\n"); |
| 1345 | complete_all(&fw->completion); |
| 1346 | return; |
| 1347 | } |
| 1348 | |
| 1349 | fw->firmware = firmware; |
| 1350 | update_firmware_info(rtwdev, fw); |
| 1351 | complete_all(&fw->completion); |
| 1352 | |
| 1353 | rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n", |
| 1354 | fw->version, fw->sub_version, fw->sub_index, fw->h2c_version); |
| 1355 | } |
| 1356 | |
| 1357 | static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type) |
| 1358 | { |
| 1359 | const char *fw_name; |
| 1360 | struct rtw_fw_state *fw; |
| 1361 | int ret; |
| 1362 | |
| 1363 | switch (type) { |
| 1364 | case RTW_WOWLAN_FW: |
| 1365 | fw = &rtwdev->wow_fw; |
| 1366 | fw_name = rtwdev->chip->wow_fw_name; |
| 1367 | break; |
| 1368 | |
| 1369 | case RTW_NORMAL_FW: |
| 1370 | fw = &rtwdev->fw; |
| 1371 | fw_name = rtwdev->chip->fw_name; |
| 1372 | break; |
| 1373 | |
| 1374 | default: |
| 1375 | rtw_warn(rtwdev, "unsupported firmware type\n"); |
| 1376 | return -ENOENT; |
| 1377 | } |
| 1378 | |
| 1379 | fw->rtwdev = rtwdev; |
| 1380 | init_completion(&fw->completion); |
| 1381 | |
| 1382 | ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, |
| 1383 | GFP_KERNEL, fw, rtw_load_firmware_cb); |
| 1384 | if (ret) { |
| 1385 | rtw_err(rtwdev, "failed to async firmware request\n"); |
| 1386 | return ret; |
| 1387 | } |
| 1388 | |
| 1389 | return 0; |
| 1390 | } |
| 1391 | |
| 1392 | static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev) |
| 1393 | { |
| 1394 | struct rtw_chip_info *chip = rtwdev->chip; |
| 1395 | struct rtw_hal *hal = &rtwdev->hal; |
| 1396 | struct rtw_efuse *efuse = &rtwdev->efuse; |
| 1397 | int ret = 0; |
| 1398 | |
| 1399 | switch (rtw_hci_type(rtwdev)) { |
| 1400 | case RTW_HCI_TYPE_PCIE: |
| 1401 | rtwdev->hci.rpwm_addr = 0x03d9; |
| 1402 | rtwdev->hci.cpwm_addr = 0x03da; |
| 1403 | break; |
| 1404 | default: |
| 1405 | rtw_err(rtwdev, "unsupported hci type\n"); |
| 1406 | return -EINVAL; |
| 1407 | } |
| 1408 | |
| 1409 | hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1); |
| 1410 | hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version); |
| 1411 | hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1; |
| 1412 | if (hal->chip_version & BIT_RF_TYPE_ID) { |
| 1413 | hal->rf_type = RF_2T2R; |
| 1414 | hal->rf_path_num = 2; |
| 1415 | hal->antenna_tx = BB_PATH_AB; |
| 1416 | hal->antenna_rx = BB_PATH_AB; |
| 1417 | } else { |
| 1418 | hal->rf_type = RF_1T1R; |
| 1419 | hal->rf_path_num = 1; |
| 1420 | hal->antenna_tx = BB_PATH_A; |
| 1421 | hal->antenna_rx = BB_PATH_A; |
| 1422 | } |
| 1423 | hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num : |
| 1424 | hal->rf_path_num; |
| 1425 | |
| 1426 | efuse->physical_size = chip->phy_efuse_size; |
| 1427 | efuse->logical_size = chip->log_efuse_size; |
| 1428 | efuse->protect_size = chip->ptct_efuse_size; |
| 1429 | |
| 1430 | /* default use ack */ |
| 1431 | rtwdev->hal.rcr |= BIT_VHT_DACK; |
| 1432 | |
| 1433 | hal->bfee_sts_cap = 3; |
| 1434 | |
| 1435 | return ret; |
| 1436 | } |
| 1437 | |
| 1438 | static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev) |
| 1439 | { |
| 1440 | struct rtw_fw_state *fw = &rtwdev->fw; |
| 1441 | int ret; |
| 1442 | |
| 1443 | ret = rtw_hci_setup(rtwdev); |
| 1444 | if (ret) { |
| 1445 | rtw_err(rtwdev, "failed to setup hci\n"); |
| 1446 | goto err; |
| 1447 | } |
| 1448 | |
| 1449 | ret = rtw_mac_power_on(rtwdev); |
| 1450 | if (ret) { |
| 1451 | rtw_err(rtwdev, "failed to power on mac\n"); |
| 1452 | goto err; |
| 1453 | } |
| 1454 | |
| 1455 | rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP); |
| 1456 | |
| 1457 | wait_for_completion(&fw->completion); |
| 1458 | if (!fw->firmware) { |
| 1459 | ret = -EINVAL; |
| 1460 | rtw_err(rtwdev, "failed to load firmware\n"); |
| 1461 | goto err; |
| 1462 | } |
| 1463 | |
| 1464 | ret = rtw_download_firmware(rtwdev, fw); |
| 1465 | if (ret) { |
| 1466 | rtw_err(rtwdev, "failed to download firmware\n"); |
| 1467 | goto err_off; |
| 1468 | } |
| 1469 | |
| 1470 | return 0; |
| 1471 | |
| 1472 | err_off: |
| 1473 | rtw_mac_power_off(rtwdev); |
| 1474 | |
| 1475 | err: |
| 1476 | return ret; |
| 1477 | } |
| 1478 | |
| 1479 | static int rtw_dump_hw_feature(struct rtw_dev *rtwdev) |
| 1480 | { |
| 1481 | struct rtw_efuse *efuse = &rtwdev->efuse; |
| 1482 | u8 hw_feature[HW_FEATURE_LEN]; |
| 1483 | u8 id; |
| 1484 | u8 bw; |
| 1485 | int i; |
| 1486 | |
| 1487 | id = rtw_read8(rtwdev, REG_C2HEVT); |
| 1488 | if (id != C2H_HW_FEATURE_REPORT) { |
| 1489 | rtw_err(rtwdev, "failed to read hw feature report\n"); |
| 1490 | return -EBUSY; |
| 1491 | } |
| 1492 | |
| 1493 | for (i = 0; i < HW_FEATURE_LEN; i++) |
| 1494 | hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i); |
| 1495 | |
| 1496 | rtw_write8(rtwdev, REG_C2HEVT, 0); |
| 1497 | |
| 1498 | bw = GET_EFUSE_HW_CAP_BW(hw_feature); |
| 1499 | efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw); |
| 1500 | efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature); |
| 1501 | efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature); |
| 1502 | efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature); |
| 1503 | efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature); |
| 1504 | |
| 1505 | rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num); |
| 1506 | |
| 1507 | if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE || |
| 1508 | efuse->hw_cap.nss > rtwdev->hal.rf_path_num) |
| 1509 | efuse->hw_cap.nss = rtwdev->hal.rf_path_num; |
| 1510 | |
| 1511 | rtw_dbg(rtwdev, RTW_DBG_EFUSE, |
| 1512 | "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", |
| 1513 | efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, |
| 1514 | efuse->hw_cap.ant_num, efuse->hw_cap.nss); |
| 1515 | |
| 1516 | return 0; |
| 1517 | } |
| 1518 | |
| 1519 | static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev) |
| 1520 | { |
| 1521 | rtw_hci_stop(rtwdev); |
| 1522 | rtw_mac_power_off(rtwdev); |
| 1523 | } |
| 1524 | |
| 1525 | static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) |
| 1526 | { |
| 1527 | struct rtw_efuse *efuse = &rtwdev->efuse; |
| 1528 | int ret; |
| 1529 | |
| 1530 | mutex_lock(&rtwdev->mutex); |
| 1531 | |
| 1532 | /* power on mac to read efuse */ |
| 1533 | ret = rtw_chip_efuse_enable(rtwdev); |
| 1534 | if (ret) |
| 1535 | goto out_unlock; |
| 1536 | |
| 1537 | ret = rtw_parse_efuse_map(rtwdev); |
| 1538 | if (ret) |
| 1539 | goto out_disable; |
| 1540 | |
| 1541 | ret = rtw_dump_hw_feature(rtwdev); |
| 1542 | if (ret) |
| 1543 | goto out_disable; |
| 1544 | |
| 1545 | ret = rtw_check_supported_rfe(rtwdev); |
| 1546 | if (ret) |
| 1547 | goto out_disable; |
| 1548 | |
| 1549 | if (efuse->crystal_cap == 0xff) |
| 1550 | efuse->crystal_cap = 0; |
| 1551 | if (efuse->pa_type_2g == 0xff) |
| 1552 | efuse->pa_type_2g = 0; |
| 1553 | if (efuse->pa_type_5g == 0xff) |
| 1554 | efuse->pa_type_5g = 0; |
| 1555 | if (efuse->lna_type_2g == 0xff) |
| 1556 | efuse->lna_type_2g = 0; |
| 1557 | if (efuse->lna_type_5g == 0xff) |
| 1558 | efuse->lna_type_5g = 0; |
| 1559 | if (efuse->channel_plan == 0xff) |
| 1560 | efuse->channel_plan = 0x7f; |
| 1561 | if (efuse->rf_board_option == 0xff) |
| 1562 | efuse->rf_board_option = 0; |
| 1563 | if (efuse->bt_setting & BIT(0)) |
| 1564 | efuse->share_ant = true; |
| 1565 | if (efuse->regd == 0xff) |
| 1566 | efuse->regd = 0; |
| 1567 | if (efuse->tx_bb_swing_setting_2g == 0xff) |
| 1568 | efuse->tx_bb_swing_setting_2g = 0; |
| 1569 | if (efuse->tx_bb_swing_setting_5g == 0xff) |
| 1570 | efuse->tx_bb_swing_setting_5g = 0; |
| 1571 | |
| 1572 | efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20; |
| 1573 | efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; |
| 1574 | efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; |
| 1575 | efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; |
| 1576 | efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0; |
| 1577 | |
| 1578 | out_disable: |
| 1579 | rtw_chip_efuse_disable(rtwdev); |
| 1580 | |
| 1581 | out_unlock: |
| 1582 | mutex_unlock(&rtwdev->mutex); |
| 1583 | return ret; |
| 1584 | } |
| 1585 | |
| 1586 | static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) |
| 1587 | { |
| 1588 | struct rtw_hal *hal = &rtwdev->hal; |
| 1589 | const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); |
| 1590 | |
| 1591 | if (!rfe_def) |
| 1592 | return -ENODEV; |
| 1593 | |
| 1594 | rtw_phy_setup_phy_cond(rtwdev, 0); |
| 1595 | |
| 1596 | rtw_phy_init_tx_power(rtwdev); |
| 1597 | if (rfe_def->agc_btg_tbl) |
| 1598 | rtw_load_table(rtwdev, rfe_def->agc_btg_tbl); |
| 1599 | rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); |
| 1600 | rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); |
| 1601 | rtw_phy_tx_power_by_rate_config(hal); |
| 1602 | rtw_phy_tx_power_limit_config(hal); |
| 1603 | |
| 1604 | return 0; |
| 1605 | } |
| 1606 | |
| 1607 | int rtw_chip_info_setup(struct rtw_dev *rtwdev) |
| 1608 | { |
| 1609 | int ret; |
| 1610 | |
| 1611 | ret = rtw_chip_parameter_setup(rtwdev); |
| 1612 | if (ret) { |
| 1613 | rtw_err(rtwdev, "failed to setup chip parameters\n"); |
| 1614 | goto err_out; |
| 1615 | } |
| 1616 | |
| 1617 | ret = rtw_chip_efuse_info_setup(rtwdev); |
| 1618 | if (ret) { |
| 1619 | rtw_err(rtwdev, "failed to setup chip efuse info\n"); |
| 1620 | goto err_out; |
| 1621 | } |
| 1622 | |
| 1623 | ret = rtw_chip_board_info_setup(rtwdev); |
| 1624 | if (ret) { |
| 1625 | rtw_err(rtwdev, "failed to setup chip board info\n"); |
| 1626 | goto err_out; |
| 1627 | } |
| 1628 | |
| 1629 | return 0; |
| 1630 | |
| 1631 | err_out: |
| 1632 | return ret; |
| 1633 | } |
| 1634 | EXPORT_SYMBOL(rtw_chip_info_setup); |
| 1635 | |
| 1636 | static void rtw_stats_init(struct rtw_dev *rtwdev) |
| 1637 | { |
| 1638 | struct rtw_traffic_stats *stats = &rtwdev->stats; |
| 1639 | struct rtw_dm_info *dm_info = &rtwdev->dm_info; |
| 1640 | int i; |
| 1641 | |
| 1642 | ewma_tp_init(&stats->tx_ewma_tp); |
| 1643 | ewma_tp_init(&stats->rx_ewma_tp); |
| 1644 | |
| 1645 | for (i = 0; i < RTW_EVM_NUM; i++) |
| 1646 | ewma_evm_init(&dm_info->ewma_evm[i]); |
| 1647 | for (i = 0; i < RTW_SNR_NUM; i++) |
| 1648 | ewma_snr_init(&dm_info->ewma_snr[i]); |
| 1649 | } |
| 1650 | |
| 1651 | int rtw_core_init(struct rtw_dev *rtwdev) |
| 1652 | { |
| 1653 | struct rtw_chip_info *chip = rtwdev->chip; |
| 1654 | struct rtw_coex *coex = &rtwdev->coex; |
| 1655 | int ret; |
| 1656 | |
| 1657 | INIT_LIST_HEAD(&rtwdev->rsvd_page_list); |
| 1658 | INIT_LIST_HEAD(&rtwdev->txqs); |
| 1659 | |
| 1660 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0) |
| 1661 | setup_timer(&rtwdev->tx_report.purge_timer, |
| 1662 | (void *)(long unsigned int)rtw_tx_report_purge_timer, |
| 1663 | (long unsigned int)rtwdev); |
| 1664 | #else |
| 1665 | timer_setup(&rtwdev->tx_report.purge_timer, |
| 1666 | rtw_tx_report_purge_timer, 0); |
| 1667 | #endif |
| 1668 | rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); |
| 1669 | |
| 1670 | INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work); |
| 1671 | INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work); |
| 1672 | INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work); |
| 1673 | INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work); |
| 1674 | INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work); |
| 1675 | INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work); |
| 1676 | INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work); |
| 1677 | INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work, |
| 1678 | rtw_coex_bt_multi_link_remain_work); |
| 1679 | INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work); |
| 1680 | INIT_WORK(&rtwdev->tx_work, rtw_tx_work); |
| 1681 | INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work); |
| 1682 | INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work); |
| 1683 | INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work); |
| 1684 | skb_queue_head_init(&rtwdev->c2h_queue); |
| 1685 | skb_queue_head_init(&rtwdev->coex.queue); |
| 1686 | skb_queue_head_init(&rtwdev->tx_report.queue); |
| 1687 | |
| 1688 | spin_lock_init(&rtwdev->rf_lock); |
| 1689 | spin_lock_init(&rtwdev->h2c.lock); |
| 1690 | spin_lock_init(&rtwdev->txq_lock); |
| 1691 | spin_lock_init(&rtwdev->tx_report.q_lock); |
| 1692 | |
| 1693 | mutex_init(&rtwdev->mutex); |
| 1694 | mutex_init(&rtwdev->coex.mutex); |
| 1695 | mutex_init(&rtwdev->hal.tx_power_mutex); |
| 1696 | |
| 1697 | init_waitqueue_head(&rtwdev->coex.wait); |
| 1698 | init_completion(&rtwdev->lps_leave_check); |
| 1699 | |
| 1700 | rtwdev->sec.total_cam_num = 32; |
| 1701 | rtwdev->hal.current_channel = 1; |
| 1702 | set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map); |
| 1703 | |
| 1704 | rtw_stats_init(rtwdev); |
| 1705 | |
| 1706 | /* default rx filter setting */ |
| 1707 | rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV | |
| 1708 | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS | |
| 1709 | BIT_AB | BIT_AM | BIT_APM; |
| 1710 | |
| 1711 | ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW); |
| 1712 | if (ret) { |
| 1713 | rtw_warn(rtwdev, "no firmware loaded\n"); |
| 1714 | return ret; |
| 1715 | } |
| 1716 | |
| 1717 | if (chip->wow_fw_name) { |
| 1718 | ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW); |
| 1719 | if (ret) { |
| 1720 | rtw_warn(rtwdev, "no wow firmware loaded\n"); |
| 1721 | wait_for_completion(&rtwdev->fw.completion); |
| 1722 | if (rtwdev->fw.firmware) |
| 1723 | release_firmware(rtwdev->fw.firmware); |
| 1724 | return ret; |
| 1725 | } |
| 1726 | } |
| 1727 | |
| 1728 | return 0; |
| 1729 | } |
| 1730 | EXPORT_SYMBOL(rtw_core_init); |
| 1731 | |
| 1732 | void rtw_core_deinit(struct rtw_dev *rtwdev) |
| 1733 | { |
| 1734 | struct rtw_fw_state *fw = &rtwdev->fw; |
| 1735 | struct rtw_fw_state *wow_fw = &rtwdev->wow_fw; |
| 1736 | struct rtw_rsvd_page *rsvd_pkt, *tmp; |
| 1737 | unsigned long flags; |
| 1738 | |
| 1739 | rtw_wait_firmware_completion(rtwdev); |
| 1740 | |
| 1741 | if (fw->firmware) |
| 1742 | release_firmware(fw->firmware); |
| 1743 | |
| 1744 | if (wow_fw->firmware) |
| 1745 | release_firmware(wow_fw->firmware); |
| 1746 | |
| 1747 | destroy_workqueue(rtwdev->tx_wq); |
| 1748 | spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags); |
| 1749 | skb_queue_purge(&rtwdev->tx_report.queue); |
| 1750 | spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags); |
| 1751 | |
| 1752 | list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, |
| 1753 | build_list) { |
| 1754 | list_del(&rsvd_pkt->build_list); |
| 1755 | kfree(rsvd_pkt); |
| 1756 | } |
| 1757 | |
| 1758 | mutex_destroy(&rtwdev->mutex); |
| 1759 | mutex_destroy(&rtwdev->coex.mutex); |
| 1760 | mutex_destroy(&rtwdev->hal.tx_power_mutex); |
| 1761 | } |
| 1762 | EXPORT_SYMBOL(rtw_core_deinit); |
| 1763 | |
| 1764 | int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) |
| 1765 | { |
| 1766 | struct rtw_hal *hal = &rtwdev->hal; |
| 1767 | int max_tx_headroom = 0; |
| 1768 | int ret; |
| 1769 | |
| 1770 | /* TODO: USB & SDIO may need extra room? */ |
| 1771 | max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz; |
| 1772 | |
| 1773 | hw->extra_tx_headroom = max_tx_headroom; |
| 1774 | hw->queues = IEEE80211_NUM_ACS; |
| 1775 | hw->txq_data_size = sizeof(struct rtw_txq); |
| 1776 | hw->sta_data_size = sizeof(struct rtw_sta_info); |
| 1777 | hw->vif_data_size = sizeof(struct rtw_vif); |
| 1778 | |
| 1779 | ieee80211_hw_set(hw, SIGNAL_DBM); |
| 1780 | ieee80211_hw_set(hw, RX_INCLUDES_FCS); |
| 1781 | ieee80211_hw_set(hw, AMPDU_AGGREGATION); |
| 1782 | ieee80211_hw_set(hw, MFP_CAPABLE); |
| 1783 | ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); |
| 1784 | ieee80211_hw_set(hw, SUPPORTS_PS); |
| 1785 | ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); |
| 1786 | ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); |
| 1787 | ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); |
| 1788 | ieee80211_hw_set(hw, HAS_RATE_CONTROL); |
| 1789 | ieee80211_hw_set(hw, TX_AMSDU); |
| 1790 | |
| 1791 | hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | |
| 1792 | BIT(NL80211_IFTYPE_AP) | |
| 1793 | BIT(NL80211_IFTYPE_ADHOC) | |
| 1794 | BIT(NL80211_IFTYPE_MESH_POINT); |
| 1795 | hw->wiphy->available_antennas_tx = hal->antenna_tx; |
| 1796 | hw->wiphy->available_antennas_rx = hal->antenna_rx; |
| 1797 | |
| 1798 | hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | |
| 1799 | WIPHY_FLAG_TDLS_EXTERNAL_SETUP; |
| 1800 | |
| 1801 | hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; |
| 1802 | |
| 1803 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0) |
| 1804 | wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); |
| 1805 | #endif |
| 1806 | |
| 1807 | #ifdef CONFIG_PM |
| 1808 | hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; |
| 1809 | hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids; |
| 1810 | #endif |
| 1811 | rtw_set_supported_band(hw, rtwdev->chip); |
| 1812 | SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr); |
| 1813 | |
| 1814 | rtw_regd_init(rtwdev, rtw_regd_notifier); |
| 1815 | |
| 1816 | ret = ieee80211_register_hw(hw); |
| 1817 | if (ret) { |
| 1818 | rtw_err(rtwdev, "failed to register hw\n"); |
| 1819 | return ret; |
| 1820 | } |
| 1821 | |
| 1822 | if (regulatory_hint(hw->wiphy, rtwdev->regd.alpha2)) |
| 1823 | rtw_err(rtwdev, "regulatory_hint fail\n"); |
| 1824 | |
| 1825 | rtw_debugfs_init(rtwdev); |
| 1826 | |
| 1827 | rtwdev->bf_info.bfer_mu_cnt = 0; |
| 1828 | rtwdev->bf_info.bfer_su_cnt = 0; |
| 1829 | |
| 1830 | return 0; |
| 1831 | } |
| 1832 | EXPORT_SYMBOL(rtw_register_hw); |
| 1833 | |
| 1834 | void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) |
| 1835 | { |
| 1836 | struct rtw_chip_info *chip = rtwdev->chip; |
| 1837 | |
| 1838 | ieee80211_unregister_hw(hw); |
| 1839 | rtw_unset_supported_band(hw, chip); |
| 1840 | } |
| 1841 | EXPORT_SYMBOL(rtw_unregister_hw); |
| 1842 | |
| 1843 | MODULE_AUTHOR("Realtek Corporation"); |
| 1844 | MODULE_DESCRIPTION("Realtek 802.11ac wireless core module"); |
| 1845 | MODULE_LICENSE("Dual BSD/GPL"); |