Duncan P. N. Exon Smith | 15f92a3 | 2014-07-29 01:10:57 +0000 | [diff] [blame] | 1 | ; RUN: llvm-dis < %s.bc| FileCheck %s |
Duncan P. N. Exon Smith | 13f5c58 | 2014-08-19 21:08:27 +0000 | [diff] [blame] | 2 | ; RUN: verify-uselistorder < %s.bc |
Duncan P. N. Exon Smith | 15f92a3 | 2014-07-29 01:10:57 +0000 | [diff] [blame] | 3 | |
| 4 | ; BinaryIntOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2. |
| 5 | ; The test checks that LLVM does not misread binary integer instructions from |
| 6 | ; older bitcode files. |
| 7 | |
| 8 | define void @add(i1 %x1, i8 %x2 ,i16 %x3, i32 %x4, i64 %x5){ |
| 9 | entry: |
| 10 | ; CHECK: %res1 = add i1 %x1, %x1 |
| 11 | %res1 = add i1 %x1, %x1 |
| 12 | |
| 13 | ; CHECK-NEXT: %res2 = add i8 %x2, %x2 |
| 14 | %res2 = add i8 %x2, %x2 |
| 15 | |
| 16 | ; CHECK-NEXT: %res3 = add i16 %x3, %x3 |
| 17 | %res3 = add i16 %x3, %x3 |
| 18 | |
| 19 | ; CHECK-NEXT: %res4 = add i32 %x4, %x4 |
| 20 | %res4 = add i32 %x4, %x4 |
| 21 | |
| 22 | ; CHECK-NEXT: %res5 = add i64 %x5, %x5 |
| 23 | %res5 = add i64 %x5, %x5 |
| 24 | |
| 25 | ; CHECK: %res6 = add nuw i1 %x1, %x1 |
| 26 | %res6 = add nuw i1 %x1, %x1 |
| 27 | |
| 28 | ; CHECK: %res7 = add nsw i1 %x1, %x1 |
| 29 | %res7 = add nsw i1 %x1, %x1 |
| 30 | |
| 31 | ; CHECK: %res8 = add nuw nsw i1 %x1, %x1 |
| 32 | %res8 = add nuw nsw i1 %x1, %x1 |
| 33 | |
| 34 | ret void |
| 35 | } |
| 36 | |
| 37 | define void @addvec8NuwNsw(<2 x i8> %x1, <3 x i8> %x2 ,<4 x i8> %x3, <8 x i8> %x4, <16 x i8> %x5){ |
| 38 | entry: |
| 39 | ; CHECK: %res1 = add nuw nsw <2 x i8> %x1, %x1 |
| 40 | %res1 = add nuw nsw <2 x i8> %x1, %x1 |
| 41 | |
| 42 | ; CHECK-NEXT: %res2 = add nuw nsw <3 x i8> %x2, %x2 |
| 43 | %res2 = add nuw nsw <3 x i8> %x2, %x2 |
| 44 | |
| 45 | ; CHECK-NEXT: %res3 = add nuw nsw <4 x i8> %x3, %x3 |
| 46 | %res3 = add nuw nsw <4 x i8> %x3, %x3 |
| 47 | |
| 48 | ; CHECK-NEXT: %res4 = add nuw nsw <8 x i8> %x4, %x4 |
| 49 | %res4 = add nuw nsw <8 x i8> %x4, %x4 |
| 50 | |
| 51 | ; CHECK-NEXT: %res5 = add nuw nsw <16 x i8> %x5, %x5 |
| 52 | %res5 = add nuw nsw <16 x i8> %x5, %x5 |
| 53 | |
| 54 | ret void |
| 55 | } |
| 56 | |
| 57 | define void @addvec16NuwNsw(<2 x i16> %x1, <3 x i16> %x2 ,<4 x i16> %x3, <8 x i16> %x4, <16 x i16> %x5){ |
| 58 | entry: |
| 59 | ; CHECK: %res1 = add nuw nsw <2 x i16> %x1, %x1 |
| 60 | %res1 = add nuw nsw <2 x i16> %x1, %x1 |
| 61 | |
| 62 | ; CHECK-NEXT: %res2 = add nuw nsw <3 x i16> %x2, %x2 |
| 63 | %res2 = add nuw nsw <3 x i16> %x2, %x2 |
| 64 | |
| 65 | ; CHECK-NEXT: %res3 = add nuw nsw <4 x i16> %x3, %x3 |
| 66 | %res3 = add nuw nsw <4 x i16> %x3, %x3 |
| 67 | |
| 68 | ; CHECK-NEXT: %res4 = add nuw nsw <8 x i16> %x4, %x4 |
| 69 | %res4 = add nuw nsw <8 x i16> %x4, %x4 |
| 70 | |
| 71 | ; CHECK-NEXT: %res5 = add nuw nsw <16 x i16> %x5, %x5 |
| 72 | %res5 = add nuw nsw <16 x i16> %x5, %x5 |
| 73 | |
| 74 | ret void |
| 75 | } |
| 76 | |
| 77 | define void @addvec32NuwNsw(<2 x i32> %x1, <3 x i32> %x2 ,<4 x i32> %x3, <8 x i32> %x4, <16 x i32> %x5){ |
| 78 | entry: |
| 79 | ; CHECK: %res1 = add nuw nsw <2 x i32> %x1, %x1 |
| 80 | %res1 = add nuw nsw <2 x i32> %x1, %x1 |
| 81 | |
| 82 | ; CHECK-NEXT: %res2 = add nuw nsw <3 x i32> %x2, %x2 |
| 83 | %res2 = add nuw nsw <3 x i32> %x2, %x2 |
| 84 | |
| 85 | ; CHECK-NEXT: %res3 = add nuw nsw <4 x i32> %x3, %x3 |
| 86 | %res3 = add nuw nsw <4 x i32> %x3, %x3 |
| 87 | |
| 88 | ; CHECK-NEXT: %res4 = add nuw nsw <8 x i32> %x4, %x4 |
| 89 | %res4 = add nuw nsw <8 x i32> %x4, %x4 |
| 90 | |
| 91 | ; CHECK-NEXT: %res5 = add nuw nsw <16 x i32> %x5, %x5 |
| 92 | %res5 = add nuw nsw <16 x i32> %x5, %x5 |
| 93 | |
| 94 | ret void |
| 95 | } |
| 96 | |
| 97 | define void @addvec64NuwNsw(<2 x i64> %x1, <3 x i64> %x2 ,<4 x i64> %x3, <8 x i64> %x4, <16 x i64> %x5){ |
| 98 | entry: |
| 99 | ; CHECK: %res1 = add nuw nsw <2 x i64> %x1, %x1 |
| 100 | %res1 = add nuw nsw <2 x i64> %x1, %x1 |
| 101 | |
| 102 | ; CHECK-NEXT: %res2 = add nuw nsw <3 x i64> %x2, %x2 |
| 103 | %res2 = add nuw nsw <3 x i64> %x2, %x2 |
| 104 | |
| 105 | ; CHECK-NEXT: %res3 = add nuw nsw <4 x i64> %x3, %x3 |
| 106 | %res3 = add nuw nsw <4 x i64> %x3, %x3 |
| 107 | |
| 108 | ; CHECK-NEXT: %res4 = add nuw nsw <8 x i64> %x4, %x4 |
| 109 | %res4 = add nuw nsw <8 x i64> %x4, %x4 |
| 110 | |
| 111 | ; CHECK-NEXT: %res5 = add nuw nsw <16 x i64> %x5, %x5 |
| 112 | %res5 = add nuw nsw <16 x i64> %x5, %x5 |
| 113 | |
| 114 | ret void |
| 115 | } |
| 116 | |
| 117 | define void @sub(i8 %x1){ |
| 118 | entry: |
| 119 | ; CHECK: %res1 = sub i8 %x1, %x1 |
| 120 | %res1 = sub i8 %x1, %x1 |
| 121 | |
| 122 | ; CHECK: %res2 = sub nuw i8 %x1, %x1 |
| 123 | %res2 = sub nuw i8 %x1, %x1 |
| 124 | |
| 125 | ; CHECK: %res3 = sub nsw i8 %x1, %x1 |
| 126 | %res3 = sub nsw i8 %x1, %x1 |
| 127 | |
| 128 | ; CHECK: %res4 = sub nuw nsw i8 %x1, %x1 |
| 129 | %res4 = sub nuw nsw i8 %x1, %x1 |
| 130 | |
| 131 | ret void |
| 132 | } |
| 133 | |
| 134 | define void @mul(i8 %x1){ |
| 135 | entry: |
| 136 | ; CHECK: %res1 = mul i8 %x1, %x1 |
| 137 | %res1 = mul i8 %x1, %x1 |
| 138 | |
| 139 | ret void |
| 140 | } |
| 141 | |
| 142 | define void @udiv(i8 %x1){ |
| 143 | entry: |
| 144 | ; CHECK: %res1 = udiv i8 %x1, %x1 |
| 145 | %res1 = udiv i8 %x1, %x1 |
| 146 | |
| 147 | ; CHECK-NEXT: %res2 = udiv exact i8 %x1, %x1 |
| 148 | %res2 = udiv exact i8 %x1, %x1 |
| 149 | |
| 150 | ret void |
| 151 | } |
| 152 | |
| 153 | define void @sdiv(i8 %x1){ |
| 154 | entry: |
| 155 | ; CHECK: %res1 = sdiv i8 %x1, %x1 |
| 156 | %res1 = sdiv i8 %x1, %x1 |
| 157 | |
| 158 | ; CHECK-NEXT: %res2 = sdiv exact i8 %x1, %x1 |
| 159 | %res2 = sdiv exact i8 %x1, %x1 |
| 160 | |
| 161 | ret void |
| 162 | } |
| 163 | |
| 164 | define void @urem(i32 %x1){ |
| 165 | entry: |
| 166 | ; CHECK: %res1 = urem i32 %x1, %x1 |
| 167 | %res1 = urem i32 %x1, %x1 |
| 168 | |
| 169 | ret void |
| 170 | } |
| 171 | |
| 172 | define void @srem(i32 %x1){ |
| 173 | entry: |
| 174 | ; CHECK: %res1 = srem i32 %x1, %x1 |
| 175 | %res1 = srem i32 %x1, %x1 |
| 176 | |
| 177 | ret void |
| 178 | } |