blob: 5214e409a28dea158f9abb811a8a16ec060437eb [file] [log] [blame]
codeworkx62f02ba2012-05-20 12:00:36 +02001/*
2 * Copyright (C) 2010 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17/*
18 * Revision History:
19 * - 2011/03/11 : Rama, Meka(v.meka@samsung.com)
20 * Initial version
21 *
22 * - 2011/12/07 : Jeonghee, Kim(jhhhh.kim@samsung.com)
23 * Add V4L2_PIX_FMT_YUV420M V4L2_PIX_FMT_NV12M
24 *
25 */
26
27#include "SecHWCUtils.h"
28
29#ifdef BOARD_USE_V4L2_ION
30#define V4L2_BUF_TYPE_OUTPUT V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
31#define V4L2_BUF_TYPE_CAPTURE V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
32#else
33#define V4L2_BUF_TYPE_OUTPUT V4L2_BUF_TYPE_VIDEO_OUTPUT
34#define V4L2_BUF_TYPE_CAPTURE V4L2_BUF_TYPE_VIDEO_CAPTURE
35#endif
36
37#define EXYNOS4_ALIGN( value, base ) (((value) + ((base) - 1)) & ~((base) - 1))
38
39//#define CHECK_FPS
40#ifdef CHECK_FPS
41#include <sys/time.h>
42#include <unistd.h>
43#define CHK_FRAME_CNT 30
44
45void check_fps()
46{
47 static struct timeval tick, tick_old;
48 static int total = 0;
49 static int cnt = 0;
50 int FPS;
51 cnt++;
52 gettimeofday(&tick, NULL);
53 if (cnt > 10) {
54 if (tick.tv_sec > tick_old.tv_sec)
55 total += ((tick.tv_usec/1000) + (tick.tv_sec - tick_old.tv_sec)*1000 - (tick_old.tv_usec/1000));
56 else
57 total += ((tick.tv_usec - tick_old.tv_usec)/1000);
58
59 memcpy(&tick_old, &tick, sizeof(timeval));
60 if (cnt == (10 + CHK_FRAME_CNT)) {
61 FPS = 1000*CHK_FRAME_CNT/total;
62 LOGE("[FPS]:%d\n", FPS);
63 total = 0;
64 cnt = 10;
65 }
66 } else {
67 memcpy(&tick_old, &tick, sizeof(timeval));
68 total = 0;
69 }
70}
71#endif
72
73struct yuv_fmt_list yuv_list[] = {
74 { "V4L2_PIX_FMT_NV12", "YUV420/2P/LSB_CBCR", V4L2_PIX_FMT_NV12, 12, 2 },
75 { "V4L2_PIX_FMT_NV12T", "YUV420/2P/LSB_CBCR", V4L2_PIX_FMT_NV12T, 12, 2 },
76 { "V4L2_PIX_FMT_NV21", "YUV420/2P/LSB_CRCB", V4L2_PIX_FMT_NV21, 12, 2 },
77 { "V4L2_PIX_FMT_NV21X", "YUV420/2P/MSB_CBCR", V4L2_PIX_FMT_NV21X, 12, 2 },
78 { "V4L2_PIX_FMT_NV12X", "YUV420/2P/MSB_CRCB", V4L2_PIX_FMT_NV12X, 12, 2 },
79 { "V4L2_PIX_FMT_YUV420", "YUV420/3P", V4L2_PIX_FMT_YUV420, 12, 3 },
80#ifdef BOARD_USE_V4L2_ION
81 { "V4L2_PIX_FMT_YUV420M", "YUV420/3P", V4L2_PIX_FMT_YUV420M, 12, 3 },
82 { "V4L2_PIX_FMT_NV12M", "YUV420/2P", V4L2_PIX_FMT_NV12M, 12, 2 },
83#endif
84 { "V4L2_PIX_FMT_YUYV", "YUV422/1P/YCBYCR", V4L2_PIX_FMT_YUYV, 16, 1 },
85 { "V4L2_PIX_FMT_YVYU", "YUV422/1P/YCRYCB", V4L2_PIX_FMT_YVYU, 16, 1 },
86 { "V4L2_PIX_FMT_UYVY", "YUV422/1P/CBYCRY", V4L2_PIX_FMT_UYVY, 16, 1 },
87 { "V4L2_PIX_FMT_VYUY", "YUV422/1P/CRYCBY", V4L2_PIX_FMT_VYUY, 16, 1 },
88 { "V4L2_PIX_FMT_UV12", "YUV422/2P/LSB_CBCR", V4L2_PIX_FMT_NV16, 16, 2 },
89 { "V4L2_PIX_FMT_UV21", "YUV422/2P/LSB_CRCB", V4L2_PIX_FMT_NV61, 16, 2 },
90 { "V4L2_PIX_FMT_UV12X", "YUV422/2P/MSB_CBCR", V4L2_PIX_FMT_NV16X, 16, 2 },
91 { "V4L2_PIX_FMT_UV21X", "YUV422/2P/MSB_CRCB", V4L2_PIX_FMT_NV61X, 16, 2 },
92 { "V4L2_PIX_FMT_YUV422P", "YUV422/3P", V4L2_PIX_FMT_YUV422P, 16, 3 },
93};
94
95int window_open(struct hwc_win_info_t *win, int id)
96{
97 int fd = 0;
98 char name[64];
99 int vsync = 1;
100 int real_id = id;
101
102 char const * const device_template = "/dev/graphics/fb%u";
103 // window & FB maping
104 // fb0 -> win-id : 2
105 // fb1 -> win-id : 3
106 // fb2 -> win-id : 4
107 // fb3 -> win-id : 0
108 // fb4 -> win_id : 1
109 // it is pre assumed that ...win0 or win1 is used here..
110
111 switch (id) {
112 case 0:
113#ifdef BOARD_USE_V4L2_ION
114 real_id = 2;
115#else
116 real_id = 3;
117#endif
118 break;
119 case 1:
120#ifdef BOARD_USE_V4L2_ION
121 real_id = 1;
122#else
123 real_id = 4;
124#endif
125 break;
126 default:
127 SEC_HWC_Log(HWC_LOG_ERROR, "%s::id(%d) is weird", __func__, id);
128 goto error;
129}
130
131// 0/10
132// snprintf(name, 64, device_template, id + 3);
133// 5/10
134// snprintf(name, 64, device_template, id + 0);
135// 0/10
136// snprintf(name, 64, device_template, id + 1);
137 snprintf(name, 64, device_template, real_id);
138
139 win->fd = open(name, O_RDWR);
140 if (win->fd <= 0) {
141 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Failed to open window device (%s) : %s",
142 __func__, strerror(errno), name);
143 goto error;
144 }
145
146#ifdef ENABLE_FIMD_VSYNC
147 if (ioctl(win->fd, S3CFB_SET_VSYNC_INT, &vsync) < 0) {
148 SEC_HWC_Log(HWC_LOG_ERROR, "%s::S3CFB_SET_VSYNC_INT fail", __func__);
149 goto error;
150 }
151#endif
152
153 return 0;
154
155error:
156 if (0 < win->fd)
157 close(win->fd);
158 win->fd = 0;
159
160 return -1;
161}
162
163int window_close(struct hwc_win_info_t *win)
164{
165 int ret = 0;
166
167 if (0 < win->fd) {
168
169#ifdef BOARD_USE_V4L2_ION
170 ion_unmap((void *)win->addr[0], ALIGN(win->size * NUM_OF_WIN_BUF, PAGE_SIZE));
171 ion_free(win->ion_fd);
172#endif
173
174#ifdef ENABLE_FIMD_VSYNC
175 int vsync = 0;
176 if (ioctl(win->fd, S3CFB_SET_VSYNC_INT, &vsync) < 0)
177 SEC_HWC_Log(HWC_LOG_ERROR, "%s::S3CFB_SET_VSYNC_INT fail", __func__);
178#endif
179 ret = close(win->fd);
180 }
181 win->fd = 0;
182
183 return ret;
184}
185
186int window_set_pos(struct hwc_win_info_t *win)
187{
188 struct s3cfb_user_window window;
189
190 //before changing the screen configuration...powerdown the window
191 if (window_hide(win) != 0)
192 return -1;
193
194 SEC_HWC_Log(HWC_LOG_DEBUG, "%s:: x(%d), y(%d)",
195 __func__, win->rect_info.x, win->rect_info.y);
196
197 win->var_info.xres_virtual = (win->lcd_info.xres + 15) & ~ 15;
198 win->var_info.yres_virtual = win->lcd_info.yres * NUM_OF_WIN_BUF;
199 win->var_info.xres = win->rect_info.w;
200 win->var_info.yres = win->rect_info.h;
201
202 win->var_info.activate &= ~FB_ACTIVATE_MASK;
203 win->var_info.activate |= FB_ACTIVATE_FORCE;
204
205 if (ioctl(win->fd, FBIOPUT_VSCREENINFO, &(win->var_info)) < 0) {
206 SEC_HWC_Log(HWC_LOG_ERROR, "%s::FBIOPUT_VSCREENINFO(%d, %d) fail",
207 __func__, win->rect_info.w, win->rect_info.h);
208 return -1;
209 }
210
211 window.x = win->rect_info.x;
212 window.y = win->rect_info.y;
213
214 if (ioctl(win->fd, S3CFB_WIN_POSITION, &window) < 0) {
215 SEC_HWC_Log(HWC_LOG_ERROR, "%s::S3CFB_WIN_POSITION(%d, %d) fail",
216 __func__, window.x, window.y);
217 return -1;
218 }
219
220 return 0;
221}
222
223int window_get_info(struct hwc_win_info_t *win, int win_num)
224{
225 int temp_size = 0;
226
227 if (ioctl(win->fd, FBIOGET_FSCREENINFO, &win->fix_info) < 0) {
228 SEC_HWC_Log(HWC_LOG_ERROR, "FBIOGET_FSCREENINFO failed : %s",
229 strerror(errno));
230 goto error;
231 }
232
233 win->size = win->fix_info.line_length * win->var_info.yres;
234
235#ifdef BOARD_USE_V4L2_ION
236 struct s3c_fb_user_ion_client ion_handle;
237 void *ion_start_addr;
238
239 if (ioctl(win->fd, S3CFB_GET_ION_USER_HANDLE, &ion_handle) < 0) {
240 SEC_HWC_Log(HWC_LOG_ERROR, "Get fb ion client is failed\n");
241 return -1;
242 }
243
244 win->ion_fd = ion_handle.fd;
245 ion_start_addr = ion_map(win->ion_fd, ALIGN(win->size * NUM_OF_WIN_BUF, PAGE_SIZE), 0);
246#endif
247
248 for (int j = 0; j < NUM_OF_WIN_BUF; j++) {
249 temp_size = win->size * j;
250#ifdef BOARD_USE_V4L2_ION
251 win->addr[j] = (uint32_t)ion_start_addr + temp_size;
252#else
253 win->addr[j] = win->fix_info.smem_start + temp_size;
254#endif
255 SEC_HWC_Log(HWC_LOG_DEBUG, "%s::win-%d add[%d] %x ",
256 __func__, win_num, j, win->addr[j]);
257 }
258 return 0;
259
260error:
261 win->fix_info.smem_start = 0;
262
263 return -1;
264}
265
266int window_pan_display(struct hwc_win_info_t *win)
267{
268 struct fb_var_screeninfo *lcd_info = &(win->lcd_info);
269
270#ifdef ENABLE_FIMD_VSYNC
271#ifdef BOARD_USE_V4L2_ION
272 int fimd_num = 0;
273 if (ioctl(win->fd, FBIO_WAITFORVSYNC, &fimd_num) < 0)
274 SEC_HWC_Log(HWC_LOG_ERROR, "%s::FBIO_WAITFORVSYNC fail(%s)",
275 __func__, strerror(errno));
276#else
277 if (ioctl(win->fd, FBIO_WAITFORVSYNC, 0) < 0)
278 SEC_HWC_Log(HWC_LOG_ERROR, "%s::FBIO_WAITFORVSYNC fail(%s)",
279 __func__, strerror(errno));
280#endif
281#endif
282
283 lcd_info->yoffset = lcd_info->yres * win->buf_index;
284
285 if (ioctl(win->fd, FBIOPAN_DISPLAY, lcd_info) < 0) {
286 SEC_HWC_Log(HWC_LOG_ERROR, "%s::FBIOPAN_DISPLAY(%d / %d / %d) fail(%s)",
287 __func__,
288 lcd_info->yres,
289 win->buf_index, lcd_info->yres_virtual,
290 strerror(errno));
291 return -1;
292 }
293 return 0;
294}
295
296int window_show(struct hwc_win_info_t *win)
297{
298 if (win->power_state == 0) {
299 if (ioctl(win->fd, FBIOBLANK, FB_BLANK_UNBLANK) < 0) {
300 SEC_HWC_Log(HWC_LOG_ERROR, "%s::FBIOBLANK failed : (%d:%s)",
301 __func__, win->fd, strerror(errno));
302 return -1;
303 }
304 win->power_state = 1;
305 }
306 return 0;
307}
308
309int window_hide(struct hwc_win_info_t *win)
310{
311 if (win->power_state == 1) {
312 if (ioctl(win->fd, FBIOBLANK, FB_BLANK_POWERDOWN) < 0) {
313 SEC_HWC_Log(HWC_LOG_ERROR, "%s::FBIOBLANK failed : (%d:%s)",
314 __func__, win->fd, strerror(errno));
315 return -1;
316 }
317 win->power_state = 0;
318 }
319 return 0;
320}
321
322int window_get_global_lcd_info(int fd, struct fb_var_screeninfo *lcd_info)
323{
324 if (ioctl(fd, FBIOGET_VSCREENINFO, lcd_info) < 0) {
325 SEC_HWC_Log(HWC_LOG_ERROR, "FBIOGET_VSCREENINFO failed : %s",
326 strerror(errno));
327 return -1;
328 }
329
330 SEC_HWC_Log(HWC_LOG_DEBUG, "%s:: Default LCD x(%d),y(%d)",
331 __func__, lcd_info->xres, lcd_info->yres);
332 return 0;
333}
334
335int fimc_v4l2_set_src(int fd, unsigned int hw_ver, s5p_fimc_img_info *src)
336{
337 struct v4l2_format fmt;
338 struct v4l2_cropcap cropcap;
339 struct v4l2_crop crop;
340 struct v4l2_requestbuffers req;
341
342#ifdef BOARD_USE_V4L2_ION
343 /* You MUST initialize structure for v4l2 */
344 memset(&fmt, 0, sizeof(fmt));
345 memset(&cropcap, 0, sizeof(cropcap));
346 memset(&crop, 0, sizeof(crop));
347 memset(&req, 0, sizeof(req));
348
349 /* To set size & format for source image (DMA-INPUT) */
350 fmt.fmt.pix_mp.num_planes = src->planes;
351 fmt.fmt.pix_mp.width = src->full_width;
352 fmt.fmt.pix_mp.height = src->full_height;
353 fmt.fmt.pix_mp.pixelformat = src->color_space;
354 fmt.fmt.pix_mp.field = V4L2_FIELD_ANY;
355#else
356 fmt.fmt.pix.width = src->full_width;
357 fmt.fmt.pix.height = src->full_height;
358 fmt.fmt.pix.pixelformat = src->color_space;
359 fmt.fmt.pix.field = V4L2_FIELD_NONE;
360#endif
361 fmt.type = V4L2_BUF_TYPE_OUTPUT;
362
363 if (ioctl(fd, VIDIOC_S_FMT, &fmt) < 0) {
364 SEC_HWC_Log(HWC_LOG_ERROR, "%s::VIDIOC_S_FMT failed : errno=%d (%s)"
365 " : fd=%d\n", __func__, errno, strerror(errno), fd);
366 return -1;
367 }
368
369 /* crop input size */
370 crop.type = V4L2_BUF_TYPE_OUTPUT;
371 crop.c.width = src->width;
372 crop.c.height = src->height;
373#ifdef BOARD_USE_V4L2_ION
374 crop.c.left = src->start_x;
375 crop.c.top = src->start_y;
376#else
377 if (0x50 <= hw_ver) {
378 crop.c.left = src->start_x;
379 crop.c.top = src->start_y;
380 } else {
381 crop.c.left = 0;
382 crop.c.top = 0;
383 }
384
385#endif
386
387 if (ioctl(fd, VIDIOC_S_CROP, &crop) < 0) {
388 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Error in video VIDIOC_S_CROP :"
389 "crop.c.left : (%d), crop.c.top : (%d), crop.c.width : (%d), crop.c.height : (%d)",
390 __func__, crop.c.left, crop.c.top, crop.c.width, crop.c.height);
391 return -1;
392 }
393
394 /* input buffer type */
395 req.count = 1;
396 req.memory = V4L2_MEMORY_USERPTR;
397 req.type = V4L2_BUF_TYPE_OUTPUT;
398
399 if (ioctl(fd, VIDIOC_REQBUFS, &req) < 0) {
400 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Error in VIDIOC_REQBUFS", __func__);
401 return -1;
402 }
403
404 return 0;
405}
406
407int fimc_v4l2_set_dst(int fd, s5p_fimc_img_info *dst,
408 int rotation, int hflip, int vflip, unsigned int addr)
409{
410 struct v4l2_format sFormat;
411 struct v4l2_control vc;
412 struct v4l2_framebuffer fbuf;
413#ifdef BOARD_USE_V4L2_ION
414 struct v4l2_crop crop;
415 struct v4l2_requestbuffers req;
416#endif
417 int ret;
418
419#ifdef BOARD_USE_V4L2_ION
420 /* You MUST initialize structure for v4l2 */
421 memset(&sFormat, 0, sizeof(sFormat));
422 memset(&vc, 0, sizeof(vc));
423 memset(&fbuf, 0, sizeof(fbuf));
424 memset(&crop, 0, sizeof(crop));
425 memset(&req, 0, sizeof(req));
426#endif
427
428 /* set rotation configuration */
429#ifdef BOARD_USE_V4L2_ION
430 vc.id = V4L2_CID_ROTATE;
431#else
432 vc.id = V4L2_CID_ROTATION;
433#endif
434 vc.value = rotation;
435
436 ret = ioctl(fd, VIDIOC_S_CTRL, &vc);
437 if (ret < 0) {
438 SEC_HWC_Log(HWC_LOG_ERROR,
439 "%s::Error in video VIDIOC_S_CTRL - rotation (%d)"
440 "vc.id : (%d), vc.value : (%d)", __func__, ret, vc.id, vc.value);
441 return -1;
442 }
443
444 vc.id = V4L2_CID_HFLIP;
445 vc.value = hflip;
446
447 ret = ioctl(fd, VIDIOC_S_CTRL, &vc);
448 if (ret < 0) {
449 SEC_HWC_Log(HWC_LOG_ERROR,
450 "%s::Error in video VIDIOC_S_CTRL - hflip (%d)"
451 "vc.id : (%d), vc.value : (%d)", __func__, ret, vc.id, vc.value);
452 return -1;
453 }
454
455 vc.id = V4L2_CID_VFLIP;
456 vc.value = vflip;
457
458 ret = ioctl(fd, VIDIOC_S_CTRL, &vc);
459 if (ret < 0) {
460 SEC_HWC_Log(HWC_LOG_ERROR,
461 "%s::Error in video VIDIOC_S_CTRL - vflip (%d)"
462 "vc.id : (%d), vc.value : (%d)", __func__, ret, vc.id, vc.value);
463 return -1;
464 }
465
466#ifdef BOARD_USE_V4L2_ION
467 /* set destination */
468 sFormat.type = V4L2_BUF_TYPE_CAPTURE;
469 sFormat.fmt.pix_mp.width = dst->full_width;
470 sFormat.fmt.pix_mp.height = dst->full_height;
471 sFormat.fmt.pix_mp.pixelformat = dst->color_space;
472 sFormat.fmt.pix_mp.num_planes = dst->planes;
473 sFormat.fmt.pix.field = V4L2_FIELD_ANY;
474
475 ret = ioctl(fd, VIDIOC_S_FMT, &sFormat);
476 if (ret < 0) {
477 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Error in video VIDIOC_S_FMT (%d)", __func__, ret);
478 return -1;
479 }
480
481 /* set destination window */
482 crop.type = V4L2_BUF_TYPE_CAPTURE;
483 crop.c.left = dst->start_x;
484 crop.c.top = dst->start_y;
485 crop.c.width = dst->width;
486 crop.c.height = dst->height;
487
488 ret = ioctl(fd, VIDIOC_S_CROP, &crop);
489 if (ret < 0) {
490 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Error in video VIDIOC_S_CROP (%d)", __func__, ret);
491 return -1;
492 }
493
494 /* input buffer type */
495 req.count = 1;
496 req.type = V4L2_BUF_TYPE_CAPTURE;
497 req.memory = V4L2_MEMORY_USERPTR;
498
499 ret = ioctl (fd, VIDIOC_REQBUFS, &req);
500 if (ret < 0) {
501 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Error in VIDIOC_REQBUFS (%d)", __func__, ret);
502 return -1;
503 }
504#else
505 /* set size, format & address for destination image (DMA-OUTPUT) */
506 ret = ioctl(fd, VIDIOC_G_FBUF, &fbuf);
507 if (ret < 0) {
508 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Error in video VIDIOC_G_FBUF (%d)", __func__, ret);
509 return -1;
510 }
511
512 fbuf.base = (void *)addr;
513 fbuf.fmt.width = dst->full_width;
514 fbuf.fmt.height = dst->full_height;
515 fbuf.fmt.pixelformat = dst->color_space;
516
517 ret = ioctl(fd, VIDIOC_S_FBUF, &fbuf);
518 if (ret < 0) {
519 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Error in video VIDIOC_S_FBUF (%d)", __func__, ret);
520 return -1;
521 }
522
523 /* set destination window */
524 sFormat.type = V4L2_BUF_TYPE_VIDEO_OVERLAY;
525 sFormat.fmt.win.w.left = dst->start_x;
526 sFormat.fmt.win.w.top = dst->start_y;
527 sFormat.fmt.win.w.width = dst->width;
528 sFormat.fmt.win.w.height = dst->height;
529
530 ret = ioctl(fd, VIDIOC_S_FMT, &sFormat);
531 if (ret < 0) {
532 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Error in video VIDIOC_S_FMT (%d)", __func__, ret);
533 return -1;
534 }
535#endif
536
537 return 0;
538}
539
540int fimc_v4l2_stream_on(int fd, enum v4l2_buf_type type)
541{
542 if (-1 == ioctl(fd, VIDIOC_STREAMON, &type)) {
543 SEC_HWC_Log(HWC_LOG_ERROR, "Error in VIDIOC_STREAMON\n");
544 return -1;
545 }
546
547 return 0;
548}
549
550int fimc_v4l2_queue(int fd, struct fimc_buf *fimc_buf, enum v4l2_buf_type type, int index)
551{
552#ifdef BOARD_USE_V4L2_ION
553 struct v4l2_plane plane[3];
554 int i;
555#endif
556 struct v4l2_buffer buf;
557 int ret;
558
559#ifdef BOARD_USE_V4L2_ION
560 buf.length = fimc_buf->planes;
561#else
562 buf.length = 0;
563 buf.m.userptr = (unsigned long)fimc_buf;
564#endif
565 buf.memory = V4L2_MEMORY_USERPTR;
566 buf.index = index;
567 buf.type = type;
568
569#ifdef BOARD_USE_V4L2_ION
570 if (buf.type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE ||
571 buf.type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
572 for (i = 0; i < buf.length; i++) {
573 plane[i].m.userptr = fimc_buf->base[i];
574 plane[i].length = fimc_buf->size[i];
575 }
576 }
577 buf.m.planes = plane;
578#endif
579
580 ret = ioctl(fd, VIDIOC_QBUF, &buf);
581 if (0 > ret) {
582 SEC_HWC_Log(HWC_LOG_ERROR, "Error in VIDIOC_QBUF : (%d)", ret);
583 return -1;
584 }
585
586 return 0;
587}
588
589int fimc_v4l2_dequeue(int fd, struct fimc_buf *fimc_buf, enum v4l2_buf_type type)
590{
591 struct v4l2_buffer buf;
592#ifdef BOARD_USE_V4L2_ION
593 struct v4l2_plane plane[3];
594#endif
595
596#ifdef BOARD_USE_V4L2_ION
597 buf.m.planes = plane;
598 buf.length = fimc_buf->planes;
599#endif
600 buf.memory = V4L2_MEMORY_USERPTR;
601 buf.type = type;
602
603 if (-1 == ioctl(fd, VIDIOC_DQBUF, &buf)) {
604 SEC_HWC_Log(HWC_LOG_ERROR, "Error in VIDIOC_DQBUF\n");
605 return -1;
606 }
607
608 return buf.index;
609}
610
611int fimc_v4l2_stream_off(int fd, enum v4l2_buf_type type)
612{
613 if (-1 == ioctl(fd, VIDIOC_STREAMOFF, &type)) {
614 SEC_HWC_Log(HWC_LOG_ERROR, "Error in VIDIOC_STREAMOFF\n");
615 return -1;
616 }
617
618 return 0;
619}
620
621int fimc_v4l2_clr_buf(int fd, enum v4l2_buf_type type)
622{
623 struct v4l2_requestbuffers req;
624
625 req.count = 0;
626 req.memory = V4L2_MEMORY_USERPTR;
627 req.type = type;
628
629 if (ioctl(fd, VIDIOC_REQBUFS, &req) == -1) {
630 SEC_HWC_Log(HWC_LOG_ERROR, "Error in VIDIOC_REQBUFS");
631 }
632
633 return 0;
634}
635
636int fimc_v4l2_S_ctrl(int fd)
637{
638 struct v4l2_control vc;
639
640 vc.id = V4L2_CID_CACHEABLE;
641 vc.value = 1;
642
643 if (ioctl(fd, VIDIOC_S_CTRL, &vc) < 0) {
644 SEC_HWC_Log(HWC_LOG_ERROR, "Error in VIDIOC_S_CTRL");
645 return -1;
646 }
647
648 return 0;
649}
650
651int fimc_handle_oneshot(int fd, struct fimc_buf *fimc_src_buf, struct fimc_buf *fimc_dst_buf)
652{
653#ifdef CHECK_FPS
654 check_fps();
655#endif
656
657#ifdef BOARD_USE_V4L2_ION
658 if (fimc_v4l2_queue(fd, fimc_src_buf, V4L2_BUF_TYPE_OUTPUT, 0) < 0) {
659 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : SRC v4l2_queue()");
660 return -1;
661 }
662
663 if (fimc_v4l2_queue(fd, fimc_dst_buf, V4L2_BUF_TYPE_CAPTURE, 0) < 0) {
664 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : DST v4l2_queue()");
665 return -2;
666 }
667
668 if (fimc_v4l2_stream_on(fd, V4L2_BUF_TYPE_OUTPUT) < 0) {
669 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : SRC v4l2_stream_on()");
670 return -3;
671 }
672
673 if (fimc_v4l2_stream_on(fd, V4L2_BUF_TYPE_CAPTURE) < 0) {
674 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : DST v4l2_stream_on()");
675 return -4;
676 }
677#else
678 if (fimc_v4l2_stream_on(fd, V4L2_BUF_TYPE_OUTPUT) < 0) {
679 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : SRC v4l2_stream_on()");
680 return -5;
681 }
682
683 if (fimc_v4l2_queue(fd, fimc_src_buf, V4L2_BUF_TYPE_OUTPUT, 0) < 0) {
684 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : SRC v4l2_queue()");
685 goto STREAM_OFF;
686 }
687#endif
688 if (fimc_v4l2_dequeue(fd, fimc_src_buf, V4L2_BUF_TYPE_OUTPUT) < 0) {
689 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : SRC v4l2_dequeue()");
690 return -6;
691 }
692#ifdef BOARD_USE_V4L2_ION
693 if (fimc_v4l2_dequeue(fd, fimc_dst_buf, V4L2_BUF_TYPE_CAPTURE) < 0) {
694 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : DST v4l2_dequeue()");
695 return -7;
696 }
697#endif
698STREAM_OFF:
699 if (fimc_v4l2_stream_off(fd, V4L2_BUF_TYPE_OUTPUT) < 0) {
700 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : SRC v4l2_stream_off()");
701 return -8;
702 }
703#ifdef BOARD_USE_V4L2_ION
704 if (fimc_v4l2_stream_off(fd, V4L2_BUF_TYPE_CAPTURE) < 0) {
705 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : DST v4l2_stream_off()");
706 return -9;
707 }
708#endif
709 if (fimc_v4l2_clr_buf(fd, V4L2_BUF_TYPE_OUTPUT) < 0) {
710 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : SRC v4l2_clr_buf()");
711 return -10;
712 }
713#ifdef BOARD_USE_V4L2_ION
714 if (fimc_v4l2_clr_buf(fd, V4L2_BUF_TYPE_CAPTURE)< 0) {
715 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : DST v4l2_clr_buf()");
716 return -11;
717 }
718#endif
719 return 0;
720}
721
722static int memcpy_rect(void *dst, void *src, int fullW, int fullH, int realW, int realH, int format)
723{
724 unsigned char *srcCb, *srcCr;
725 unsigned char *dstCb, *dstCr;
726 unsigned char *srcY, *dstY;
727 int srcCbOffset, srcCrOffset;
728 int dstCbOffset, dstFrameOffset, dstCrOffset;
729 int cbFullW, cbRealW, cbFullH, cbRealH;
730 int ySrcFW, ySrcFH, ySrcRW, ySrcRH;
731 int planes;
732 int i;
733
734 SEC_HWC_Log(HWC_LOG_DEBUG,
735 "++memcpy_rect()::"
736 "dst(0x%x),src(0x%x),f.w(%d),f.h(%d),r.w(%d),r.h(%d),format(0x%x)",
737 (unsigned int)dst, (unsigned int)src, fullW, fullH, realW, realH, format);
738
739// Set dst Y, Cb, Cr address for FIMC
740 {
741 cbFullW = fullW >> 1;
742 cbRealW = realW >> 1;
743 cbFullH = fullH >> 1;
744 cbRealH = realH >> 1;
745 dstFrameOffset = fullW * fullH;
746 dstCrOffset = cbFullW * cbFullH;
747 dstY = (unsigned char *)dst;
748 dstCb = (unsigned char *)dst + dstFrameOffset;
749 dstCr = (unsigned char *)dstCb + dstCrOffset;
750 }
751
752// Get src Y, Cb, Cr address for source buffer.
753// Each address is aligned by 16's multiple for GPU both width and height.
754 {
755 ySrcFW = fullW;
756 ySrcFH = fullH;
757 ySrcRW = realW;
758 ySrcRH = realH;
759 srcCbOffset = EXYNOS4_ALIGN(ySrcRW,16)* EXYNOS4_ALIGN(ySrcRH,16);
760 srcCrOffset = EXYNOS4_ALIGN(cbRealW,16)* EXYNOS4_ALIGN(cbRealH,16);
761 srcY = (unsigned char *)src;
762 srcCb = (unsigned char *)src + srcCbOffset;
763 srcCr = (unsigned char *)srcCb + srcCrOffset;
764 }
765 SEC_HWC_Log(HWC_LOG_DEBUG,
766 "--memcpy_rect()::\n"
767 "dstY(0x%x),dstCb(0x%x),dstCr(0x%x) \n"
768 "srcY(0x%x),srcCb(0x%x),srcCr(0x%x) \n"
769 "cbRealW(%d),cbRealH(%d)",
770 (unsigned int)dstY,(unsigned int)dstCb,(unsigned int)dstCr,
771 (unsigned int)srcY,(unsigned int)srcCb,(unsigned int)srcCr,
772 cbRealW, cbRealH);
773
774 if (format == HAL_PIXEL_FORMAT_YV12) { //YV12(Y,Cr,Cv)
775 planes = 3;
776//This is code for VE, deleted temporory by SSONG 2011.09.22
777// This will be enabled later.
778/*
779 //as defined in hardware.h, cb & cr full_width should be aligned to 16. ALIGN(y_stride/2, 16).
780 ////Alignment is hard coded to 16.
781 ////for example...check frameworks/media/libvideoeditor/lvpp/VideoEditorTools.cpp file for UV stride cal
782 cbSrcFW = (cbSrcFW + 15) & (~15);
783 srcCbOffset = ySrcFW * fullH;
784 srcCrOffset = srcCbOffset + ((cbSrcFW * fullH) >> 1);
785 srcY = (unsigned char *)src;
786 srcCb = (unsigned char *)src + srcCbOffset;
787 srcCr = (unsigned char *)src + srcCrOffset;
788*/
789 } else if ((format == HAL_PIXEL_FORMAT_YCbCr_420_P)) {
790 planes = 3;
791 } else if (format == HAL_PIXEL_FORMAT_YCbCr_420_SP || format == HAL_PIXEL_FORMAT_YCrCb_420_SP) {
792 planes = 2;
793 } else {
794 SEC_HWC_Log(HWC_LOG_ERROR, "use default memcpy instead of memcpy_rect");
795 return -1;
796 }
797//#define CHECK_PERF
798#ifdef CHECK_PERF
799 struct timeval start, end;
800 gettimeofday(&start, NULL);
801#endif
802 for (i = 0; i < realH; i++)
803 memcpy(dstY + fullW * i, srcY + ySrcFW * i, ySrcRW);
804 if (planes == 2) {
805 for (i = 0; i < cbRealH; i++)
806 memcpy(dstCb + ySrcFW * i, srcCb + ySrcFW * i, ySrcRW);
807 } else if (planes == 3) {
808 for (i = 0; i < cbRealH; i++)
809 memcpy(dstCb + cbFullW * i, srcCb + cbFullW * i, cbRealW);
810 for (i = 0; i < cbRealH; i++)
811 memcpy(dstCr + cbFullW * i, srcCr + cbFullW * i, cbRealW);
812 }
813#ifdef CHECK_PERF
814 gettimeofday(&end, NULL);
815 SEC_HWC_Log(HWC_LOG_ERROR, "[COPY]=%d,",(end.tv_sec - start.tv_sec)*1000+(end.tv_usec - start.tv_usec)/1000);
816#endif
817
818 return 0;
819}
820
821/*****************************************************************************/
822static int get_src_phys_addr(struct hwc_context_t *ctx,
823 sec_img *src_img, sec_rect *src_rect)
824{
825 s5p_fimc_t *fimc = &ctx->fimc;
826 struct s3c_mem_alloc *ptr_mem_alloc = &ctx->s3c_mem.mem_alloc[0];
827 struct s3c_mem_dma_param s3c_mem_dma;
828#ifdef USE_HW_PMEM
829 sec_pmem_alloc_t *pm_alloc = &ctx->sec_pmem.sec_pmem_alloc[0];
830#endif
831
832 unsigned int src_virt_addr = 0;
833 unsigned int src_phys_addr = 0;
834 unsigned int src_frame_size = 0;
835
836 struct pmem_region region;
837 ADDRS * addr;
838
839 // error check routine
840 if (0 == src_img->base && !(src_img->usage & GRALLOC_USAGE_HW_FIMC1)) {
841 SEC_HWC_Log(HWC_LOG_ERROR, "%s invalid src image base\n", __func__);
842 return 0;
843 }
844
845 switch (src_img->mem_type) {
846 case HWC_PHYS_MEM_TYPE:
847 src_phys_addr = src_img->base + src_img->offset;
848 break;
849
850 case HWC_VIRT_MEM_TYPE:
851 case HWC_UNKNOWN_MEM_TYPE:
852 switch (src_img->format) {
853 case HAL_PIXEL_FORMAT_CUSTOM_YCbCr_420_SP:
854 case HAL_PIXEL_FORMAT_CUSTOM_YCrCb_420_SP:
855 case HAL_PIXEL_FORMAT_CUSTOM_YCbCr_420_SP_TILED:
856 case HAL_PIXEL_FORMAT_CUSTOM_YCbCr_422_SP:
857 case HAL_PIXEL_FORMAT_CUSTOM_YCrCb_422_SP:
858 addr = (ADDRS *)(src_img->base);
859 fimc->params.src.buf_addr_phy_rgb_y = addr->addr_y;
860 fimc->params.src.buf_addr_phy_cb = addr->addr_cbcr;
861
862 src_phys_addr = fimc->params.src.buf_addr_phy_rgb_y;
863 if (0 == src_phys_addr) {
864 SEC_HWC_Log(HWC_LOG_ERROR, "%s address error "
865 "(format=CUSTOM_YCbCr/YCrCb_420_SP Y-addr=0x%x "
866 "CbCr-Addr=0x%x)",
867 __func__, fimc->params.src.buf_addr_phy_rgb_y,
868 fimc->params.src.buf_addr_phy_cb);
869 return 0;
870 }
871 break;
872 case HAL_PIXEL_FORMAT_CUSTOM_YCbCr_422_I:
873 case HAL_PIXEL_FORMAT_CUSTOM_YCrCb_422_I:
874 case HAL_PIXEL_FORMAT_CUSTOM_CbYCrY_422_I:
875 case HAL_PIXEL_FORMAT_CUSTOM_CrYCbY_422_I:
876 addr = (ADDRS *)(src_img->base + src_img->offset);
877 fimc->params.src.buf_addr_phy_rgb_y = addr->addr_y;
878 src_phys_addr = fimc->params.src.buf_addr_phy_rgb_y;
879 if (0 == src_phys_addr) {
880 SEC_HWC_Log(HWC_LOG_ERROR, "%s address error "
881 "(format=CUSTOM_YCbCr/CbYCrY_422_I Y-addr=0x%x)",
882 __func__, fimc->params.src.buf_addr_phy_rgb_y);
883 return 0;
884 }
885 break;
886 default:
887#ifdef BOARD_USE_V4L2_ION
888 fimc->params.src.buf_addr_phy_rgb_y = src_img->base;
889 fimc->params.src.buf_addr_phy_cb = src_img->base + src_img->uoffset;
890 fimc->params.src.buf_addr_phy_cr = src_img->base + src_img->uoffset + src_img->voffset;
891 src_phys_addr = fimc->params.src.buf_addr_phy_rgb_y;
892 break;
893#endif
894 if (src_img->usage & GRALLOC_USAGE_HW_FIMC1) {
895 fimc->params.src.buf_addr_phy_rgb_y = src_img->paddr;
896 fimc->params.src.buf_addr_phy_cb = src_img->paddr + src_img->uoffset;
897 fimc->params.src.buf_addr_phy_cr = src_img->paddr + src_img->uoffset + src_img->voffset;
898 src_phys_addr = fimc->params.src.buf_addr_phy_rgb_y;
899 break;
900 }
901 // copy
902 src_frame_size = FRAME_SIZE(src_img->format, src_img->w, src_img->h);
903 if (src_frame_size == 0) {
904 SEC_HWC_Log(HWC_LOG_ERROR, "%s::FRAME_SIZE fail", __func__);
905 return 0;
906 }
907
908#ifdef USE_HW_PMEM
909 if (0 <= checkPmem(&ctx->sec_pmem, 0, src_frame_size)) {
910 src_virt_addr = pm_alloc->virt_addr;
911 src_phys_addr = pm_alloc->phys_addr;
912 pm_alloc->size = src_frame_size;
913 } else
914#endif
915 if (0 <= checkMem(&ctx->s3c_mem, 0, src_frame_size)) {
916 src_virt_addr = ptr_mem_alloc->vir_addr;
917 src_phys_addr = ptr_mem_alloc->phy_addr;
918 ptr_mem_alloc->size = src_frame_size;
919 } else {
920 SEC_HWC_Log(HWC_LOG_ERROR, "%s::check_mem fail", __func__);
921 return 0;
922 }
923 if ((src_img->format == HAL_PIXEL_FORMAT_YCbCr_420_P) ||
924 (src_img->format == HAL_PIXEL_FORMAT_YV12) ||
925 (src_img->format == HAL_PIXEL_FORMAT_YCbCr_420_SP) ||
926 (src_img->format == HAL_PIXEL_FORMAT_YCrCb_420_SP)) {
927 if (memcpy_rect((void *)src_virt_addr, (void*)((unsigned int)src_img->base),
928 src_img->f_w, src_img->f_h, src_rect->w, src_rect->h, src_img->format) != 0)
929 return 0;
930 } else {
931 memcpy((void *)src_virt_addr, (void*)((unsigned int)src_img->base), src_frame_size);
932 }
933
934#ifdef USE_HW_PMEM
935 if (pm_alloc->size == src_frame_size) {
936 region.offset = 0;
937 region.len = src_frame_size;
938 if (ioctl(ctx->sec_pmem.pmem_master_fd, PMEM_CACHE_FLUSH, &region) < 0)
939 SEC_HWC_Log(HWC_LOG_ERROR, "%s::pmem cache flush fail ", __func__);
940 }
941#endif
942 break;
943 }
944 }
945
946 return src_phys_addr;
947}
948
949static int get_dst_phys_addr(struct hwc_context_t *ctx, sec_img *dst_img,
950 sec_rect *dst_rect, int *dst_memcpy_flag)
951{
952 unsigned int dst_phys_addr = 0;
953
954 if (HWC_PHYS_MEM_TYPE == dst_img->mem_type && 0 != dst_img->base)
955 dst_phys_addr = dst_img->base;
956 else
957 dst_phys_addr = dst_img->base;
958
959 return dst_phys_addr;
960}
961
962static inline int rotateValueHAL2PP(unsigned char transform)
963{
964 int rotate_flag = transform & 0x7;
965
966 switch (rotate_flag) {
967 case HAL_TRANSFORM_ROT_90: return 90;
968 case HAL_TRANSFORM_ROT_180: return 180;
969 case HAL_TRANSFORM_ROT_270: return 270;
970 case HAL_TRANSFORM_FLIP_H | HAL_TRANSFORM_ROT_90: return 90;
971 case HAL_TRANSFORM_FLIP_V | HAL_TRANSFORM_ROT_90: return 90;
972 case HAL_TRANSFORM_FLIP_H: return 0;
973 case HAL_TRANSFORM_FLIP_V: return 0;
974 }
975 return 0;
976}
977
978static inline int hflipValueHAL2PP(unsigned char transform)
979{
980 int flip_flag = transform & 0x7;
981 switch (flip_flag) {
982 case HAL_TRANSFORM_FLIP_H:
983 case HAL_TRANSFORM_FLIP_H | HAL_TRANSFORM_ROT_90:
984 return 1;
985 case HAL_TRANSFORM_FLIP_V | HAL_TRANSFORM_ROT_90:
986 case HAL_TRANSFORM_ROT_90:
987 case HAL_TRANSFORM_ROT_180:
988 case HAL_TRANSFORM_ROT_270:
989 case HAL_TRANSFORM_FLIP_V:
990 break;
991 }
992 return 0;
993}
994
995static inline int vflipValueHAL2PP(unsigned char transform)
996{
997 int flip_flag = transform & 0x7;
998 switch (flip_flag) {
999 case HAL_TRANSFORM_FLIP_V:
1000 case HAL_TRANSFORM_FLIP_V | HAL_TRANSFORM_ROT_90:
1001 return 1;
1002 case HAL_TRANSFORM_FLIP_H | HAL_TRANSFORM_ROT_90:
1003 case HAL_TRANSFORM_ROT_90:
1004 case HAL_TRANSFORM_ROT_180:
1005 case HAL_TRANSFORM_ROT_270:
1006 case HAL_TRANSFORM_FLIP_H:
1007 break;
1008 }
1009 return 0;
1010}
1011
1012static inline int multipleOf2(int number)
1013{
1014 if (number % 2 == 1)
1015 return (number - 1);
1016 else
1017 return number;
1018}
1019
1020static inline int multipleOf4(int number)
1021{
1022 int remain_number = number % 4;
1023
1024 if (remain_number != 0)
1025 return (number - remain_number);
1026 else
1027 return number;
1028}
1029
1030static inline int multipleOf8(int number)
1031{
1032 int remain_number = number % 8;
1033
1034 if (remain_number != 0)
1035 return (number - remain_number);
1036 else
1037 return number;
1038}
1039
1040static inline int multipleOf16(int number)
1041{
1042 int remain_number = number % 16;
1043
1044 if (remain_number != 0)
1045 return (number - remain_number);
1046 else
1047 return number;
1048}
1049
1050static inline int widthOfPP(unsigned int ver, int pp_color_format, int number)
1051{
1052#ifdef BOARD_USE_V4L2_ION
1053 if (1) {
1054#else
1055 if (0x50 <= ver) {
1056#endif
1057 switch (pp_color_format) {
1058 /* 422 1/2/3 plane */
1059 case V4L2_PIX_FMT_YUYV:
1060 case V4L2_PIX_FMT_UYVY:
1061 case V4L2_PIX_FMT_NV61:
1062 case V4L2_PIX_FMT_NV16:
1063 case V4L2_PIX_FMT_YUV422P:
1064
1065 /* 420 2/3 plane */
1066 case V4L2_PIX_FMT_NV21:
1067 case V4L2_PIX_FMT_NV12:
1068 case V4L2_PIX_FMT_NV12T:
1069 case V4L2_PIX_FMT_YUV420:
1070 return multipleOf2(number);
1071
1072 default :
1073 return number;
1074 }
1075 } else {
1076 switch (pp_color_format) {
1077 case V4L2_PIX_FMT_RGB565:
1078 return multipleOf8(number);
1079
1080 case V4L2_PIX_FMT_RGB32:
1081 return multipleOf4(number);
1082
1083 case V4L2_PIX_FMT_YUYV:
1084 case V4L2_PIX_FMT_UYVY:
1085 return multipleOf4(number);
1086
1087 case V4L2_PIX_FMT_NV61:
1088 case V4L2_PIX_FMT_NV16:
1089 return multipleOf8(number);
1090
1091 case V4L2_PIX_FMT_YUV422P:
1092 return multipleOf16(number);
1093
1094 case V4L2_PIX_FMT_NV21:
1095 case V4L2_PIX_FMT_NV12:
1096 case V4L2_PIX_FMT_NV12T:
1097 return multipleOf8(number);
1098
1099 case V4L2_PIX_FMT_YUV420:
1100 return multipleOf16(number);
1101
1102 default :
1103 return number;
1104 }
1105 }
1106 return number;
1107}
1108
1109static inline int heightOfPP(int pp_color_format, int number)
1110{
1111 switch (pp_color_format) {
1112 case V4L2_PIX_FMT_NV21:
1113 case V4L2_PIX_FMT_NV12:
1114 case V4L2_PIX_FMT_NV12T:
1115 case V4L2_PIX_FMT_YUV420:
1116 return multipleOf2(number);
1117
1118 default :
1119 return number;
1120 break;
1121 }
1122 return number;
1123}
1124
1125static unsigned int get_yuv_bpp(unsigned int fmt)
1126{
1127 int i, sel = -1;
1128
1129 for (i = 0; i < (int)(sizeof(yuv_list) / sizeof(struct yuv_fmt_list)); i++) {
1130 if (yuv_list[i].fmt == fmt) {
1131 sel = i;
1132 break;
1133 }
1134 }
1135
1136 if (sel == -1)
1137 return sel;
1138 else
1139 return yuv_list[sel].bpp;
1140}
1141
1142static unsigned int get_yuv_planes(unsigned int fmt)
1143{
1144 int i, sel = -1;
1145
1146 for (i = 0; i < (int)(sizeof(yuv_list) / sizeof(struct yuv_fmt_list)); i++) {
1147 if (yuv_list[i].fmt == fmt) {
1148 sel = i;
1149 break;
1150 }
1151 }
1152
1153 if (sel == -1)
1154 return sel;
1155 else
1156 return yuv_list[sel].planes;
1157}
1158
1159static int runcFimcCore(struct hwc_context_t *ctx,
1160 unsigned int src_phys_addr, sec_img *src_img, sec_rect *src_rect,
1161 uint32_t src_color_space,
1162 unsigned int dst_phys_addr, sec_img *dst_img, sec_rect *dst_rect,
1163 uint32_t dst_color_space, int transform)
1164{
1165 s5p_fimc_t * fimc = &ctx->fimc;
1166 s5p_fimc_params_t * params = &(fimc->params);
1167
1168 struct fimc_buf fimc_src_buf;
1169 int src_bpp, src_planes;
1170
1171#ifdef BOARD_USE_V4L2_ION
1172 struct fimc_buf fimc_dst_buf;
1173 int dst_bpp, dst_planes;
1174 unsigned int src_frame_size = 0;
1175 unsigned int dst_frame_size = 0;
1176#endif
1177 unsigned int frame_size = 0;
1178
1179 bool src_cbcr_order = true;
1180 int rotate_value = rotateValueHAL2PP(transform);
1181 int hflip = hflipValueHAL2PP(transform);
1182 int vflip = vflipValueHAL2PP(transform);
1183
1184 /* 1. param(fimc config)->src information
1185 * - src_img,src_rect => s_fw,s_fh,s_w,s_h,s_x,s_y
1186 */
1187 params->src.full_width = src_img->f_w;
1188 params->src.full_height = src_img->f_h;
1189 params->src.width = src_rect->w;
1190 params->src.height = src_rect->h;
1191 params->src.start_x = src_rect->x;
1192 params->src.start_y = src_rect->y;
1193 params->src.color_space = src_color_space;
1194 params->src.buf_addr_phy_rgb_y = src_phys_addr;
1195
1196#ifdef BOARD_USE_V4L2_ION
1197 params->dst.full_width = dst_img->f_w;
1198 params->dst.full_height = dst_img->f_h;
1199 params->dst.width = widthOfPP(fimc->hw_ver, dst_color_space, dst_rect->w);
1200 params->dst.height = heightOfPP(dst_color_space, dst_rect->h);
1201 params->dst.start_x = dst_rect->x;
1202 params->dst.start_y = dst_rect->y;
1203 params->dst.color_space = dst_color_space;
1204 params->dst.buf_addr_phy_rgb_y = dst_phys_addr;
1205#endif
1206
1207 /* check src minimum */
1208 if (src_rect->w < 16 || src_rect->h < 8) {
1209 SEC_HWC_Log(HWC_LOG_ERROR,
1210 "%s src size is not supported by fimc : f_w=%d f_h=%d "
1211 "x=%d y=%d w=%d h=%d (ow=%d oh=%d) format=0x%x", __func__,
1212 params->src.full_width, params->src.full_height,
1213 params->src.start_x, params->src.start_y,
1214 params->src.width, params->src.height,
1215 src_rect->w, src_rect->h,
1216 params->src.color_space);
1217 return -1;
1218 }
1219
1220#ifdef BOARD_USE_V4L2_ION
1221#else
1222 /* 2. param(fimc config)->dst information
1223 * - dst_img,dst_rect,rot => d_fw,d_fh,d_w,d_h,d_x,d_y
1224 */
1225 switch (rotate_value) {
1226 case 0:
1227 params->dst.full_width = dst_img->f_w;
1228 params->dst.full_height = dst_img->f_h;
1229
1230 params->dst.start_x = dst_rect->x;
1231 params->dst.start_y = dst_rect->y;
1232
1233 params->dst.width =
1234 widthOfPP(fimc->hw_ver, dst_color_space, dst_rect->w);
1235 params->dst.height = heightOfPP(dst_color_space, dst_rect->h);
1236 break;
1237 case 90:
1238 params->dst.full_width = dst_img->f_h;
1239 params->dst.full_height = dst_img->f_w;
1240
1241 params->dst.start_x = dst_rect->y;
1242 params->dst.start_y = dst_img->f_w - (dst_rect->x + dst_rect->w);
1243
1244 params->dst.width =
1245 widthOfPP(fimc->hw_ver, dst_color_space, dst_rect->h);
1246 params->dst.height =
1247 widthOfPP(fimc->hw_ver, dst_color_space, dst_rect->w);
1248
1249 if (0x50 > fimc->hw_ver)
1250 params->dst.start_y += (dst_rect->w - params->dst.height);
1251 break;
1252 case 180:
1253 params->dst.full_width = dst_img->f_w;
1254 params->dst.full_height = dst_img->f_h;
1255
1256 params->dst.start_x = dst_img->f_w - (dst_rect->x + dst_rect->w);
1257 params->dst.start_y = dst_img->f_h - (dst_rect->y + dst_rect->h);
1258
1259 params->dst.width =
1260 widthOfPP(fimc->hw_ver, dst_color_space, dst_rect->w);
1261 params->dst.height = heightOfPP(dst_color_space, dst_rect->h);
1262 break;
1263 case 270:
1264 params->dst.full_width = dst_img->f_h;
1265 params->dst.full_height = dst_img->f_w;
1266
1267 params->dst.start_x = dst_img->f_h - (dst_rect->y + dst_rect->h);
1268 params->dst.start_y = dst_rect->x;
1269
1270 params->dst.width =
1271 widthOfPP(fimc->hw_ver, dst_color_space, dst_rect->h);
1272 params->dst.height =
1273 widthOfPP(fimc->hw_ver, dst_color_space, dst_rect->w);
1274
1275 if (0x50 > fimc->hw_ver)
1276 params->dst.start_y += (dst_rect->w - params->dst.height);
1277 break;
1278 }
1279 params->dst.color_space = dst_color_space;
1280#endif
1281
1282 SEC_HWC_Log(HWC_LOG_DEBUG,
1283 "runcFimcCore()::"
1284 "SRC f.w(%d),f.h(%d),x(%d),y(%d),w(%d),h(%d)=>"
1285 "DST f.w(%d),f.h(%d),x(%d),y(%d),w(%d),h(%d)",
1286 params->src.full_width, params->src.full_height,
1287 params->src.start_x, params->src.start_y,
1288 params->src.width, params->src.height,
1289 params->dst.full_width, params->dst.full_height,
1290 params->dst.start_x, params->dst.start_y,
1291 params->dst.width, params->dst.height);
1292
1293 /* check dst minimum */
1294 if (dst_rect->w < 8 || dst_rect->h < 4) {
1295 SEC_HWC_Log(HWC_LOG_ERROR,
1296 "%s dst size is not supported by fimc : f_w=%d f_h=%d "
1297 "x=%d y=%d w=%d h=%d (ow=%d oh=%d) format=0x%x", __func__,
1298 params->dst.full_width, params->dst.full_height,
1299 params->dst.start_x, params->dst.start_y,
1300 params->dst.width, params->dst.height,
1301 dst_rect->w, dst_rect->h, params->dst.color_space);
1302 return -1;
1303 }
1304 /* check scaling limit
1305 * the scaling limie must not be more than MAX_RESIZING_RATIO_LIMIT
1306 */
1307 if (((src_rect->w > dst_rect->w) &&
1308 ((src_rect->w / dst_rect->w) > MAX_RESIZING_RATIO_LIMIT)) ||
1309 ((dst_rect->w > src_rect->w) &&
1310 ((dst_rect->w / src_rect->w) > MAX_RESIZING_RATIO_LIMIT))) {
1311 SEC_HWC_Log(HWC_LOG_ERROR,
1312 "%s over scaling limit : src.w=%d dst.w=%d (limit=%d)",
1313 __func__, src_rect->w, dst_rect->w, MAX_RESIZING_RATIO_LIMIT);
1314 return -1;
1315 }
1316
1317 /* 3. Set configuration related to destination (DMA-OUT)
1318 * - set input format & size
1319 * - crop input size
1320 * - set input buffer
1321 * - set buffer type (V4L2_MEMORY_USERPTR)
1322 */
1323#ifdef BOARD_USE_V4L2_ION
1324 switch (dst_img->format) {
1325 case HAL_PIXEL_FORMAT_RGBA_8888:
1326 case HAL_PIXEL_FORMAT_RGBX_8888:
1327 case HAL_PIXEL_FORMAT_RGB_888:
1328 case HAL_PIXEL_FORMAT_BGRA_8888:
1329 dst_planes = 1;
1330 dst_bpp = 32;
1331 break;
1332
1333 case HAL_PIXEL_FORMAT_RGB_565:
1334 case HAL_PIXEL_FORMAT_RGBA_5551:
1335 case HAL_PIXEL_FORMAT_RGBA_4444:
1336 dst_planes = 1;
1337 dst_bpp = 16;
1338 break;
1339 }
1340
1341 dst_frame_size = params->dst.width * params->dst.height ;
1342 params->dst.planes = dst_planes;
1343
1344 if (dst_planes == 1) {
1345 fimc_dst_buf.base[0] = params->dst.buf_addr_phy_rgb_y;
1346 if (dst_bpp == 32)
1347 fimc_dst_buf.size[0] = dst_frame_size * 4;
1348 else if (dst_bpp == 16)
1349 fimc_dst_buf.size[0] = dst_frame_size * 2;
1350 }
1351#endif
1352
1353 if (fimc_v4l2_set_dst(fimc->dev_fd, &params->dst, rotate_value, hflip, vflip, dst_phys_addr) < 0) {
1354 SEC_HWC_Log(HWC_LOG_ERROR, "fimc_v4l2_set_dst is failed\n");
1355 return -1;
1356 }
1357
1358 /* 4. Set configuration related to source (DMA-INPUT)
1359 * - set input format & size
1360 * - crop input size
1361 * - set input buffer
1362 * - set buffer type (V4L2_MEMORY_USERPTR)
1363 */
1364#ifndef BOARD_USE_V4L2_ION
1365 if (fimc_v4l2_set_src(fimc->dev_fd, fimc->hw_ver, &params->src) < 0) {
1366 SEC_HWC_Log(HWC_LOG_ERROR, "fimc_v4l2_set_src is failed\n");
1367 return -1;
1368 }
1369#endif
1370
1371 /* 5. Set input dma address (Y/RGB, Cb, Cr)
1372 * - zero copy : mfc, camera
1373 * - memcpy to pmem : SW dec(420P), video editor(YV12)
1374 */
1375 switch (src_img->format) {
1376 case HAL_PIXEL_FORMAT_CUSTOM_YCbCr_420_SP:
1377 case HAL_PIXEL_FORMAT_CUSTOM_YCrCb_420_SP:
1378 case HAL_PIXEL_FORMAT_CUSTOM_YCbCr_420_SP_TILED:
1379 case HAL_PIXEL_FORMAT_CUSTOM_YCbCr_422_SP:
1380 case HAL_PIXEL_FORMAT_CUSTOM_YCrCb_422_SP:
1381 /* for video contents zero copy case */
1382 fimc_src_buf.base[0] = params->src.buf_addr_phy_rgb_y;
1383 fimc_src_buf.base[1] = params->src.buf_addr_phy_cb;
1384 break;
1385
1386 case HAL_PIXEL_FORMAT_CUSTOM_YCbCr_422_I:
1387 case HAL_PIXEL_FORMAT_CUSTOM_YCrCb_422_I:
1388 case HAL_PIXEL_FORMAT_CUSTOM_CbYCrY_422_I:
1389 case HAL_PIXEL_FORMAT_CUSTOM_CrYCbY_422_I:
1390 case HAL_PIXEL_FORMAT_RGB_565:
1391 case HAL_PIXEL_FORMAT_YV12:
1392 default:
1393 if (src_img->format == HAL_PIXEL_FORMAT_YV12)
1394 src_cbcr_order = false;
1395
1396#ifdef BOARD_USE_V4L2_ION
1397 fimc_src_buf.base[0] = params->src.buf_addr_phy_rgb_y;
1398 if (src_cbcr_order == true) {
1399 fimc_src_buf.base[1] = params->src.buf_addr_phy_cb;
1400 fimc_src_buf.base[2] = params->src.buf_addr_phy_cr;
1401 } else {
1402 fimc_src_buf.base[1] = params->src.buf_addr_phy_cr;
1403 fimc_src_buf.base[2] = params->src.buf_addr_phy_cb;
1404 }
1405 SEC_HWC_Log(HWC_LOG_DEBUG,
1406 "runFimcCore - Y=0x%X, U=0x%X, V=0x%X\n",
1407 fimc_src_buf.base[0], fimc_src_buf.base[1],fimc_src_buf.base[2]);
1408 src_frame_size = params->src.full_width * params->src.full_height;
1409 fimc_src_buf.size[0] = src_frame_size;
1410 fimc_src_buf.size[1] = src_frame_size >> 2;
1411 fimc_src_buf.size[2] = src_frame_size >> 2;
1412 SEC_HWC_Log(HWC_LOG_DEBUG,
1413 "runFimcCore - Y_length=%d, U_length=%d, V_length=%d\n",
1414 fimc_src_buf.size[0], fimc_src_buf.size[1],fimc_src_buf.size[2]);
1415 src_planes = get_yuv_planes(src_color_space);
1416
1417 break;
1418#endif
1419
1420 if (src_img->usage & GRALLOC_USAGE_HW_FIMC1) {
1421 fimc_src_buf.base[0] = params->src.buf_addr_phy_rgb_y;
1422 if (src_cbcr_order == true) {
1423 fimc_src_buf.base[1] = params->src.buf_addr_phy_cb;
1424 fimc_src_buf.base[2] = params->src.buf_addr_phy_cr;
1425 }
1426 else {
1427 fimc_src_buf.base[2] = params->src.buf_addr_phy_cb;
1428 fimc_src_buf.base[1] = params->src.buf_addr_phy_cr;
1429 }
1430 SEC_HWC_Log(HWC_LOG_DEBUG,
1431 "runFimcCore - Y=0x%X, U=0x%X, V=0x%X\n",
1432 fimc_src_buf.base[0], fimc_src_buf.base[1],fimc_src_buf.base[2]);
1433 break;
1434 }
1435
1436 /* set source Y image */
1437 fimc_src_buf.base[0] = params->src.buf_addr_phy_rgb_y;
1438 /* set source Cb,Cr images for 2 or 3 planes */
1439 src_bpp = get_yuv_bpp(src_color_space);
1440 src_planes = get_yuv_planes(src_color_space);
1441 if (2 == src_planes) { /* 2 planes */
1442 frame_size = params->src.full_width * params->src.full_height;
1443 params->src.buf_addr_phy_cb =
1444 params->src.buf_addr_phy_rgb_y + frame_size;
1445 /* CbCr */
1446 fimc_src_buf.base[1] = params->src.buf_addr_phy_cb;
1447 } else if (3 == src_planes) { /* 3 planes */
1448 frame_size = params->src.full_width * params->src.full_height;
1449 params->src.buf_addr_phy_cb =
1450 params->src.buf_addr_phy_rgb_y + frame_size;
1451 if (12 == src_bpp)
1452 params->src.buf_addr_phy_cr =
1453 params->src.buf_addr_phy_cb + (frame_size >> 2);
1454 else
1455 params->src.buf_addr_phy_cr =
1456 params->src.buf_addr_phy_cb + (frame_size >> 1);
1457 /* Cb, Cr */
1458 if (src_cbcr_order == true) {
1459 fimc_src_buf.base[1] = params->src.buf_addr_phy_cb;
1460 fimc_src_buf.base[2] = params->src.buf_addr_phy_cr;
1461 }
1462 else {
1463 fimc_src_buf.base[2] = params->src.buf_addr_phy_cb;
1464 fimc_src_buf.base[1] = params->src.buf_addr_phy_cr;
1465 }
1466 }
1467 break;
1468 }
1469
1470 /* 6. Run FIMC
1471 * - stream on => queue => dequeue => stream off => clear buf
1472 */
1473#ifdef BOARD_USE_V4L2_ION
1474 int ret = 0;
1475 params->src.planes = src_planes;
1476
1477 if (fimc_v4l2_set_src(fimc->dev_fd, fimc->hw_ver, &params->src) < 0) {
1478 SEC_HWC_Log(HWC_LOG_ERROR, "fimc_v4l2_set_src is failed\n");
1479 return -1;
1480 }
1481
1482 fimc_src_buf.planes = src_planes;
1483 fimc_dst_buf.planes = dst_planes;
1484
1485 ret = fimc_handle_oneshot(fimc->dev_fd, &fimc_src_buf, &fimc_dst_buf);
1486
1487 if (ret < 0) {
1488 SEC_HWC_Log(HWC_LOG_ERROR,"fimc_handle_oneshot = %d\n",ret);
1489 if (ret == -2) {
1490 fimc_v4l2_clr_buf(fimc->dev_fd, V4L2_BUF_TYPE_OUTPUT);
1491 } else if (ret == -3) {
1492 fimc_v4l2_clr_buf(fimc->dev_fd, V4L2_BUF_TYPE_OUTPUT);
1493 fimc_v4l2_clr_buf(fimc->dev_fd, V4L2_BUF_TYPE_CAPTURE);
1494 }
1495 return ret;
1496 }
1497#else
1498 if (fimc_handle_oneshot(fimc->dev_fd, &fimc_src_buf, NULL) < 0) {
1499 fimc_v4l2_clr_buf(fimc->dev_fd, V4L2_BUF_TYPE_OUTPUT);
1500 return -1;
1501 }
1502#endif
1503
1504 return 0;
1505}
1506
1507#ifdef SUB_TITLES_HWC
1508int createG2d(sec_g2d_t *g2d)
1509{
1510 g2d->dev_fd = open(SEC_G2D_DEV_NAME, O_RDWR);
1511
1512 if (g2d->dev_fd <= 0) {
1513 SEC_HWC_Log(HWC_LOG_ERROR, "%s::G2d open error (%d)", __func__, errno);
1514 goto err;
1515 }
1516
1517 return 0;
1518err:
1519 if (0 < g2d->dev_fd)
1520 close(g2d->dev_fd);
1521 g2d->dev_fd =0;
1522
1523 return -1;
1524}
1525
1526int destroyG2d(sec_g2d_t *g2d)
1527{
1528 // close
1529 if (0 < g2d->dev_fd)
1530 close(g2d->dev_fd);
1531 g2d->dev_fd = 0;
1532
1533 return 0;
1534}
1535#endif
1536
1537int createFimc(s5p_fimc_t *fimc)
1538{
1539 struct v4l2_capability cap;
1540 struct v4l2_format fmt;
1541 struct v4l2_control vc;
1542
1543 // open device file
1544 if (fimc->dev_fd <= 0)
1545 fimc->dev_fd = open(PP_DEVICE_DEV_NAME, O_RDWR);
1546
1547 if (fimc->dev_fd <= 0) {
1548 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Post processor open error (%d)",
1549 __func__, errno);
1550 goto err;
1551 }
1552
1553 // check capability
1554 if (ioctl(fimc->dev_fd, VIDIOC_QUERYCAP, &cap) < 0) {
1555 SEC_HWC_Log(HWC_LOG_ERROR, "VIDIOC_QUERYCAP failed");
1556 goto err;
1557 }
1558
1559 if (!(cap.capabilities & V4L2_CAP_STREAMING)) {
1560 SEC_HWC_Log(HWC_LOG_ERROR, "%d has no streaming support", fimc->dev_fd);
1561 goto err;
1562 }
1563
1564 if (!(cap.capabilities & V4L2_CAP_VIDEO_OUTPUT)) {
1565 SEC_HWC_Log(HWC_LOG_ERROR, "%d is no video output", fimc->dev_fd);
1566 goto err;
1567 }
1568
1569 /*
1570 * malloc fimc_outinfo structure
1571 */
1572 fmt.type = V4L2_BUF_TYPE_OUTPUT;
1573 if (ioctl(fimc->dev_fd, VIDIOC_G_FMT, &fmt) < 0) {
1574 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Error in video VIDIOC_G_FMT", __func__);
1575 goto err;
1576 }
1577
1578#ifdef BOARD_USE_V4L2_ION
1579#else
1580 vc.id = V4L2_CID_FIMC_VERSION;
1581 vc.value = 0;
1582
1583 if (ioctl(fimc->dev_fd, VIDIOC_G_CTRL, &vc) < 0) {
1584 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Error in video VIDIOC_G_CTRL", __func__);
1585 goto err;
1586 }
1587 fimc->hw_ver = vc.value;
1588#endif
1589
1590 return 0;
1591
1592err:
1593 if (0 < fimc->dev_fd)
1594 close(fimc->dev_fd);
1595 fimc->dev_fd =0;
1596
1597 return -1;
1598}
1599
1600int destroyFimc(s5p_fimc_t *fimc)
1601{
1602 if (fimc->out_buf.virt_addr != NULL) {
1603 fimc->out_buf.virt_addr = NULL;
1604 fimc->out_buf.length = 0;
1605 }
1606
1607 // close
1608 if (0 < fimc->dev_fd)
1609 close(fimc->dev_fd);
1610 fimc->dev_fd = 0;
1611
1612 return 0;
1613}
1614
1615int runFimc(struct hwc_context_t *ctx,
1616 struct sec_img *src_img, struct sec_rect *src_rect,
1617 struct sec_img *dst_img, struct sec_rect *dst_rect,
1618 uint32_t transform)
1619{
1620 s5p_fimc_t * fimc = &ctx->fimc;
1621
1622 unsigned int src_phys_addr = 0;
1623 unsigned int dst_phys_addr = 0;
1624 int rotate_value = 0;
1625 int flag_force_memcpy = 0;
1626 int32_t src_color_space;
1627 int32_t dst_color_space;
1628
1629 /* 1. source address and size */
1630 src_phys_addr = get_src_phys_addr(ctx, src_img, src_rect);
1631 if (0 == src_phys_addr)
1632 return -1;
1633
1634 /* 2. destination address and size */
1635 dst_phys_addr = get_dst_phys_addr(ctx, dst_img, dst_rect, &flag_force_memcpy);
1636 if (0 == dst_phys_addr)
1637 return -2;
1638
1639 /* 3. check whether fimc supports the src format */
1640 src_color_space = HAL_PIXEL_FORMAT_2_V4L2_PIX(src_img->format);
1641 if (0 > src_color_space)
1642 return -3;
1643 dst_color_space = HAL_PIXEL_FORMAT_2_V4L2_PIX(dst_img->format);
1644 if (0 > dst_color_space)
1645 return -4;
1646
1647 /* 4. FIMC: src_rect of src_img => dst_rect of dst_img */
1648 if (runcFimcCore(ctx, src_phys_addr, src_img, src_rect,
1649 (uint32_t)src_color_space, dst_phys_addr, dst_img, dst_rect,
1650 (uint32_t)dst_color_space, transform) < 0)
1651 return -5;
1652
1653 if (flag_force_memcpy == 1) {
1654#ifdef USE_HW_PMEM
1655 if (0 != ctx->sec_pmem.sec_pmem_alloc[1].size) {
1656 struct s3c_mem_dma_param s3c_mem_dma;
1657
1658 s3c_mem_dma.src_addr =
1659 (unsigned long)(ctx->sec_pmem.sec_pmem_alloc[1].virt_addr);
1660 s3c_mem_dma.size = ctx->sec_pmem.sec_pmem_alloc[1].size;
1661
1662 ioctl(ctx->s3c_mem.fd, S3C_MEM_CACHE_INVAL, &s3c_mem_dma);
1663
1664 memcpy((void*)((unsigned int)dst_img->base),
1665 (void *)(ctx->sec_pmem.sec_pmem_alloc[1].virt_addr),
1666 ctx->sec_pmem.sec_pmem_alloc[1].size);
1667 } else
1668#endif
1669 {
1670 struct s3c_mem_alloc *ptr_mem_alloc = &ctx->s3c_mem.mem_alloc[1];
1671 struct s3c_mem_dma_param s3c_mem_dma;
1672
1673 s3c_mem_dma.src_addr = (unsigned long)ptr_mem_alloc->vir_addr;
1674 s3c_mem_dma.size = ptr_mem_alloc->size;
1675
1676 ioctl(ctx->s3c_mem.fd, S3C_MEM_CACHE_INVAL, &s3c_mem_dma);
1677
1678 memcpy((void*)((unsigned int)dst_img->base),
1679 (void *)ptr_mem_alloc->vir_addr, ptr_mem_alloc->size);
1680 }
1681 }
1682
1683 return 0;
1684}
1685
1686#ifdef SUB_TITLES_HWC
1687static int get_g2d_src_phys_addr(struct hwc_context_t *ctx, g2d_rect *src_rect)
1688{
1689 sec_g2d_t *g2d = &ctx->g2d;
1690 struct s3c_mem_alloc *ptr_mem_alloc = &ctx->s3c_mem.mem_alloc[0];
1691#ifdef USE_HW_PMEM
1692 sec_pmem_alloc_t *pm_alloc = &ctx->sec_pmem.sec_pmem_alloc[0];
1693#endif
1694
1695 unsigned int src_virt_addr = 0;
1696 unsigned int src_phys_addr = 0;
1697 unsigned int src_frame_size = 0;
1698
1699 struct pmem_region region;
1700
1701 // error check routine
1702 if (0 == src_rect->virt_addr) {
1703 SEC_HWC_Log(HWC_LOG_ERROR, "%s invalid src address\n", __func__);
1704 return 0;
1705 }
1706
1707 src_frame_size = FRAME_SIZE(src_rect->color_format,
1708 src_rect->full_w, src_rect->full_h);
1709 if (src_frame_size == 0) {
1710 SEC_HWC_Log(HWC_LOG_ERROR, "%s::FRAME_SIZE fail", __func__);
1711 return 0;
1712 }
1713
1714#ifdef USE_HW_PMEM
1715 if (0 <= checkPmem(&ctx->sec_pmem, 0, src_frame_size)) {
1716 src_virt_addr = pm_alloc->virt_addr;
1717 src_phys_addr = pm_alloc->phys_addr;
1718 pm_alloc->size = src_frame_size;
1719 } else
1720#endif
1721 if (0 <= checkMem(&ctx->s3c_mem, 0, src_frame_size)) {
1722 src_virt_addr = ptr_mem_alloc->vir_addr;
1723 src_phys_addr = ptr_mem_alloc->phy_addr;
1724 ptr_mem_alloc->size = src_frame_size;
1725 } else {
1726 SEC_HWC_Log(HWC_LOG_ERROR, "%s::check_mem fail", __func__);
1727 return 0;
1728 }
1729 memcpy((void *)src_virt_addr, (void*)((unsigned int)src_rect->virt_addr), src_frame_size);
1730
1731 return src_phys_addr;
1732}
1733
1734int get_HAL_2_G2D_FORMAT(int format)
1735{
1736 switch (format) {
1737 case HAL_PIXEL_FORMAT_RGBA_8888: return G2D_ABGR_8888;
1738 case HAL_PIXEL_FORMAT_RGBX_8888: return G2D_XBGR_8888;
1739 case HAL_PIXEL_FORMAT_BGRA_8888: return G2D_ARGB_8888;
1740 case HAL_PIXEL_FORMAT_RGB_888: return G2D_PACKED_BGR_888;
1741 case HAL_PIXEL_FORMAT_RGB_565: return G2D_RGB_565;
1742 case HAL_PIXEL_FORMAT_RGBA_5551: return G2D_RGBA_5551;
1743 case HAL_PIXEL_FORMAT_RGBA_4444: return G2D_RGBA_4444;
1744 default:
1745 return -1;
1746 }
1747}
1748
1749static inline int rotateValueHAL2G2D(unsigned char transform)
1750{
1751 int rotate_flag = transform & 0x7;
1752
1753 switch (rotate_flag) {
1754 case HAL_TRANSFORM_ROT_90: return G2D_ROT_90;
1755 case HAL_TRANSFORM_ROT_180: return G2D_ROT_180;
1756 case HAL_TRANSFORM_ROT_270: return G2D_ROT_270;
1757 default:
1758 return G2D_ROT_0;
1759 }
1760}
1761
1762int runG2d(struct hwc_context_t *ctx, g2d_rect *src_rect, g2d_rect *dst_rect,
1763 uint32_t transform)
1764{
1765 sec_g2d_t * g2d = &ctx->g2d;
1766 g2d_flag flag = {G2D_ROT_0, G2D_ALPHA_BLENDING_OPAQUE, 0, 0, 0, 0, 0, 0};
1767 int rotate_value = 0;
1768
1769 // 1 : source address and size
1770 src_rect->phys_addr = get_g2d_src_phys_addr(ctx, src_rect);
1771 if (0 == src_rect->phys_addr)
1772 return -1;
1773
1774 // 2 : destination address and size
1775 if (0 == dst_rect->phys_addr)
1776 return -2;
1777
1778 // check whether g2d supports the src format
1779 src_rect->color_format = get_HAL_2_G2D_FORMAT(src_rect->color_format);
1780 if (0 > src_rect->color_format)
1781 return -3;
1782
1783 dst_rect->color_format = get_HAL_2_G2D_FORMAT(dst_rect->color_format);
1784 if (0 > dst_rect->color_format)
1785 return -4;
1786
1787 flag.rotate_val = rotateValueHAL2G2D(transform);
1788
1789 // scale and rotate and alpha with FIMG
1790 if(stretchSecFimg(src_rect, dst_rect, &flag) < 0)
1791 return -5;
1792
1793 return 0;
1794}
1795#endif
1796
1797int createMem(struct s3c_mem_t *mem, unsigned int index, unsigned int size)
1798{
1799 struct s3c_mem_alloc *ptr_mem_alloc;
1800 struct s3c_mem_alloc mem_alloc_info;
1801
1802 if (index >= NUM_OF_MEM_OBJ) {
1803 SEC_HWC_Log(HWC_LOG_ERROR, "%s::invalid index (%d >= %d)",
1804 __func__, index, NUM_OF_MEM_OBJ);
1805 goto err;
1806 }
1807
1808 ptr_mem_alloc = &mem->mem_alloc[index];
1809
1810 if (mem->fd <= 0) {
1811 mem->fd = open(S3C_MEM_DEV_NAME, O_RDWR);
1812 if (mem->fd <= 0) {
1813 SEC_HWC_Log(HWC_LOG_ERROR, "%s::open(%s) fail(%s)",
1814 __func__, S3C_MEM_DEV_NAME, strerror(errno));
1815 goto err;
1816 }
1817 }
1818
1819 // kcoolsw : what the hell of this line??
1820 if (0 == size)
1821 return 0;
1822
1823 mem_alloc_info.size = size;
1824
1825 if (ioctl(mem->fd, S3C_MEM_CACHEABLE_ALLOC, &mem_alloc_info) < 0) {
1826 SEC_HWC_Log(HWC_LOG_ERROR, "%s::S3C_MEM_ALLOC(size : %d) fail",
1827 __func__, mem_alloc_info.size);
1828 goto err;
1829 }
1830
1831 ptr_mem_alloc->phy_addr = mem_alloc_info.phy_addr;
1832 ptr_mem_alloc->vir_addr = mem_alloc_info.vir_addr;
1833 ptr_mem_alloc->size = mem_alloc_info.size;
1834
1835 return 0;
1836
1837err:
1838 if (0 < mem->fd)
1839 close(mem->fd);
1840 mem->fd = 0;
1841
1842 return 0;
1843}
1844
1845int destroyMem(struct s3c_mem_t *mem)
1846{
1847 int i;
1848 struct s3c_mem_alloc *ptr_mem_alloc;
1849
1850 if (mem->fd <= 0) {
1851 SEC_HWC_Log(HWC_LOG_ERROR, "%s::invalied fd(%d) fail", __func__, mem->fd);
1852 return -1;
1853 }
1854
1855 for (i = 0; i < NUM_OF_MEM_OBJ; i++) {
1856 ptr_mem_alloc = &mem->mem_alloc[i];
1857
1858 if (0 != ptr_mem_alloc->vir_addr) {
1859 if (ioctl(mem->fd, S3C_MEM_FREE, ptr_mem_alloc) < 0) {
1860 SEC_HWC_Log(HWC_LOG_ERROR, "%s::S3C_MEM_FREE fail", __func__);
1861 return -1;
1862 }
1863
1864 ptr_mem_alloc->phy_addr = 0;
1865 ptr_mem_alloc->vir_addr = 0;
1866 ptr_mem_alloc->size = 0;
1867 }
1868 }
1869
1870 close(mem->fd);
1871 mem->fd = 0;
1872
1873 return 0;
1874}
1875
1876int checkMem(struct s3c_mem_t *mem, unsigned int index, unsigned int size)
1877{
1878 int ret;
1879 struct s3c_mem_alloc *ptr_mem_alloc;
1880 struct s3c_mem_alloc mem_alloc_info;
1881
1882 if (index >= NUM_OF_MEM_OBJ) {
1883 SEC_HWC_Log(HWC_LOG_ERROR, "%s::invalid index (%d >= %d)", __func__,
1884 index, NUM_OF_MEM_OBJ);
1885 return -1;
1886 }
1887
1888 if (mem->fd <= 0) {
1889 ret = createMem(mem, index, size);
1890 return ret;
1891 }
1892
1893 ptr_mem_alloc = &mem->mem_alloc[index];
1894
1895 if (ptr_mem_alloc->size < (int)size) {
1896 if (0 < ptr_mem_alloc->size) {
1897 // free allocated mem
1898 if (ioctl(mem->fd, S3C_MEM_FREE, ptr_mem_alloc) < 0) {
1899 SEC_HWC_Log(HWC_LOG_ERROR, "%s::S3C_MEM_FREE fail", __func__);
1900 return -1;
1901 }
1902 }
1903
1904 // allocate mem with requested size
1905 mem_alloc_info.size = size;
1906 if (ioctl(mem->fd, S3C_MEM_CACHEABLE_ALLOC, &mem_alloc_info) < 0) {
1907 SEC_HWC_Log(HWC_LOG_ERROR, "%s::S3C_MEM_ALLOC(size : %d) fail",
1908 __func__, mem_alloc_info.size);
1909 return -1;
1910 }
1911
1912 ptr_mem_alloc->phy_addr = mem_alloc_info.phy_addr;
1913 ptr_mem_alloc->vir_addr = mem_alloc_info.vir_addr;
1914 ptr_mem_alloc->size = mem_alloc_info.size;
1915 }
1916
1917 return 0;
1918}
1919
1920#ifdef USE_HW_PMEM
1921int createPmem(sec_pmem_t *pm, unsigned int buf_size)
1922{
1923 int master_fd, err = 0, i;
1924 void *base;
1925 unsigned int phys_base;
1926 size_t size, sub_size[NUM_OF_MEM_OBJ];
1927 struct pmem_region region;
1928
1929 master_fd = open(PMEM_DEVICE_DEV_NAME, O_RDWR, 0);
1930 if (master_fd < 0) {
1931 pm->pmem_master_fd = -1;
1932 if (EACCES == errno) {
1933 return 0;
1934 } else {
1935 SEC_HWC_Log(HWC_LOG_ERROR, "%s::open(%s) fail(%s)",
1936 __func__, PMEM_DEVICE_DEV_NAME, strerror(errno));
1937 return -errno;
1938 }
1939 }
1940
1941 if (ioctl(master_fd, PMEM_GET_TOTAL_SIZE, &region) < 0) {
1942 SEC_HWC_Log(HWC_LOG_ERROR, "PMEM_GET_TOTAL_SIZE failed, default mode");
1943 size = 8<<20; // 8 MiB
1944 } else {
1945 size = region.len;
1946 }
1947
1948 base = mmap(0, size, PROT_READ|PROT_WRITE, MAP_SHARED, master_fd, 0);
1949 if (base == MAP_FAILED) {
1950 SEC_HWC_Log(HWC_LOG_ERROR, "[%s] mmap failed : %d (%s)", __func__,
1951 errno, strerror(errno));
1952 base = 0;
1953 close(master_fd);
1954 master_fd = -1;
1955 return -errno;
1956 }
1957
1958 if (ioctl(master_fd, PMEM_GET_PHYS, &region) < 0) {
1959 SEC_HWC_Log(HWC_LOG_ERROR, "PMEM_GET_PHYS failed, limp mode");
1960 region.offset = 0;
1961 }
1962
1963 pm->pmem_master_fd = master_fd;
1964 pm->pmem_master_base = base;
1965 pm->pmem_total_size = size;
1966 //pm->pmem_master_phys_base = region.offset;
1967 phys_base = region.offset;
1968
1969 // sec_pmem_alloc[0] for temporary buffer for source
1970 sub_size[0] = buf_size;
1971 sub_size[0] = roundUpToPageSize(sub_size[0]);
1972
1973 for (i = 0; i < NUM_OF_MEM_OBJ; i++) {
1974 sec_pmem_alloc_t *pm_alloc = &(pm->sec_pmem_alloc[i]);
1975 int fd, ret;
1976 int offset = i ? sub_size[i-1] : 0;
1977 struct pmem_region sub = { offset, sub_size[i] };
1978
1979 // create the "sub-heap"
1980 if (0 > (fd = open(PMEM_DEVICE_DEV_NAME, O_RDWR, 0))) {
1981 SEC_HWC_Log(HWC_LOG_ERROR,
1982 "[%s][index=%d] open failed (%dL) : %d (%s)",
1983 __func__, i, __LINE__, errno, strerror(errno));
1984 return -errno;
1985 }
1986
1987 // connect to it
1988 if (0 != (ret = ioctl(fd, PMEM_CONNECT, pm->pmem_master_fd))) {
1989 SEC_HWC_Log(HWC_LOG_ERROR,
1990 "[%s][index=%d] ioctl(PMEM_CONNECT) failed : %d (%s)",
1991 __func__, i, errno, strerror(errno));
1992 close(fd);
1993 return -errno;
1994 }
1995
1996 // make it available to the client process
1997 if (0 != (ret = ioctl(fd, PMEM_MAP, &sub))) {
1998 SEC_HWC_Log(HWC_LOG_ERROR,
1999 "[%s][index=%d] ioctl(PMEM_MAP) failed : %d (%s)",
2000 __func__, i, errno, strerror(errno));
2001 close(fd);
2002 return -errno;
2003 }
2004
2005 pm_alloc->fd = fd;
2006 pm_alloc->total_size = sub_size[i];
2007 pm_alloc->offset = offset;
2008 pm_alloc->virt_addr = (unsigned int)base + (unsigned int)offset;
2009 pm_alloc->phys_addr = (unsigned int)phys_base + (unsigned int)offset;
2010
2011#if defined (PMEM_DEBUG)
2012 SEC_HWC_Log(HWC_LOG_DEBUG, "[%s] pm_alloc[%d] fd=%d total_size=%d "
2013 "offset=0x%x virt_addr=0x%x phys_addr=0x%x",
2014 __func__, i, pm_alloc->fd, pm_alloc->total_size,
2015 pm_alloc->offset, pm_alloc->virt_addr, pm_alloc->phys_addr);
2016#endif
2017 }
2018
2019 return err;
2020}
2021
2022int destroyPmem(sec_pmem_t *pm)
2023{
2024 int i, err;
2025
2026 for (i=0; i<NUM_OF_MEM_OBJ; i++) {
2027 sec_pmem_alloc_t *pm_alloc = &(pm->sec_pmem_alloc[i]);
2028
2029 if (0 <= pm_alloc->fd) {
2030 struct pmem_region sub = { pm_alloc->offset, pm_alloc->total_size };
2031
2032 if (0 > (err = ioctl(pm_alloc->fd, PMEM_UNMAP, &sub)))
2033 SEC_HWC_Log(HWC_LOG_ERROR,
2034 "[%s][index=%d] ioctl(PMEM_UNMAP) failed : %d (%s)",
2035 __func__, i, errno, strerror(errno));
2036#if defined (PMEM_DEBUG)
2037 else
2038 SEC_HWC_Log(HWC_LOG_DEBUG,
2039 "[%s] pm_alloc[%d] unmap fd=%d total_size=%d offset=0x%x",
2040 __func__, i, pm_alloc->fd, pm_alloc->total_size,
2041 pm_alloc->offset);
2042#endif
2043 close(pm_alloc->fd);
2044
2045 pm_alloc->fd = -1;
2046 pm_alloc->total_size = 0;
2047 pm_alloc->offset = 0;
2048 pm_alloc->virt_addr = 0;
2049 pm_alloc->phys_addr = 0;
2050 }
2051 }
2052
2053 if (0 <= pm->pmem_master_fd) {
2054 munmap(pm->pmem_master_base, pm->pmem_total_size);
2055 close(pm->pmem_master_fd);
2056 pm->pmem_master_fd = -1;
2057 }
2058
2059 pm->pmem_master_base = 0;
2060 pm->pmem_total_size = 0;
2061
2062 return 0;
2063}
2064
2065int checkPmem(sec_pmem_t *pm, unsigned int index, unsigned int requested_size)
2066{
2067 sec_pmem_alloc_t *pm_alloc = &(pm->sec_pmem_alloc[index]);
2068
2069 if (0 < pm_alloc->virt_addr &&
2070 requested_size <= (unsigned int)(pm_alloc->total_size))
2071 return 0;
2072
2073 pm_alloc->size = 0;
2074 return -1;
2075}
2076
2077#endif