Gitiles
Code Review Sign In
review.blissroms.org / platform_hardware_samsung / 86d0895f82ca01b07da6e0d1e5e37d26f5114333 / . / exynos5 / hal / libhwcomposer / SecHWCUtils.cpp
blob: 9a03ed299b28253a53a1c5b28b46822cc961497a [file] [log] [blame]
codeworkx62f02ba2012-05-20 12:00:36 +0200[diff] [blame]1/*
2 * Copyright (C) 2010 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17/*
18 *
19 * @author Rama, Meka(v.meka@samsung.com)
20 Sangwoo, Park(sw5771.park@samsung.com)
21 Jamie Oh (jung-min.oh@samsung.com)
22 * @date 2011-03-11
23 *
24 */
25
26#include "SecHWCUtils.h"
27
28#define V4L2_BUF_TYPE_OUTPUT V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
29#define V4L2_BUF_TYPE_CAPTURE V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
30#define EXYNOS4_ALIGN( value, base ) (((value) + ((base) - 1)) & ~((base) - 1))
31
32//#define CHECK_FPS
33#ifdef CHECK_FPS
34#include <sys/time.h>
35#include <unistd.h>
36#define CHK_FRAME_CNT 30
37
38void check_fps()
39{
40 static struct timeval tick, tick_old;
41 static int total = 0;
42 static int cnt = 0;
43 int FPS;
44 cnt++;
45 gettimeofday(&tick, NULL);
46 if (cnt > 10) {
47 if (tick.tv_sec > tick_old.tv_sec)
48 total += ((tick.tv_usec/1000) + (tick.tv_sec - tick_old.tv_sec)*1000 - (tick_old.tv_usec/1000));
49 else
50 total += ((tick.tv_usec - tick_old.tv_usec)/1000);
51
52 memcpy(&tick_old, &tick, sizeof(timeval));
53 if (cnt == (10 + CHK_FRAME_CNT)) {
54 FPS = 1000*CHK_FRAME_CNT/total;
55 LOGE("[FPS]:%d\n", FPS);
56 total = 0;
57 cnt = 10;
58 }
59 } else {
60 memcpy(&tick_old, &tick, sizeof(timeval));
61 total = 0;
62 }
63}
64#endif
65
66struct yuv_fmt_list yuv_list[] = {
67 { "V4L2_PIX_FMT_NV12", "YUV420/2P/LSB_CBCR", V4L2_PIX_FMT_NV12, 12, 2 },
68 { "V4L2_PIX_FMT_NV12T", "YUV420/2P/LSB_CBCR", V4L2_PIX_FMT_NV12T, 12, 2 },
69 { "V4L2_PIX_FMT_NV21", "YUV420/2P/LSB_CRCB", V4L2_PIX_FMT_NV21, 12, 2 },
70 { "V4L2_PIX_FMT_NV21X", "YUV420/2P/MSB_CBCR", V4L2_PIX_FMT_NV21X, 12, 2 },
71 { "V4L2_PIX_FMT_NV12X", "YUV420/2P/MSB_CRCB", V4L2_PIX_FMT_NV12X, 12, 2 },
72 { "V4L2_PIX_FMT_YUV420", "YUV420/3P", V4L2_PIX_FMT_YUV420, 12, 3 },
73 { "V4L2_PIX_FMT_YUV420M", "YUV420/3P", V4L2_PIX_FMT_YUV420M, 12, 3 },
74 { "V4L2_PIX_FMT_YVU420M", "YVU420/3P", V4L2_PIX_FMT_YVU420M, 12, 3 },
75 { "V4L2_PIX_FMT_NV12M", "YUV420/2P/LSB_CBCR", V4L2_PIX_FMT_NV12M, 12, 2 },
76 { "V4L2_PIX_FMT_YUYV", "YUV422/1P/YCBYCR", V4L2_PIX_FMT_YUYV, 16, 1 },
77 { "V4L2_PIX_FMT_YVYU", "YUV422/1P/YCRYCB", V4L2_PIX_FMT_YVYU, 16, 1 },
78 { "V4L2_PIX_FMT_UYVY", "YUV422/1P/CBYCRY", V4L2_PIX_FMT_UYVY, 16, 1 },
79 { "V4L2_PIX_FMT_VYUY", "YUV422/1P/CRYCBY", V4L2_PIX_FMT_VYUY, 16, 1 },
80 { "V4L2_PIX_FMT_UV12", "YUV422/2P/LSB_CBCR", V4L2_PIX_FMT_NV16, 16, 2 },
81 { "V4L2_PIX_FMT_UV21", "YUV422/2P/LSB_CRCB", V4L2_PIX_FMT_NV61, 16, 2 },
82 { "V4L2_PIX_FMT_UV12X", "YUV422/2P/MSB_CBCR", V4L2_PIX_FMT_NV16X, 16, 2 },
83 { "V4L2_PIX_FMT_UV21X", "YUV422/2P/MSB_CRCB", V4L2_PIX_FMT_NV61X, 16, 2 },
84 { "V4L2_PIX_FMT_YUV422P", "YUV422/3P", V4L2_PIX_FMT_YUV422P, 16, 3 },
85};
86
87int window_open(struct hwc_win_info_t *win, int id)
88{
89 int fd = 0;
90 char name[64];
91 int vsync = 1;
92 int real_id = id;
93
94 char const * const device_template = "/dev/graphics/fb%u";
95 // window & FB maping
96 // fb0 -> win-id : 2
97 // fb1 -> win-id : 1
98 // fb2 -> win-id : 0
99 // fb3 -> no device node
100 // fb4 -> no device node
101 // it is pre assumed that ...win0 or win1 is used here..
102
103 switch (id) {
104 case 0:
105 real_id = 2;
106 break;
107 case 1:
108 real_id = 1;
109 break;
110 default:
111 SEC_HWC_Log(HWC_LOG_ERROR, "%s::id(%d) is weird", __func__, id);
112 goto error;
113}
114
115 snprintf(name, 64, device_template, real_id);
116
117 win->fd = open(name, O_RDWR);
118 if (win->fd <= 0) {
119 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Failed to open window device (%s) : %s",
120 __func__, strerror(errno), name);
121 goto error;
122 }
123
124#ifdef ENABLE_FIMD_VSYNC
125 vsync = 1;
126 if (ioctl(win->fd, S3CFB_SET_VSYNC_INT, &vsync) < 0) {
127 SEC_HWC_Log(HWC_LOG_ERROR, "%s::S3CFB_SET_VSYNC_INT fail", __func__);
128 goto error;
129 }
130#endif
131
132 return 0;
133
134error:
135 if (0 < win->fd)
136 close(win->fd);
137 win->fd = 0;
138
139 return -1;
140}
141
142int window_close(struct hwc_win_info_t *win)
143{
144 int ret = 0;
145
146 if (0 < win->fd) {
147 ion_unmap((void *)win->addr[0], ALIGN(win->size * NUM_OF_WIN_BUF, PAGE_SIZE));
148 ion_free(win->ion_fd);
149
150#ifdef ENABLE_FIMD_VSYNC
151 /* Set using VSYNC Interrupt for FIMD_0 */
152 int vsync = 0;
153 if (ioctl(win->fd, S3CFB_SET_VSYNC_INT, &vsync) < 0)
154 SEC_HWC_Log(HWC_LOG_ERROR, "%s::S3CFB_SET_VSYNC_INT fail", __func__);
155#endif
156 ret = close(win->fd);
157 }
158 win->fd = 0;
159
160 return ret;
161}
162
163int window_set_pos(struct hwc_win_info_t *win)
164{
165 struct s3cfb_user_window window;
166
167 //before changing the screen configuration...powerdown the window
168 if (window_hide(win) != 0)
169 return -1;
170
171 SEC_HWC_Log(HWC_LOG_DEBUG, "%s:: x(%d), y(%d)",
172 __func__, win->rect_info.x, win->rect_info.y);
173
174 win->var_info.xres_virtual = (win->lcd_info.xres + 15) & ~ 15;
175 win->var_info.yres_virtual = win->lcd_info.yres * NUM_OF_WIN_BUF;
176 win->var_info.xres = win->rect_info.w;
177 win->var_info.yres = win->rect_info.h;
178 win->var_info.activate &= ~FB_ACTIVATE_MASK;
179 win->var_info.activate |= FB_ACTIVATE_FORCE;
180 if (ioctl(win->fd, FBIOPUT_VSCREENINFO, &(win->var_info)) < 0) {
181 SEC_HWC_Log(HWC_LOG_ERROR, "%s::FBIOPUT_VSCREENINFO(%d, %d) fail",
182 __func__, win->rect_info.w, win->rect_info.h);
183 return -1;
184 }
185
186 window.x = win->rect_info.x;
187 window.y = win->rect_info.y;
188 if (ioctl(win->fd, S3CFB_WIN_POSITION, &window) < 0) {
189 SEC_HWC_Log(HWC_LOG_ERROR, "%s::S3CFB_WIN_POSITION(%d, %d) fail",
190 __func__, window.x, window.y);
191 return -1;
192 }
193
194 return 0;
195}
196
197int window_get_info(struct hwc_win_info_t *win, int win_num)
198{
199 int temp_size = 0;
200
201 if (ioctl(win->fd, FBIOGET_FSCREENINFO, &win->fix_info) < 0) {
202 SEC_HWC_Log(HWC_LOG_ERROR, "FBIOGET_FSCREENINFO failed : %s",
203 strerror(errno));
204 goto error;
205 }
206
207 win->size = win->fix_info.line_length * win->var_info.yres;
208
209 struct s3c_fb_user_ion_client ion_handle;
210 void *ion_start_addr;
211 if (ioctl(win->fd, S3CFB_GET_ION_USER_HANDLE, &ion_handle) < 0) {
212 SEC_HWC_Log(HWC_LOG_ERROR, "Get fb ion client is failed\n");
213 return -1;
214 }
215
216 win->ion_fd = ion_handle.fd;
217 ion_start_addr = ion_map(win->ion_fd, ALIGN(win->size * NUM_OF_WIN_BUF, PAGE_SIZE), 0);
218
219 for (int j = 0; j < NUM_OF_WIN_BUF; j++) {
220 temp_size = win->size * j;
221 win->addr[j] = (uint32_t)ion_start_addr + temp_size;
222 SEC_HWC_Log(HWC_LOG_DEBUG, "%s::win-%d add[%d] %x ",
223 __func__, win_num, j, win->addr[j]);
224 }
225 return 0;
226
227error:
228 win->fix_info.smem_start = 0;
229
230 return -1;
231}
232
233int window_pan_display(struct hwc_win_info_t *win)
234{
235 struct fb_var_screeninfo *lcd_info = &(win->lcd_info);
236
237#ifdef ENABLE_FIMD_VSYNC
238 int pan_num = 0;
239 if (ioctl(win->fd, FBIO_WAITFORVSYNC, &pan_num) < 0)
240 SEC_HWC_Log(HWC_LOG_ERROR, "%s::FBIO_WAITFORVSYNC fail(%s)",
241 __func__, strerror(errno));
242#endif
243
244 lcd_info->yoffset = lcd_info->yres * win->buf_index;
245
246 if (ioctl(win->fd, FBIOPAN_DISPLAY, lcd_info) < 0) {
247 SEC_HWC_Log(HWC_LOG_ERROR, "%s::FBIOPAN_DISPLAY(%d / %d / %d) fail(%s)",
248 __func__,
249 lcd_info->yres,
250 win->buf_index, lcd_info->yres_virtual,
251 strerror(errno));
252 return -1;
253 }
254 return 0;
255}
256
257int window_show(struct hwc_win_info_t *win)
258{
259 if (win->power_state == 0) {
260 if (ioctl(win->fd, FBIOBLANK, FB_BLANK_UNBLANK) < 0) {
261 SEC_HWC_Log(HWC_LOG_ERROR, "%s::FBIOBLANK failed : (%d:%s)",
262 __func__, win->fd, strerror(errno));
263 return -1;
264 }
265 win->power_state = 1;
266 }
267 return 0;
268}
269
270int window_hide(struct hwc_win_info_t *win)
271{
272 if (win->power_state == 1) {
273 if (ioctl(win->fd, FBIOBLANK, FB_BLANK_POWERDOWN) < 0) {
274 SEC_HWC_Log(HWC_LOG_ERROR, "%s::FBIOBLANK failed : (%d:%s)",
275 __func__, win->fd, strerror(errno));
276 return -1;
277 }
278 win->power_state = 0;
279 }
280 return 0;
281}
282
283int window_get_global_lcd_info(int fd, struct fb_var_screeninfo *lcd_info)
284{
285 if (ioctl(fd, FBIOGET_VSCREENINFO, lcd_info) < 0) {
286 SEC_HWC_Log(HWC_LOG_ERROR, "FBIOGET_VSCREENINFO failed : %s",
287 strerror(errno));
288 return -1;
289 }
290
291 SEC_HWC_Log(HWC_LOG_DEBUG, "%s:: Default LCD x(%d),y(%d)",
292 __func__, lcd_info->xres, lcd_info->yres);
293 return 0;
294}
295
296int fimc_v4l2_set_src(int fd, s5p_fimc_img_info *src)
297{
298 struct v4l2_format fmt;
299 struct v4l2_cropcap cropcap;
300 struct v4l2_crop crop;
301 struct v4l2_requestbuffers req;
302
303 /* You MUST initialize structure for v4l2 */
304 memset(&fmt, 0, sizeof(fmt));
305 memset(&cropcap, 0, sizeof(cropcap));
306 memset(&crop, 0, sizeof(crop));
307 memset(&req, 0, sizeof(req));
308
309 /************** To set size & format for source image (DMA-INPUT) **************/
310 fmt.fmt.pix_mp.num_planes = src->planes;
311 fmt.fmt.pix_mp.width = src->full_width;
312 fmt.fmt.pix_mp.height = src->full_height;
313 fmt.fmt.pix_mp.pixelformat = src->color_space;
314 fmt.fmt.pix_mp.field = V4L2_FIELD_ANY;
315 fmt.type = V4L2_BUF_TYPE_OUTPUT;
316
317 SEC_HWC_Log(HWC_LOG_DEBUG,
318 "fimc_v4l2_set_src-VIDIOC_S_FMT, type(%d), field(%d), plane(%d)"
319 "pixelformat(0x%X), width(%d), height(%d)",
320 fmt.type, fmt.fmt.pix.field, fmt.fmt.pix_mp.num_planes,
321 fmt.fmt.pix_mp.pixelformat, fmt.fmt.pix_mp.width, fmt.fmt.pix_mp.height);
322
323 if (ioctl(fd, VIDIOC_S_FMT, &fmt) < 0) {
324 SEC_HWC_Log(HWC_LOG_ERROR, "%s::VIDIOC_S_FMT failed : errno=%d (%s)"
325 " : fd=%d\n", __func__, errno, strerror(errno), fd);
326 return -1;
327 }
328
329 /************** crop input size **************/
330 crop.type = V4L2_BUF_TYPE_OUTPUT;
331 crop.c.width = src->width;
332 crop.c.height = src->height;
333 crop.c.left = src->start_x;
334 crop.c.top = src->start_y;
335
336 SEC_HWC_Log(HWC_LOG_DEBUG,
337 "fimc_v4l2_set_src-VIDIOC_S_CROP, type(%d), XY(%d,%d), WH(%d,%d)",
338 crop.type, crop.c.left, crop.c.top, crop.c.width, crop.c.height);
339
340 if (ioctl(fd, VIDIOC_S_CROP, &crop) < 0) {
341 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Error in video VIDIOC_S_CROP :"
342 "crop.c.left : (%d), crop.c.top : (%d), crop.c.width : (%d), crop.c.height : (%d)",
343 __func__, crop.c.left, crop.c.top, crop.c.width, crop.c.height);
344 return -1;
345 }
346
347 /************** input buffer type **************/
348 req.count = 1;
349 req.memory = V4L2_MEMORY_USERPTR;
350 req.type = V4L2_BUF_TYPE_OUTPUT;
351
352 SEC_HWC_Log(HWC_LOG_DEBUG,
353 "fimc_v4l2_set_src-VIDIOC_REQBUFS, count(%d), type(%d), memory(%d)",
354 req.count, req.type, req.memory);
355
356 if (ioctl(fd, VIDIOC_REQBUFS, &req) < 0) {
357 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Error in VIDIOC_REQBUFS", __func__);
358 return -1;
359 }
360
361 return 0;
362}
363
364int fimc_v4l2_set_dst(int fd, s5p_fimc_img_info *dst,
365 int rotation, int hflip, int vflip, unsigned int addr)
366{
367 struct v4l2_format sFormat;
368 struct v4l2_control vc;
369 struct v4l2_framebuffer fbuf;
370 struct v4l2_crop crop;
371 struct v4l2_requestbuffers req;
372 int ret;
373
374 /* You MUST initialize structure for v4l2 */
375 memset(&sFormat, 0, sizeof(sFormat));
376 memset(&vc, 0, sizeof(vc));
377 memset(&fbuf, 0, sizeof(fbuf));
378 memset(&crop, 0, sizeof(crop));
379 memset(&req, 0, sizeof(req));
380
381 /************** set rotation configuration **************/
382 vc.id = V4L2_CID_ROTATE;
383 vc.value = rotation;
384
385 SEC_HWC_Log(HWC_LOG_DEBUG,
386 "fimc_v4l2_set_dst-V4L2_CID_ROTATE, rot(%d)",vc.value);
387
388 ret = ioctl(fd, VIDIOC_S_CTRL, &vc);
389 if (ret < 0) {
390 SEC_HWC_Log(HWC_LOG_ERROR,
391 "%s::Error in video VIDIOC_S_CTRL - rotation (%d)"
392 "vc.id : (%d), vc.value : (%d)", __func__, ret, vc.id, vc.value);
393 return -1;
394 }
395
396 /************** set hflip configuration **************/
397 vc.id = V4L2_CID_HFLIP;
398 vc.value = hflip;
399
400 SEC_HWC_Log(HWC_LOG_DEBUG,
401 "fimc_v4l2_set_dst-V4L2_CID_HFLIP, hflip(%d)",vc.value);
402
403 ret = ioctl(fd, VIDIOC_S_CTRL, &vc);
404 if (ret < 0) {
405 SEC_HWC_Log(HWC_LOG_ERROR,
406 "%s::Error in video VIDIOC_S_CTRL - hflip (%d)"
407 "vc.id : (%d), vc.value : (%d)", __func__, ret, vc.id, vc.value);
408 return -1;
409 }
410
411 /************** set vflip configuration **************/
412 vc.id = V4L2_CID_VFLIP;
413 vc.value = vflip;
414
415 SEC_HWC_Log(HWC_LOG_DEBUG,
416 "fimc_v4l2_set_dst-V4L2_CID_VFLIP, vflip(%d)",vc.value);
417
418 ret = ioctl(fd, VIDIOC_S_CTRL, &vc);
419 if (ret < 0) {
420 SEC_HWC_Log(HWC_LOG_ERROR,
421 "%s::Error in video VIDIOC_S_CTRL - vflip (%d)"
422 "vc.id : (%d), vc.value : (%d)", __func__, ret, vc.id, vc.value);
423 return -1;
424 }
425
426 /************** set destination **************/
427 sFormat.type = V4L2_BUF_TYPE_CAPTURE;
428 sFormat.fmt.pix_mp.width = dst->full_width;
429 sFormat.fmt.pix_mp.height = dst->full_height;
430 sFormat.fmt.pix_mp.pixelformat = dst->color_space;
431 sFormat.fmt.pix_mp.num_planes = dst->planes;
432 sFormat.fmt.pix.field = V4L2_FIELD_ANY;
433
434 SEC_HWC_Log(HWC_LOG_DEBUG,
435 "fimc_v4l2_set_dst-VIDIOC_S_FMT, type(%d), field(%d), plane(%d)"
436 "pixelformat(0x%X), width(%d), height(%d)",
437 sFormat.type, sFormat.fmt.pix.field, sFormat.fmt.pix_mp.num_planes,
438 sFormat.fmt.pix_mp.pixelformat, sFormat.fmt.pix_mp.width, sFormat.fmt.pix_mp.height);
439
440 ret = ioctl(fd, VIDIOC_S_FMT, &sFormat);
441 if (ret < 0) {
442 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Error in video VIDIOC_S_FMT (%d)", __func__, ret);
443 return -1;
444 }
445
446 /************** set destination window**************/
447 crop.type = V4L2_BUF_TYPE_CAPTURE;
448 crop.c.left = dst->start_x;
449 crop.c.top = dst->start_y;
450 crop.c.width = dst->width;
451 crop.c.height = dst->height;
452
453 SEC_HWC_Log(HWC_LOG_DEBUG,
454 "fimc_v4l2_set_dst-VIDIOC_S_CROP, type(%d), XY(%d,%d), WH(%d,%d)",
455 crop.type, crop.c.left, crop.c.top, crop.c.width, crop.c.height);
456
457 ret = ioctl(fd, VIDIOC_S_CROP, &crop);
458 if (ret < 0) {
459 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Error in video VIDIOC_S_CROP (%d)", __func__, ret);
460 return -1;
461 }
462
463 /************** input buffer type **************/
464 req.count = 1;
465 req.type = V4L2_BUF_TYPE_CAPTURE;
466 req.memory = V4L2_MEMORY_USERPTR;
467
468 SEC_HWC_Log(HWC_LOG_DEBUG,
469 "fimc_v4l2_set_dst-VIDIOC_REQBUFS, count(%d), type(%d), memory(%d)",
470 req.count, req.type, req.memory);
471
472 ret = ioctl (fd, VIDIOC_REQBUFS, &req);
473 if (ret < 0) {
474 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Error in VIDIOC_REQBUFS (%d)", __func__, ret);
475 return -1;
476 }
477
478 return 0;
479}
480
481int fimc_v4l2_stream_on(int fd, enum v4l2_buf_type type)
482{
483 SEC_HWC_Log(HWC_LOG_DEBUG,"fimc_v4l2_stream_on-VIDIOC_STREAMON, type(%d)",type);
484
485 if (-1 == ioctl(fd, VIDIOC_STREAMON, &type)) {
486 SEC_HWC_Log(HWC_LOG_ERROR, "Error in VIDIOC_STREAMON\n");
487 return -1;
488 }
489
490 return 0;
491}
492
493int fimc_v4l2_queue(int fd, struct fimc_buf *fimc_buf, enum v4l2_buf_type type, int index)
494{
495 struct v4l2_plane plane[3];
496 struct v4l2_buffer buf;
497 int i;
498 int ret;
499
500 buf.length = fimc_buf->planes;
501 buf.memory = V4L2_MEMORY_USERPTR;
502 buf.index = index;
503 buf.type = type;
504
505 if (buf.type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE ||
506 buf.type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
507 for (i = 0; i < buf.length; i++) {
508 plane[i].m.userptr = fimc_buf->base[i];
509 plane[i].length = fimc_buf->size[i];
510 }
511 }
512 buf.m.planes = plane;
513
514 SEC_HWC_Log(HWC_LOG_DEBUG,"fimc_v4l2_queue-VIDIOC_QBUF, type(%d),"
515 "length(%d), memory(%d), index(%d)",
516 buf.type, buf.length, buf.memory, buf.index);
517
518 ret = ioctl(fd, VIDIOC_QBUF, &buf);
519 if (0 > ret) {
520 SEC_HWC_Log(HWC_LOG_ERROR, "Error in VIDIOC_QBUF : (%d)", ret);
521 return -1;
522 }
523
524 return 0;
525}
526
527int fimc_v4l2_dequeue(int fd, struct fimc_buf *fimc_buf, enum v4l2_buf_type type)
528{
529 struct v4l2_buffer buf;
530 struct v4l2_plane plane[3];
531
532 buf.m.planes = plane;
533 buf.length = fimc_buf->planes;
534 buf.memory = V4L2_MEMORY_USERPTR;
535 buf.type = type;
536
537 if (-1 == ioctl(fd, VIDIOC_DQBUF, &buf)) {
538 SEC_HWC_Log(HWC_LOG_ERROR, "Error in VIDIOC_DQBUF\n");
539 return -1;
540 }
541
542 return buf.index;
543}
544
545int fimc_v4l2_stream_off(int fd, enum v4l2_buf_type type)
546{
547 SEC_HWC_Log(HWC_LOG_DEBUG,"fimc_v4l2_stream_off-VIDIOC_STREAMOFF, type(%d),",type);
548
549 if (-1 == ioctl(fd, VIDIOC_STREAMOFF, &type)) {
550 SEC_HWC_Log(HWC_LOG_ERROR, "Error in VIDIOC_STREAMOFF\n");
551 return -1;
552 }
553
554 return 0;
555}
556
557int fimc_v4l2_clr_buf(int fd, enum v4l2_buf_type type)
558{
559 struct v4l2_requestbuffers req;
560
561 req.count = 0;
562 req.memory = V4L2_MEMORY_USERPTR;
563 req.type = type;
564
565 SEC_HWC_Log(HWC_LOG_DEBUG,"fimc_v4l2_clr_buf-VIDIOC_REQBUFS,"
566 "count(%d), memory(%d), type(%d)",
567 req.count, req.memory, req.type);
568
569 if (ioctl(fd, VIDIOC_REQBUFS, &req) == -1) {
570 SEC_HWC_Log(HWC_LOG_ERROR, "Error in VIDIOC_REQBUFS");
571 }
572
573 return 0;
574}
575
576int fimc_v4l2_S_ctrl(int fd)
577{
578 struct v4l2_control vc;
579
580 vc.id = V4L2_CID_CACHEABLE;
581 vc.value = 1;
582
583 SEC_HWC_Log(HWC_LOG_DEBUG,"fimc_v4l2_S_ctrl-VIDIOC_S_CTRL,"
584 "id(%d), value(%d)",vc.id , vc.value);
585
586 if (ioctl(fd, VIDIOC_S_CTRL, &vc) < 0) {
587 SEC_HWC_Log(HWC_LOG_ERROR, "Error in VIDIOC_S_CTRL");
588 return -1;
589 }
590
591 return 0;
592}
593
594int fimc_handle_oneshot(int fd, struct fimc_buf *fimc_src_buf, struct fimc_buf *fimc_dst_buf)
595{
596#ifdef CHECK_FPS
597 check_fps();
598#endif
599
600 if (fimc_v4l2_queue(fd, fimc_src_buf, V4L2_BUF_TYPE_OUTPUT, 0) < 0) {
601 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : SRC v4l2_queue()");
602 return -1;
603 }
604
605 if (fimc_v4l2_queue(fd, fimc_dst_buf, V4L2_BUF_TYPE_CAPTURE, 0) < 0) {
606 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : DST v4l2_queue()");
607 return -2;
608 }
609
610 if (fimc_v4l2_stream_on(fd, V4L2_BUF_TYPE_OUTPUT) < 0) {
611 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : SRC v4l2_stream_on()");
612 return -3;
613 }
614
615 if (fimc_v4l2_stream_on(fd, V4L2_BUF_TYPE_CAPTURE) < 0) {
616 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : DST v4l2_stream_on()");
617 return -4;
618 }
619
620 if (fimc_v4l2_dequeue(fd, fimc_src_buf, V4L2_BUF_TYPE_OUTPUT) < 0) {
621 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : SRC v4l2_dequeue()");
622 return -6;
623 }
624
625 if (fimc_v4l2_dequeue(fd, fimc_dst_buf, V4L2_BUF_TYPE_CAPTURE) < 0) {
626 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : DST v4l2_dequeue()");
627 return -7;
628 }
629
630STREAM_OFF:
631 if (fimc_v4l2_stream_off(fd, V4L2_BUF_TYPE_OUTPUT) < 0) {
632 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : SRC v4l2_stream_off()");
633 return -8;
634 }
635
636 if (fimc_v4l2_stream_off(fd, V4L2_BUF_TYPE_CAPTURE) < 0) {
637 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : DST v4l2_stream_off()");
638 return -9;
639 }
640
641 if (fimc_v4l2_clr_buf(fd, V4L2_BUF_TYPE_OUTPUT) < 0) {
642 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : SRC v4l2_clr_buf()");
643 return -10;
644 }
645
646 if (fimc_v4l2_clr_buf(fd, V4L2_BUF_TYPE_CAPTURE)< 0) {
647 SEC_HWC_Log(HWC_LOG_ERROR, "Fail : DST v4l2_clr_buf()");
648 return -11;
649 }
650
651 return 0;
652}
653
654static int memcpy_rect(void *dst, void *src, int fullW, int fullH, int realW, int realH, int format)
655{
656 unsigned char *srcCb, *srcCr;
657 unsigned char *dstCb, *dstCr;
658 unsigned char *srcY, *dstY;
659 int srcCbOffset, srcCrOffset;
660 int dstCbOffset, dstFrameOffset, dstCrOffset;
661 int cbFullW, cbRealW, cbFullH, cbRealH;
662 int ySrcFW, ySrcFH, ySrcRW, ySrcRH;
663 int planes;
664 int i;
665
666 SEC_HWC_Log(HWC_LOG_DEBUG,
667 "++memcpy_rect()::"
668 "dst(0x%x),src(0x%x),f.w(%d),f.h(%d),r.w(%d),r.h(%d),format(0x%x)",
669 (unsigned int)dst, (unsigned int)src, fullW, fullH, realW, realH, format);
670
671// Set dst Y, Cb, Cr address for FIMC
672 {
673 cbFullW = fullW >> 1;
674 cbRealW = realW >> 1;
675 cbFullH = fullH >> 1;
676 cbRealH = realH >> 1;
677 dstFrameOffset = fullW * fullH;
678 dstCrOffset = cbFullW * cbFullH;
679 dstY = (unsigned char *)dst;
680 dstCb = (unsigned char *)dst + dstFrameOffset;
681 dstCr = (unsigned char *)dstCb + dstCrOffset;
682 }
683
684// Get src Y, Cb, Cr address for source buffer.
685// Each address is aligned by 16's multiple for GPU both width and height.
686 {
687 ySrcFW = fullW;
688 ySrcFH = fullH;
689 ySrcRW = realW;
690 ySrcRH = realH;
691 srcCbOffset = EXYNOS4_ALIGN(ySrcRW,16)* EXYNOS4_ALIGN(ySrcRH,16);
692 srcCrOffset = EXYNOS4_ALIGN(cbRealW,16)* EXYNOS4_ALIGN(cbRealH,16);
693 srcY = (unsigned char *)src;
694 srcCb = (unsigned char *)src + srcCbOffset;
695 srcCr = (unsigned char *)srcCb + srcCrOffset;
696 }
697 SEC_HWC_Log(HWC_LOG_DEBUG,
698 "--memcpy_rect()::\n"
699 "dstY(0x%x),dstCb(0x%x),dstCr(0x%x) \n"
700 "srcY(0x%x),srcCb(0x%x),srcCr(0x%x) \n"
701 "cbRealW(%d),cbRealH(%d)",
702 (unsigned int)dstY,(unsigned int)dstCb,(unsigned int)dstCr,
703 (unsigned int)srcY,(unsigned int)srcCb,(unsigned int)srcCr,
704 cbRealW, cbRealH);
705
706 if (format == HAL_PIXEL_FORMAT_YV12) { //YV12(Y,Cr,Cv)
707 planes = 3;
708//This is code for VE, deleted temporory by SSONG 2011.09.22
709// This will be enabled later.
710/*
711 //as defined in hardware.h, cb & cr full_width should be aligned to 16. ALIGN(y_stride/2, 16).
712 ////Alignment is hard coded to 16.
713 ////for example...check frameworks/media/libvideoeditor/lvpp/VideoEditorTools.cpp file for UV stride cal
714 cbSrcFW = (cbSrcFW + 15) & (~15);
715 srcCbOffset = ySrcFW * fullH;
716 srcCrOffset = srcCbOffset + ((cbSrcFW * fullH) >> 1);
717 srcY = (unsigned char *)src;
718 srcCb = (unsigned char *)src + srcCbOffset;
719 srcCr = (unsigned char *)src + srcCrOffset;
720*/
721 } else if ((format == HAL_PIXEL_FORMAT_YCbCr_420_P) ||
722 (format == HAL_PIXEL_FORMAT_CUSTOM_YCbCr_420_P_SBS_LR) ||
723 (format == HAL_PIXEL_FORMAT_CUSTOM_YCbCr_420_P_SBS_RL) ||
724 (format == HAL_PIXEL_FORMAT_CUSTOM_YCbCr_420_P_TB_LR) ||
725 (format == HAL_PIXEL_FORMAT_CUSTOM_YCbCr_420_P_TB_RL)) {
726 planes = 3;
727 } else if (format == HAL_PIXEL_FORMAT_YCbCr_420_SP || format == HAL_PIXEL_FORMAT_YCrCb_420_SP) {
728 planes = 2;
729 } else {
730 SEC_HWC_Log(HWC_LOG_ERROR, "use default memcpy instead of memcpy_rect");
731 return -1;
732 }
733//#define CHECK_PERF
734#ifdef CHECK_PERF
735 struct timeval start, end;
736 gettimeofday(&start, NULL);
737#endif
738 for (i = 0; i < realH; i++)
739 memcpy(dstY + fullW * i, srcY + ySrcFW * i, ySrcRW);
740 if (planes == 2) {
741 for (i = 0; i < cbRealH; i++)
742 memcpy(dstCb + ySrcFW * i, srcCb + ySrcFW * i, ySrcRW);
743 } else if (planes == 3) {
744 for (i = 0; i < cbRealH; i++)
745 memcpy(dstCb + cbFullW * i, srcCb + cbFullW * i, cbRealW);
746 for (i = 0; i < cbRealH; i++)
747 memcpy(dstCr + cbFullW * i, srcCr + cbFullW * i, cbRealW);
748 }
749#ifdef CHECK_PERF
750 gettimeofday(&end, NULL);
751 SEC_HWC_Log(HWC_LOG_ERROR, "[COPY]=%d,",(end.tv_sec - start.tv_sec)*1000+(end.tv_usec - start.tv_usec)/1000);
752#endif
753
754 return 0;
755}
756
757/*****************************************************************************/
758static int get_src_phys_addr(struct hwc_context_t *ctx,
759 sec_img *src_img, sec_rect *src_rect)
760{
761 s5p_fimc_t *fimc = &ctx->fimc;
762 struct s3c_mem_alloc *ptr_mem_alloc = &ctx->s3c_mem.mem_alloc[0];
763 struct s3c_mem_dma_param s3c_mem_dma;
764
765 unsigned int src_virt_addr = 0;
766 unsigned int src_phys_addr = 0;
767 unsigned int src_frame_size = 0;
768
769 // error check routine
770 if (0 == src_img->base) {
771 SEC_HWC_Log(HWC_LOG_ERROR, "%s invalid src image base\n", __func__);
772 return 0;
773 }
774
775 fimc->params.src.buf_addr_phy_rgb_y = src_img->base;
776 fimc->params.src.buf_addr_phy_cb = src_img->base + src_img->uoffset;
777 fimc->params.src.buf_addr_phy_cr = src_img->base + src_img->uoffset + src_img->voffset;
778 src_phys_addr = fimc->params.src.buf_addr_phy_rgb_y;
779
780 return src_phys_addr;
781}
782
783static int get_dst_phys_addr(struct hwc_context_t *ctx, sec_img *dst_img,
784 sec_rect *dst_rect, int *dst_memcpy_flag)
785{
786 unsigned int dst_phys_addr = 0;
787
788 dst_phys_addr = dst_img->base;
789
790 return dst_phys_addr;
791}
792
793static inline int rotateValueHAL2PP(unsigned char transform)
794{
795 int rotate_flag = transform & 0x7;
796
797 switch (rotate_flag) {
798 case HAL_TRANSFORM_ROT_90: return 90;
799 case HAL_TRANSFORM_ROT_180: return 180;
800 case HAL_TRANSFORM_ROT_270: return 270;
801 case HAL_TRANSFORM_FLIP_H | HAL_TRANSFORM_ROT_90: return 90;
802 case HAL_TRANSFORM_FLIP_V | HAL_TRANSFORM_ROT_90: return 90;
803 case HAL_TRANSFORM_FLIP_H: return 0;
804 case HAL_TRANSFORM_FLIP_V: return 0;
805 }
806 return 0;
807}
808
809static inline int hflipValueHAL2PP(unsigned char transform)
810{
811 int flip_flag = transform & 0x7;
812 switch (flip_flag) {
813 case HAL_TRANSFORM_FLIP_H:
814 case HAL_TRANSFORM_FLIP_H | HAL_TRANSFORM_ROT_90:
815 return 1;
816 case HAL_TRANSFORM_FLIP_V | HAL_TRANSFORM_ROT_90:
817 case HAL_TRANSFORM_ROT_90:
818 case HAL_TRANSFORM_ROT_180:
819 case HAL_TRANSFORM_ROT_270:
820 case HAL_TRANSFORM_FLIP_V:
821 break;
822 }
823 return 0;
824}
825
826static inline int vflipValueHAL2PP(unsigned char transform)
827{
828 int flip_flag = transform & 0x7;
829 switch (flip_flag) {
830 case HAL_TRANSFORM_FLIP_V:
831 case HAL_TRANSFORM_FLIP_V | HAL_TRANSFORM_ROT_90:
832 return 1;
833 case HAL_TRANSFORM_FLIP_H | HAL_TRANSFORM_ROT_90:
834 case HAL_TRANSFORM_ROT_90:
835 case HAL_TRANSFORM_ROT_180:
836 case HAL_TRANSFORM_ROT_270:
837 case HAL_TRANSFORM_FLIP_H:
838 break;
839 }
840 return 0;
841}
842
843static inline int multipleOf2(int number)
844{
845 if (number % 2 == 1)
846 return (number - 1);
847 else
848 return number;
849}
850
851static inline int multipleOf4(int number)
852{
853 int remain_number = number % 4;
854
855 if (remain_number != 0)
856 return (number - remain_number);
857 else
858 return number;
859}
860
861static inline int multipleOf8(int number)
862{
863 int remain_number = number % 8;
864
865 if (remain_number != 0)
866 return (number - remain_number);
867 else
868 return number;
869}
870
871static inline int multipleOf16(int number)
872{
873 int remain_number = number % 16;
874
875 if (remain_number != 0)
876 return (number - remain_number);
877 else
878 return number;
879}
880
881static inline int widthOfPP( int pp_color_format, int number)
882{
883 switch (pp_color_format) {
884 /* 422 1/2/3 plane */
885 case V4L2_PIX_FMT_YUYV:
886 case V4L2_PIX_FMT_UYVY:
887 case V4L2_PIX_FMT_NV61:
888 case V4L2_PIX_FMT_NV16:
889 case V4L2_PIX_FMT_YUV422P:
890
891 /* 420 2/3 plane */
892 case V4L2_PIX_FMT_NV21:
893 case V4L2_PIX_FMT_NV12:
894 case V4L2_PIX_FMT_NV12T:
895 case V4L2_PIX_FMT_YUV420:
896 return multipleOf2(number);
897
898 default :
899 return number;
900 }
901
902}
903
904static inline int heightOfPP(int pp_color_format, int number)
905{
906 switch (pp_color_format) {
907 case V4L2_PIX_FMT_NV21:
908 case V4L2_PIX_FMT_NV12:
909 case V4L2_PIX_FMT_NV12T:
910 case V4L2_PIX_FMT_YUV420:
911 return multipleOf2(number);
912
913 default :
914 return number;
915 break;
916 }
917 return number;
918}
919
920static unsigned int get_yuv_bpp(unsigned int fmt)
921{
922 int i, sel = -1;
923
924 for (i = 0; i < (int)(sizeof(yuv_list) / sizeof(struct yuv_fmt_list)); i++) {
925 if (yuv_list[i].fmt == fmt) {
926 sel = i;
927 break;
928 }
929 }
930
931 if (sel == -1)
932 return sel;
933 else
934 return yuv_list[sel].bpp;
935}
936
937static unsigned int get_yuv_planes(unsigned int fmt)
938{
939 int i, sel = -1;
940
941 for (i = 0; i < (int)(sizeof(yuv_list) / sizeof(struct yuv_fmt_list)); i++) {
942 if (yuv_list[i].fmt == fmt) {
943 sel = i;
944 break;
945 }
946 }
947
948 if (sel == -1)
949 return sel;
950 else
951 return yuv_list[sel].planes;
952}
953
954static int runFimcCore(struct hwc_context_t *ctx,
955 unsigned int src_phys_addr, sec_img *src_img, sec_rect *src_rect,
956 uint32_t src_color_space,
957 unsigned int dst_phys_addr, sec_img *dst_img, sec_rect *dst_rect,
958 uint32_t dst_color_space, int transform)
959{
960 s5p_fimc_t * fimc = &ctx->fimc;
961 s5p_fimc_params_t * params = &(fimc->params);
962
963 struct fimc_buf fimc_src_buf;
964 int src_bpp, src_planes;
965
966 struct fimc_buf fimc_dst_buf;
967 int dst_bpp, dst_planes;
968 unsigned int src_frame_size = 0;
969 unsigned int dst_frame_size = 0;
970 unsigned int frame_size = 0;
971
972 bool src_cbcr_order = true;
973 int rotate_value = rotateValueHAL2PP(transform);
974 int hflip = hflipValueHAL2PP(transform);
975 int vflip = vflipValueHAL2PP(transform);
976
977 /* 1. param(fimc config)->src information
978 * - src_img,src_rect => s_fw,s_fh,s_w,s_h,s_x,s_y
979 */
980 params->src.full_width = src_img->f_w;
981 params->src.full_height = src_img->f_h;
982 params->src.width = src_rect->w;
983 params->src.height = src_rect->h;
984 params->src.start_x = src_rect->x;
985 params->src.start_y = src_rect->y;
986 params->src.color_space = src_color_space;
987 params->src.buf_addr_phy_rgb_y = src_phys_addr;
988
989 params->dst.buf_addr_phy_rgb_y = dst_phys_addr;
990
991 /* check src minimum */
992 if (src_rect->w < 64 || src_rect->h < 32) {
993 SEC_HWC_Log(HWC_LOG_ERROR,
994 "%s src size is not supported by fimc : f_w=%d f_h=%d "
995 "x=%d y=%d w=%d h=%d (ow=%d oh=%d) format=0x%x", __func__,
996 params->src.full_width, params->src.full_height,
997 params->src.start_x, params->src.start_y,
998 params->src.width, params->src.height,
999 src_rect->w, src_rect->h,
1000 params->src.color_space);
1001 return -1;
1002 }
1003
1004 params->dst.full_width = dst_img->f_w;
1005 params->dst.full_height = dst_img->f_h;
1006 params->dst.start_x = dst_rect->x;
1007 params->dst.start_y = dst_rect->y;
1008 params->dst.width = widthOfPP(dst_color_space, dst_rect->w);
1009 params->dst.height = heightOfPP(dst_color_space, dst_rect->h);
1010 params->dst.color_space = dst_color_space;
1011
1012 SEC_HWC_Log(HWC_LOG_DEBUG,
1013 "runFimcCore()::"
1014 "SRC f.w(%d),f.h(%d),x(%d),y(%d),w(%d),h(%d)=>"
1015 "DST f.w(%d),f.h(%d),x(%d),y(%d),w(%d),h(%d)",
1016 params->src.full_width, params->src.full_height,
1017 params->src.start_x, params->src.start_y,
1018 params->src.width, params->src.height,
1019 params->dst.full_width, params->dst.full_height,
1020 params->dst.start_x, params->dst.start_y,
1021 params->dst.width, params->dst.height);
1022
1023 /* check dst minimum */
1024#if (GSC_VERSION == GSC_EVT0)
1025 if (dst_rect->w < 64 || dst_rect->h < 32) {
1026#else
1027 if (dst_rect->w < 32 || dst_rect->h < 8) {
1028#endif
1029
1030 SEC_HWC_Log(HWC_LOG_ERROR,
1031 "%s dst size is not supported by fimc : f_w=%d f_h=%d "
1032 "x=%d y=%d w=%d h=%d (ow=%d oh=%d) format=0x%x", __func__,
1033 params->dst.full_width, params->dst.full_height,
1034 params->dst.start_x, params->dst.start_y,
1035 params->dst.width, params->dst.height,
1036 dst_rect->w, dst_rect->h, params->dst.color_space);
1037 return -1;
1038 }
1039
1040 /* 2. Set configuration related to destination (DMA-OUT)
1041 * - set input format & size
1042 * - crop input size
1043 * - set input buffer
1044 * - set buffer type (V4L2_MEMORY_USERPTR)
1045 */
1046 switch (dst_img->format) {
1047 case HAL_PIXEL_FORMAT_RGBA_8888:
1048 case HAL_PIXEL_FORMAT_RGBX_8888:
1049 case HAL_PIXEL_FORMAT_RGB_888:
1050 case HAL_PIXEL_FORMAT_BGRA_8888:
1051 dst_planes = 1;
1052 dst_bpp = 32;
1053 break;
1054
1055 case HAL_PIXEL_FORMAT_RGB_565:
1056 case HAL_PIXEL_FORMAT_RGBA_5551:
1057 case HAL_PIXEL_FORMAT_RGBA_4444:
1058 dst_planes = 1;
1059 dst_bpp = 16;
1060 break;
1061 }
1062
1063 dst_frame_size = params->dst.width * params->dst.height ;
1064 params->dst.planes = dst_planes;
1065
1066 if (dst_planes == 1) {
1067 fimc_dst_buf.base[0] = params->dst.buf_addr_phy_rgb_y;
1068 if (dst_bpp == 32)
1069 fimc_dst_buf.size[0] = dst_frame_size * 4;
1070 else if (dst_bpp == 16)
1071 fimc_dst_buf.size[0] = dst_frame_size * 2;
1072 }
1073
1074 if (fimc_v4l2_set_dst(fimc->dev_fd, &params->dst, rotate_value, hflip, vflip, dst_phys_addr) < 0) {
1075 SEC_HWC_Log(HWC_LOG_ERROR, "fimc_v4l2_set_dst is failed\n");
1076 return -1;
1077 }
1078
1079 /* 3. Set input dma address (Y/RGB, Cb, Cr)
1080 * set source frame size
1081 */
1082 src_frame_size = params->src.full_width * params->src.full_height;
1083 fimc_src_buf.size[0] = src_frame_size;
1084 fimc_src_buf.size[1] = src_frame_size >> 2;
1085 fimc_src_buf.size[2] = src_frame_size >> 2;
1086
1087 SEC_HWC_Log(HWC_LOG_DEBUG,
1088 "runFimcCore - Y_length=%d, U_length=%d, V_length=%d\n",
1089 fimc_src_buf.size[0], fimc_src_buf.size[1],fimc_src_buf.size[2]);
1090
1091 /* set source Y image */
1092 fimc_src_buf.base[0] = params->src.buf_addr_phy_rgb_y;
1093 /* set source Cb,Cr images for 2 or 3 planes */
1094 src_bpp = get_yuv_bpp(src_color_space);
1095 src_planes = get_yuv_planes(src_color_space);
1096 if (2 == src_planes) { /* 2 planes */
1097 frame_size = params->src.full_width * params->src.full_height;
1098 params->src.buf_addr_phy_cb =
1099 params->src.buf_addr_phy_rgb_y + frame_size;
1100 /* CbCr */
1101 fimc_src_buf.base[1] = params->src.buf_addr_phy_cb;
1102 } else if (3 == src_planes) { /* 3 planes */
1103 frame_size = params->src.full_width * params->src.full_height;
1104 params->src.buf_addr_phy_cb =
1105 params->src.buf_addr_phy_rgb_y + frame_size;
1106 if (12 == src_bpp)
1107 params->src.buf_addr_phy_cr =
1108 params->src.buf_addr_phy_cb + (frame_size >> 2);
1109 else
1110 params->src.buf_addr_phy_cr =
1111 params->src.buf_addr_phy_cb + (frame_size >> 1);
1112 /* Cb, Cr */
1113 if (src_cbcr_order == true) {
1114 fimc_src_buf.base[1] = params->src.buf_addr_phy_cb;
1115 fimc_src_buf.base[2] = params->src.buf_addr_phy_cr;
1116 }
1117 else {
1118 fimc_src_buf.base[2] = params->src.buf_addr_phy_cb;
1119 fimc_src_buf.base[1] = params->src.buf_addr_phy_cr;
1120 }
1121 }
1122
1123 SEC_HWC_Log(HWC_LOG_DEBUG,
1124 "runFimcCore - Y=0x%X, U=0x%X, V=0x%X\n",
1125 fimc_src_buf.base[0], fimc_src_buf.base[1],fimc_src_buf.base[2]);
1126
1127 int ret = 0;
1128 params->src.planes = src_planes;
1129
1130 /* 4. Set configuration related to source (DMA-INPUT)
1131 * - set input format & size
1132 * - crop input size
1133 * - set input buffer
1134 * - set buffer type (V4L2_MEMORY_USERPTR)
1135 */
1136 if (fimc_v4l2_set_src(fimc->dev_fd, &params->src) < 0) {
1137 SEC_HWC_Log(HWC_LOG_ERROR, "fimc_v4l2_set_src is failed\n");
1138 return -1;
1139 }
1140
1141 fimc_src_buf.planes = src_planes;
1142 fimc_dst_buf.planes = dst_planes;
1143
1144 /* 5. Run FIMC
1145 * - stream on => queue => dequeue => stream off => clear buf
1146 */
1147 ret = fimc_handle_oneshot(fimc->dev_fd, &fimc_src_buf, &fimc_dst_buf);
1148
1149 if (ret < 0) {
1150 SEC_HWC_Log(HWC_LOG_ERROR,"fimc_handle_oneshot = %d\n",ret);
1151 if (ret == -2) {
1152 fimc_v4l2_clr_buf(fimc->dev_fd, V4L2_BUF_TYPE_OUTPUT);
1153 } else if (ret == -3) {
1154 fimc_v4l2_clr_buf(fimc->dev_fd, V4L2_BUF_TYPE_OUTPUT);
1155 fimc_v4l2_clr_buf(fimc->dev_fd, V4L2_BUF_TYPE_CAPTURE);
1156 }
1157 return ret;
1158 }
1159
1160 return 0;
1161}
1162
1163#ifdef SUB_TITLES_HWC
1164int createG2d(sec_g2d_t *g2d)
1165{
1166 g2d->dev_fd = open(SEC_G2D_DEV_NAME, O_RDWR);
1167
1168 if (g2d->dev_fd <= 0) {
1169 SEC_HWC_Log(HWC_LOG_ERROR, "%s::G2d open error (%d)", __func__, errno);
1170 goto err;
1171 }
1172
1173 return 0;
1174err:
1175 if (0 < g2d->dev_fd)
1176 close(g2d->dev_fd);
1177 g2d->dev_fd =0;
1178
1179 return -1;
1180}
1181
1182int destroyG2d(sec_g2d_t *g2d)
1183{
1184 // close
1185 if (0 < g2d->dev_fd)
1186 close(g2d->dev_fd);
1187 g2d->dev_fd = 0;
1188
1189 return 0;
1190}
1191#endif
1192
1193int createVideoDev(s5p_fimc_t *fimc)
1194{
1195 struct v4l2_capability cap;
1196 struct v4l2_format fmt;
1197 struct v4l2_control vc;
1198
1199 // open device file
1200 if (fimc->dev_fd <= 0)
1201 fimc->dev_fd = open(PP_DEVICE_DEV_NAME, O_RDWR);
1202
1203 if (fimc->dev_fd <= 0) {
1204 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Post processor open error (%d)",
1205 __func__, errno);
1206 goto err;
1207 }
1208
1209 /* Initial debug log level for video driver.
1210 User can use command below to change log level.
1211 # echo 7 > /sys/module/gsc/parameters/gsc_dbg
1212 # echo 8 > /proc/sys/kernel/printk
1213 Each number for gsc_dgb means,
1214 3: error
1215 4: waring
1216 6: info
1217 7: debug
1218 */
1219 system("echo 3 > /sys/module/gsc/parameters/gsc_dbg");
1220
1221 // check capability
1222 if (ioctl(fimc->dev_fd, VIDIOC_QUERYCAP, &cap) < 0) {
1223 SEC_HWC_Log(HWC_LOG_ERROR, "VIDIOC_QUERYCAP failed");
1224 goto err;
1225 }
1226
1227 if (!(cap.capabilities & V4L2_CAP_STREAMING)) {
1228 SEC_HWC_Log(HWC_LOG_ERROR, "%d has no streaming support", fimc->dev_fd);
1229 goto err;
1230 }
1231
1232 if (!(cap.capabilities & V4L2_CAP_VIDEO_OUTPUT)) {
1233 SEC_HWC_Log(HWC_LOG_ERROR, "%d is no video output", fimc->dev_fd);
1234 goto err;
1235 }
1236
1237 /*
1238 * malloc fimc_outinfo structure
1239 */
1240 fmt.type = V4L2_BUF_TYPE_OUTPUT;
1241 if (ioctl(fimc->dev_fd, VIDIOC_G_FMT, &fmt) < 0) {
1242 SEC_HWC_Log(HWC_LOG_ERROR, "%s::Error in video VIDIOC_G_FMT", __func__);
1243 goto err;
1244 }
1245
1246 return 0;
1247
1248err:
1249 if (0 < fimc->dev_fd)
1250 close(fimc->dev_fd);
1251 fimc->dev_fd =0;
1252
1253 return -1;
1254}
1255
1256int destroyVideoDev(s5p_fimc_t *fimc)
1257{
1258 if (fimc->out_buf.virt_addr != NULL) {
1259 fimc->out_buf.virt_addr = NULL;
1260 fimc->out_buf.length = 0;
1261 }
1262
1263 // close
1264 if (0 < fimc->dev_fd)
1265 close(fimc->dev_fd);
1266 fimc->dev_fd = 0;
1267
1268 return 0;
1269}
1270
1271int runFimc(struct hwc_context_t *ctx,
1272 struct sec_img *src_img, struct sec_rect *src_rect,
1273 struct sec_img *dst_img, struct sec_rect *dst_rect,
1274 uint32_t transform)
1275{
1276 s5p_fimc_t * fimc = &ctx->fimc;
1277
1278 unsigned int src_phys_addr = 0;
1279 unsigned int dst_phys_addr = 0;
1280 int rotate_value = 0;
1281 int flag_force_memcpy = 0;
1282 int32_t src_color_space;
1283 int32_t dst_color_space;
1284
1285 /* 1. source address and size */
1286 src_phys_addr = get_src_phys_addr(ctx, src_img, src_rect);
1287 if (0 == src_phys_addr)
1288 return -1;
1289
1290 /* 2. destination address and size */
1291 dst_phys_addr = get_dst_phys_addr(ctx, dst_img, dst_rect, &flag_force_memcpy);
1292 if (0 == dst_phys_addr)
1293 return -2;
1294
1295 /* 3. check whether fimc supports the src format */
1296 src_color_space = HAL_PIXEL_FORMAT_2_V4L2_PIX(src_img->format);
1297 if (0 > src_color_space)
1298 return -3;
1299 dst_color_space = HAL_PIXEL_FORMAT_2_V4L2_PIX(dst_img->format);
1300 if (0 > dst_color_space)
1301 return -4;
1302
1303 /* 4. FIMC: src_rect of src_img => dst_rect of dst_img */
1304 if (runFimcCore(ctx, src_phys_addr, src_img, src_rect,
1305 (uint32_t)src_color_space, dst_phys_addr, dst_img, dst_rect,
1306 (uint32_t)dst_color_space, transform) < 0)
1307 return -5;
1308
1309 return 0;
1310}
1311
1312#ifdef SUB_TITLES_HWC
1313static int get_g2d_src_phys_addr(struct hwc_context_t *ctx, g2d_rect *src_rect)
1314{
1315 sec_g2d_t *g2d = &ctx->g2d;
1316 struct s3c_mem_alloc *ptr_mem_alloc = &ctx->s3c_mem.mem_alloc[0];
1317#ifdef USE_HW_PMEM
1318 sec_pmem_alloc_t *pm_alloc = &ctx->sec_pmem.sec_pmem_alloc[0];
1319#endif
1320
1321 unsigned int src_virt_addr = 0;
1322 unsigned int src_phys_addr = 0;
1323 unsigned int src_frame_size = 0;
1324
1325 struct pmem_region region;
1326
1327 // error check routine
1328 if (0 == src_rect->virt_addr) {
1329 SEC_HWC_Log(HWC_LOG_ERROR, "%s invalid src address\n", __func__);
1330 return 0;
1331 }
1332
1333 src_frame_size = FRAME_SIZE(src_rect->color_format,
1334 src_rect->full_w, src_rect->full_h);
1335 if (src_frame_size == 0) {
1336 SEC_HWC_Log(HWC_LOG_ERROR, "%s::FRAME_SIZE fail", __func__);
1337 return 0;
1338 }
1339
1340#ifdef USE_HW_PMEM
1341 if (0 <= checkPmem(&ctx->sec_pmem, 0, src_frame_size)) {
1342 src_virt_addr = pm_alloc->virt_addr;
1343 src_phys_addr = pm_alloc->phys_addr;
1344 pm_alloc->size = src_frame_size;
1345 } else
1346#endif
1347 if (0 <= checkMem(&ctx->s3c_mem, 0, src_frame_size)) {
1348 src_virt_addr = ptr_mem_alloc->vir_addr;
1349 src_phys_addr = ptr_mem_alloc->phy_addr;
1350 ptr_mem_alloc->size = src_frame_size;
1351 } else {
1352 SEC_HWC_Log(HWC_LOG_ERROR, "%s::check_mem fail", __func__);
1353 return 0;
1354 }
1355 memcpy((void *)src_virt_addr, (void*)((unsigned int)src_rect->virt_addr), src_frame_size);
1356
1357 return src_phys_addr;
1358}
1359
1360int get_HAL_2_G2D_FORMAT(int format)
1361{
1362 switch (format) {
1363 case HAL_PIXEL_FORMAT_RGBA_8888: return G2D_ABGR_8888;
1364 case HAL_PIXEL_FORMAT_RGBX_8888: return G2D_XBGR_8888;
1365 case HAL_PIXEL_FORMAT_BGRA_8888: return G2D_ARGB_8888;
1366 case HAL_PIXEL_FORMAT_RGB_888: return G2D_PACKED_BGR_888;
1367 case HAL_PIXEL_FORMAT_RGB_565: return G2D_RGB_565;
1368 case HAL_PIXEL_FORMAT_RGBA_5551: return G2D_RGBA_5551;
1369 case HAL_PIXEL_FORMAT_RGBA_4444: return G2D_RGBA_4444;
1370 default:
1371 return -1;
1372 }
1373}
1374
1375static inline int rotateValueHAL2G2D(unsigned char transform)
1376{
1377 int rotate_flag = transform & 0x7;
1378
1379 switch (rotate_flag) {
1380 case HAL_TRANSFORM_ROT_90: return G2D_ROT_90;
1381 case HAL_TRANSFORM_ROT_180: return G2D_ROT_180;
1382 case HAL_TRANSFORM_ROT_270: return G2D_ROT_270;
1383 default:
1384 return G2D_ROT_0;
1385 }
1386}
1387
1388int runG2d(struct hwc_context_t *ctx, g2d_rect *src_rect, g2d_rect *dst_rect,
1389 uint32_t transform)
1390{
1391 sec_g2d_t * g2d = &ctx->g2d;
1392 g2d_flag flag = {G2D_ROT_0, G2D_ALPHA_BLENDING_OPAQUE, 0, 0, 0, 0, 0, 0};
1393 int rotate_value = 0;
1394
1395 // 1 : source address and size
1396 src_rect->phys_addr = get_g2d_src_phys_addr(ctx, src_rect);
1397 if (0 == src_rect->phys_addr)
1398 return -1;
1399
1400 // 2 : destination address and size
1401 if (0 == dst_rect->phys_addr)
1402 return -2;
1403
1404 // check whether g2d supports the src format
1405 src_rect->color_format = get_HAL_2_G2D_FORMAT(src_rect->color_format);
1406 if (0 > src_rect->color_format)
1407 return -3;
1408
1409 dst_rect->color_format = get_HAL_2_G2D_FORMAT(dst_rect->color_format);
1410 if (0 > dst_rect->color_format)
1411 return -4;
1412
1413 flag.rotate_val = rotateValueHAL2G2D(transform);
1414
1415 // scale and rotate and alpha with FIMG
1416 if(stretchSecFimg(src_rect, dst_rect, &flag) < 0)
1417 return -5;
1418
1419 return 0;
1420}
1421#endif
1422
1423int createMem(struct s3c_mem_t *mem, unsigned int index, unsigned int size)
1424{
1425 struct s3c_mem_alloc *ptr_mem_alloc;
1426 struct s3c_mem_alloc mem_alloc_info;
1427
1428 if (index >= NUM_OF_MEM_OBJ) {
1429 SEC_HWC_Log(HWC_LOG_ERROR, "%s::invalid index (%d >= %d)",
1430 __func__, index, NUM_OF_MEM_OBJ);
1431 goto err;
1432 }
1433
1434 ptr_mem_alloc = &mem->mem_alloc[index];
1435
1436 if (mem->fd <= 0) {
1437 mem->fd = open(S3C_MEM_DEV_NAME, O_RDWR);
1438 if (mem->fd <= 0) {
1439 SEC_HWC_Log(HWC_LOG_ERROR, "%s::open(%s) fail(%s)",
1440 __func__, S3C_MEM_DEV_NAME, strerror(errno));
1441 goto err;
1442 }
1443 }
1444
1445 // kcoolsw : what the hell of this line??
1446 if (0 == size)
1447 return 0;
1448
1449 mem_alloc_info.size = size;
1450
1451 if (ioctl(mem->fd, S3C_MEM_CACHEABLE_ALLOC, &mem_alloc_info) < 0) {
1452 SEC_HWC_Log(HWC_LOG_ERROR, "%s::S3C_MEM_ALLOC(size : %d) fail",
1453 __func__, mem_alloc_info.size);
1454 goto err;
1455 }
1456
1457 ptr_mem_alloc->phy_addr = mem_alloc_info.phy_addr;
1458 ptr_mem_alloc->vir_addr = mem_alloc_info.vir_addr;
1459 ptr_mem_alloc->size = mem_alloc_info.size;
1460
1461 return 0;
1462
1463err:
1464 if (0 < mem->fd)
1465 close(mem->fd);
1466 mem->fd = 0;
1467
1468 return 0;
1469}
1470
1471int destroyMem(struct s3c_mem_t *mem)
1472{
1473 int i;
1474 struct s3c_mem_alloc *ptr_mem_alloc;
1475
1476 if (mem->fd <= 0) {
1477 SEC_HWC_Log(HWC_LOG_ERROR, "%s::invalied fd(%d) fail", __func__, mem->fd);
1478 return -1;
1479 }
1480
1481 for (i = 0; i < NUM_OF_MEM_OBJ; i++) {
1482 ptr_mem_alloc = &mem->mem_alloc[i];
1483
1484 if (0 != ptr_mem_alloc->vir_addr) {
1485 if (ioctl(mem->fd, S3C_MEM_FREE, ptr_mem_alloc) < 0) {
1486 SEC_HWC_Log(HWC_LOG_ERROR, "%s::S3C_MEM_FREE fail", __func__);
1487 return -1;
1488 }
1489
1490 ptr_mem_alloc->phy_addr = 0;
1491 ptr_mem_alloc->vir_addr = 0;
1492 ptr_mem_alloc->size = 0;
1493 }
1494 }
1495
1496 close(mem->fd);
1497 mem->fd = 0;
1498
1499 return 0;
1500}
1501
1502int checkMem(struct s3c_mem_t *mem, unsigned int index, unsigned int size)
1503{
1504 int ret;
1505 struct s3c_mem_alloc *ptr_mem_alloc;
1506 struct s3c_mem_alloc mem_alloc_info;
1507
1508 if (index >= NUM_OF_MEM_OBJ) {
1509 SEC_HWC_Log(HWC_LOG_ERROR, "%s::invalid index (%d >= %d)", __func__,
1510 index, NUM_OF_MEM_OBJ);
1511 return -1;
1512 }
1513
1514 if (mem->fd <= 0) {
1515 ret = createMem(mem, index, size);
1516 return ret;
1517 }
1518
1519 ptr_mem_alloc = &mem->mem_alloc[index];
1520
1521 if (ptr_mem_alloc->size < (int)size) {
1522 if (0 < ptr_mem_alloc->size) {
1523 // free allocated mem
1524 if (ioctl(mem->fd, S3C_MEM_FREE, ptr_mem_alloc) < 0) {
1525 SEC_HWC_Log(HWC_LOG_ERROR, "%s::S3C_MEM_FREE fail", __func__);
1526 return -1;
1527 }
1528 }
1529
1530 // allocate mem with requested size
1531 mem_alloc_info.size = size;
1532 if (ioctl(mem->fd, S3C_MEM_CACHEABLE_ALLOC, &mem_alloc_info) < 0) {
1533 SEC_HWC_Log(HWC_LOG_ERROR, "%s::S3C_MEM_ALLOC(size : %d) fail",
1534 __func__, mem_alloc_info.size);
1535 return -1;
1536 }
1537
1538 ptr_mem_alloc->phy_addr = mem_alloc_info.phy_addr;
1539 ptr_mem_alloc->vir_addr = mem_alloc_info.vir_addr;
1540 ptr_mem_alloc->size = mem_alloc_info.size;
1541 }
1542
1543 return 0;
1544}
1545
1546#ifdef USE_HW_PMEM
1547int createPmem(sec_pmem_t *pm, unsigned int buf_size)
1548{
1549 int master_fd, err = 0, i;
1550 void *base;
1551 unsigned int phys_base;
1552 size_t size, sub_size[NUM_OF_MEM_OBJ];
1553 struct pmem_region region;
1554
1555 master_fd = open(PMEM_DEVICE_DEV_NAME, O_RDWR, 0);
1556 if (master_fd < 0) {
1557 pm->pmem_master_fd = -1;
1558 if (EACCES == errno) {
1559 return 0;
1560 } else {
1561 SEC_HWC_Log(HWC_LOG_ERROR, "%s::open(%s) fail(%s)",
1562 __func__, PMEM_DEVICE_DEV_NAME, strerror(errno));
1563 return -errno;
1564 }
1565 }
1566
1567 if (ioctl(master_fd, PMEM_GET_TOTAL_SIZE, &region) < 0) {
1568 SEC_HWC_Log(HWC_LOG_ERROR, "PMEM_GET_TOTAL_SIZE failed, default mode");
1569 size = 8<<20; // 8 MiB
1570 } else {
1571 size = region.len;
1572 }
1573
1574 base = mmap(0, size, PROT_READ|PROT_WRITE, MAP_SHARED, master_fd, 0);
1575 if (base == MAP_FAILED) {
1576 SEC_HWC_Log(HWC_LOG_ERROR, "[%s] mmap failed : %d (%s)", __func__,
1577 errno, strerror(errno));
1578 base = 0;
1579 close(master_fd);
1580 master_fd = -1;
1581 return -errno;
1582 }
1583
1584 if (ioctl(master_fd, PMEM_GET_PHYS, &region) < 0) {
1585 SEC_HWC_Log(HWC_LOG_ERROR, "PMEM_GET_PHYS failed, limp mode");
1586 region.offset = 0;
1587 }
1588
1589 pm->pmem_master_fd = master_fd;
1590 pm->pmem_master_base = base;
1591 pm->pmem_total_size = size;
1592 //pm->pmem_master_phys_base = region.offset;
1593 phys_base = region.offset;
1594
1595 // sec_pmem_alloc[0] for temporary buffer for source
1596 sub_size[0] = buf_size;
1597 sub_size[0] = roundUpToPageSize(sub_size[0]);
1598
1599 for (i = 0; i < NUM_OF_MEM_OBJ; i++) {
1600 sec_pmem_alloc_t *pm_alloc = &(pm->sec_pmem_alloc[i]);
1601 int fd, ret;
1602 int offset = i ? sub_size[i-1] : 0;
1603 struct pmem_region sub = { offset, sub_size[i] };
1604
1605 // create the "sub-heap"
1606 if (0 > (fd = open(PMEM_DEVICE_DEV_NAME, O_RDWR, 0))) {
1607 SEC_HWC_Log(HWC_LOG_ERROR,
1608 "[%s][index=%d] open failed (%dL) : %d (%s)",
1609 __func__, i, __LINE__, errno, strerror(errno));
1610 return -errno;
1611 }
1612
1613 // connect to it
1614 if (0 != (ret = ioctl(fd, PMEM_CONNECT, pm->pmem_master_fd))) {
1615 SEC_HWC_Log(HWC_LOG_ERROR,
1616 "[%s][index=%d] ioctl(PMEM_CONNECT) failed : %d (%s)",
1617 __func__, i, errno, strerror(errno));
1618 close(fd);
1619 return -errno;
1620 }
1621
1622 // make it available to the client process
1623 if (0 != (ret = ioctl(fd, PMEM_MAP, &sub))) {
1624 SEC_HWC_Log(HWC_LOG_ERROR,
1625 "[%s][index=%d] ioctl(PMEM_MAP) failed : %d (%s)",
1626 __func__, i, errno, strerror(errno));
1627 close(fd);
1628 return -errno;
1629 }
1630
1631 pm_alloc->fd = fd;
1632 pm_alloc->total_size = sub_size[i];
1633 pm_alloc->offset = offset;
1634 pm_alloc->virt_addr = (unsigned int)base + (unsigned int)offset;
1635 pm_alloc->phys_addr = (unsigned int)phys_base + (unsigned int)offset;
1636
1637#if defined (PMEM_DEBUG)
1638 SEC_HWC_Log(HWC_LOG_DEBUG, "[%s] pm_alloc[%d] fd=%d total_size=%d "
1639 "offset=0x%x virt_addr=0x%x phys_addr=0x%x",
1640 __func__, i, pm_alloc->fd, pm_alloc->total_size,
1641 pm_alloc->offset, pm_alloc->virt_addr, pm_alloc->phys_addr);
1642#endif
1643 }
1644
1645 return err;
1646}
1647
1648int destroyPmem(sec_pmem_t *pm)
1649{
1650 int i, err;
1651
1652 for (i=0; i<NUM_OF_MEM_OBJ; i++) {
1653 sec_pmem_alloc_t *pm_alloc = &(pm->sec_pmem_alloc[i]);
1654
1655 if (0 <= pm_alloc->fd) {
1656 struct pmem_region sub = { pm_alloc->offset, pm_alloc->total_size };
1657
1658 if (0 > (err = ioctl(pm_alloc->fd, PMEM_UNMAP, &sub)))
1659 SEC_HWC_Log(HWC_LOG_ERROR,
1660 "[%s][index=%d] ioctl(PMEM_UNMAP) failed : %d (%s)",
1661 __func__, i, errno, strerror(errno));
1662#if defined (PMEM_DEBUG)
1663 else
1664 SEC_HWC_Log(HWC_LOG_DEBUG,
1665 "[%s] pm_alloc[%d] unmap fd=%d total_size=%d offset=0x%x",
1666 __func__, i, pm_alloc->fd, pm_alloc->total_size,
1667 pm_alloc->offset);
1668#endif
1669 close(pm_alloc->fd);
1670
1671 pm_alloc->fd = -1;
1672 pm_alloc->total_size = 0;
1673 pm_alloc->offset = 0;
1674 pm_alloc->virt_addr = 0;
1675 pm_alloc->phys_addr = 0;
1676 }
1677 }
1678
1679 if (0 <= pm->pmem_master_fd) {
1680 munmap(pm->pmem_master_base, pm->pmem_total_size);
1681 close(pm->pmem_master_fd);
1682 pm->pmem_master_fd = -1;
1683 }
1684
1685 pm->pmem_master_base = 0;
1686 pm->pmem_total_size = 0;
1687
1688 return 0;
1689}
1690
1691int checkPmem(sec_pmem_t *pm, unsigned int index, unsigned int requested_size)
1692{
1693 sec_pmem_alloc_t *pm_alloc = &(pm->sec_pmem_alloc[index]);
1694
1695 if (0 < pm_alloc->virt_addr &&
1696 requested_size <= (unsigned int)(pm_alloc->total_size))
1697 return 0;
1698
1699 pm_alloc->size = 0;
1700 return -1;
1701}
1702
1703#endif