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Yabin Cui76769e52015-07-13 12:23:54 -07001/*
2 * Copyright (C) 2015 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "perf_regs.h"
18
Yabin Cui6e75e1b2018-02-06 13:42:16 -080019#include <string.h>
20
Elliott Hughes66dd09e2015-12-04 14:00:57 -080021#include <android-base/logging.h>
22#include <android-base/stringprintf.h>
23#include <android-base/strings.h>
Thiébaud Weksteen4848ee02020-10-23 16:06:59 +020024#include <unordered_map>
Yabin Cui76769e52015-07-13 12:23:54 -070025
Yabin Cui257d5e62016-03-30 16:21:47 -070026#include "perf_event.h"
27
Yabin Cuifaa7b922021-01-11 17:35:57 -080028namespace simpleperf {
29
Yabin Cui417df292016-11-16 12:26:13 -080030ArchType ScopedCurrentArch::current_arch = ARCH_UNSUPPORTED;
Yabin Cui76769e52015-07-13 12:23:54 -070031
Yabin Cui48460892016-03-18 12:30:31 -070032ArchType GetArchType(const std::string& arch) {
Than McIntosh46546e92015-12-29 13:56:10 -050033 if (arch == "x86" || arch == "i686") {
Yabin Cui48460892016-03-18 12:30:31 -070034 return ARCH_X86_32;
Yabin Cui76769e52015-07-13 12:23:54 -070035 } else if (arch == "x86_64") {
Yabin Cui48460892016-03-18 12:30:31 -070036 return ARCH_X86_64;
haocheng.zydb13e562022-10-12 22:57:39 +080037 } else if (arch == "riscv64") {
38 return ARCH_RISCV64;
Yabin Cui76769e52015-07-13 12:23:54 -070039 } else if (arch == "aarch64") {
Yabin Cui48460892016-03-18 12:30:31 -070040 return ARCH_ARM64;
Yabin Cui76769e52015-07-13 12:23:54 -070041 } else if (android::base::StartsWith(arch, "arm")) {
Yabin Cui417df292016-11-16 12:26:13 -080042 // If arch is "armv8l", it is likely that we are using a 32-bit simpleperf
43 // binary on a aarch64 device. In this case, the profiling environment is
44 // ARCH_ARM64, because the kernel is aarch64.
45 if (arch[3] == 'v') {
46 int version = atoi(&arch[4]);
47 if (version >= 8) {
48 return ARCH_ARM64;
49 }
50 }
Yabin Cui48460892016-03-18 12:30:31 -070051 return ARCH_ARM;
Yabin Cui76769e52015-07-13 12:23:54 -070052 }
Yabin Cui48460892016-03-18 12:30:31 -070053 LOG(ERROR) << "unsupported arch: " << arch;
54 return ARCH_UNSUPPORTED;
Yabin Cui76769e52015-07-13 12:23:54 -070055}
56
Yabin Cui257d5e62016-03-30 16:21:47 -070057ArchType GetArchForAbi(ArchType machine_arch, int abi) {
58 if (abi == PERF_SAMPLE_REGS_ABI_32) {
59 if (machine_arch == ARCH_X86_64) {
60 return ARCH_X86_32;
61 }
62 if (machine_arch == ARCH_ARM64) {
63 return ARCH_ARM;
64 }
Yabin Cuif227b6d2021-01-06 14:01:53 -080065 } else if (abi == PERF_SAMPLE_REGS_ABI_64) {
66 if (machine_arch == ARCH_X86_32) {
67 return ARCH_X86_64;
68 }
69 if (machine_arch == ARCH_ARM) {
70 return ARCH_ARM64;
71 }
Yabin Cui257d5e62016-03-30 16:21:47 -070072 }
73 return machine_arch;
74}
75
76std::string GetArchString(ArchType arch) {
77 switch (arch) {
78 case ARCH_X86_32:
79 return "x86";
80 case ARCH_X86_64:
81 return "x86_64";
82 case ARCH_ARM64:
83 return "arm64";
84 case ARCH_ARM:
85 return "arm";
haocheng.zydb13e562022-10-12 22:57:39 +080086 case ARCH_RISCV64:
87 return "riscv64";
Yabin Cui257d5e62016-03-30 16:21:47 -070088 default:
89 break;
90 }
91 return "unknown";
92}
93
Yabin Cui48460892016-03-18 12:30:31 -070094uint64_t GetSupportedRegMask(ArchType arch) {
95 switch (arch) {
Yabin Cui76769e52015-07-13 12:23:54 -070096 case ARCH_X86_32:
Yabin Cui30ae2db2017-06-22 13:02:29 -070097 return ((1ULL << PERF_REG_X86_32_MAX) - 1) & ~(1ULL << PERF_REG_X86_DS) &
Thiébaud Weksteen4848ee02020-10-23 16:06:59 +020098 ~(1ULL << PERF_REG_X86_ES) & ~(1ULL << PERF_REG_X86_FS) & ~(1ULL << PERF_REG_X86_GS);
Yabin Cui76769e52015-07-13 12:23:54 -070099 case ARCH_X86_64:
100 return (((1ULL << PERF_REG_X86_64_MAX) - 1) & ~(1ULL << PERF_REG_X86_DS) &
101 ~(1ULL << PERF_REG_X86_ES) & ~(1ULL << PERF_REG_X86_FS) & ~(1ULL << PERF_REG_X86_GS));
102 case ARCH_ARM:
103 return ((1ULL << PERF_REG_ARM_MAX) - 1);
104 case ARCH_ARM64:
105 return ((1ULL << PERF_REG_ARM64_MAX) - 1);
haocheng.zydb13e562022-10-12 22:57:39 +0800106 case ARCH_RISCV64:
107 return ((1ULL << PERF_REG_RISCV_MAX) - 1);
Yabin Cuica7b9e72015-07-13 19:44:24 -0700108 default:
109 return 0;
Yabin Cui76769e52015-07-13 12:23:54 -0700110 }
111 return 0;
112}
113
114static std::unordered_map<size_t, std::string> x86_reg_map = {
115 {PERF_REG_X86_AX, "ax"}, {PERF_REG_X86_BX, "bx"}, {PERF_REG_X86_CX, "cx"},
116 {PERF_REG_X86_DX, "dx"}, {PERF_REG_X86_SI, "si"}, {PERF_REG_X86_DI, "di"},
117 {PERF_REG_X86_BP, "bp"}, {PERF_REG_X86_SP, "sp"}, {PERF_REG_X86_IP, "ip"},
118 {PERF_REG_X86_FLAGS, "flags"}, {PERF_REG_X86_CS, "cs"}, {PERF_REG_X86_SS, "ss"},
119 {PERF_REG_X86_DS, "ds"}, {PERF_REG_X86_ES, "es"}, {PERF_REG_X86_FS, "fs"},
120 {PERF_REG_X86_GS, "gs"},
121};
122
123static std::unordered_map<size_t, std::string> arm_reg_map = {
124 {PERF_REG_ARM_FP, "fp"}, {PERF_REG_ARM_IP, "ip"}, {PERF_REG_ARM_SP, "sp"},
125 {PERF_REG_ARM_LR, "lr"}, {PERF_REG_ARM_PC, "pc"},
126};
127
128static std::unordered_map<size_t, std::string> arm64_reg_map = {
Thiébaud Weksteen4848ee02020-10-23 16:06:59 +0200129 {PERF_REG_ARM64_LR, "lr"},
130 {PERF_REG_ARM64_SP, "sp"},
131 {PERF_REG_ARM64_PC, "pc"},
Yabin Cui76769e52015-07-13 12:23:54 -0700132};
133
haocheng.zydb13e562022-10-12 22:57:39 +0800134static std::unordered_map<size_t, std::string> riscv64_reg_map = {
135 {PERF_REG_RISCV_PC, "pc"},
136 {PERF_REG_RISCV_RA, "ra"},
137 {PERF_REG_RISCV_SP, "sp"},
138 {PERF_REG_RISCV_GP, "gp"},
139 {PERF_REG_RISCV_TP, "tp"},
140 {PERF_REG_RISCV_T0, "t0"},
141 {PERF_REG_RISCV_T1, "t1"},
142 {PERF_REG_RISCV_T2, "t2"},
143 {PERF_REG_RISCV_S0, "s0"},
144 {PERF_REG_RISCV_S1, "s1"},
145 {PERF_REG_RISCV_A0, "a0"},
146 {PERF_REG_RISCV_A1, "a1"},
147 {PERF_REG_RISCV_A2, "a2"},
148 {PERF_REG_RISCV_A3, "a3"},
149 {PERF_REG_RISCV_A4, "a4"},
150 {PERF_REG_RISCV_A5, "a5"},
151 {PERF_REG_RISCV_A6, "a6"},
152 {PERF_REG_RISCV_A7, "a7"},
153 {PERF_REG_RISCV_S2, "s2"},
154 {PERF_REG_RISCV_S3, "s3"},
155 {PERF_REG_RISCV_S4, "s4"},
156 {PERF_REG_RISCV_S5, "s5"},
157 {PERF_REG_RISCV_S6, "s6"},
158 {PERF_REG_RISCV_S7, "s7"},
159 {PERF_REG_RISCV_S8, "s8"},
160 {PERF_REG_RISCV_S9, "s9"},
161 {PERF_REG_RISCV_S10, "s10"},
162 {PERF_REG_RISCV_S11, "s11"},
163 {PERF_REG_RISCV_T3, "t3"},
164 {PERF_REG_RISCV_T4, "t4"},
165 {PERF_REG_RISCV_T5, "t5"},
166 {PERF_REG_RISCV_T6, "t6"},
167};
168
Yabin Cui48460892016-03-18 12:30:31 -0700169std::string GetRegName(size_t regno, ArchType arch) {
Yabin Cuiffaa9122016-01-15 15:25:48 -0800170 // Cast regno to int type to avoid -Werror=type-limits.
171 int reg = static_cast<int>(regno);
Yabin Cui48460892016-03-18 12:30:31 -0700172 switch (arch) {
Yabin Cui76769e52015-07-13 12:23:54 -0700173 case ARCH_X86_64: {
174 if (reg >= PERF_REG_X86_R8 && reg <= PERF_REG_X86_R15) {
Yabin Cuiffaa9122016-01-15 15:25:48 -0800175 return android::base::StringPrintf("r%d", reg - PERF_REG_X86_R8 + 8);
Yabin Cui76769e52015-07-13 12:23:54 -0700176 }
George Burgess IVda078442018-08-13 22:41:12 -0700177 FALLTHROUGH_INTENDED;
178 }
Yabin Cui76769e52015-07-13 12:23:54 -0700179 case ARCH_X86_32: {
180 auto it = x86_reg_map.find(reg);
181 CHECK(it != x86_reg_map.end()) << "unknown reg " << reg;
182 return it->second;
183 }
184 case ARCH_ARM: {
185 if (reg >= PERF_REG_ARM_R0 && reg <= PERF_REG_ARM_R10) {
Yabin Cuiffaa9122016-01-15 15:25:48 -0800186 return android::base::StringPrintf("r%d", reg - PERF_REG_ARM_R0);
Yabin Cui76769e52015-07-13 12:23:54 -0700187 }
Yabin Cui078e0c42021-07-13 14:18:06 -0700188 if (auto it = arm_reg_map.find(reg); it != arm_reg_map.end()) {
189 return it->second;
190 }
191 FALLTHROUGH_INTENDED;
Yabin Cui76769e52015-07-13 12:23:54 -0700192 }
193 case ARCH_ARM64: {
194 if (reg >= PERF_REG_ARM64_X0 && reg <= PERF_REG_ARM64_X29) {
Yabin Cuiffaa9122016-01-15 15:25:48 -0800195 return android::base::StringPrintf("r%d", reg - PERF_REG_ARM64_X0);
Yabin Cui76769e52015-07-13 12:23:54 -0700196 }
197 auto it = arm64_reg_map.find(reg);
198 CHECK(it != arm64_reg_map.end()) << "unknown reg " << reg;
199 return it->second;
200 }
haocheng.zydb13e562022-10-12 22:57:39 +0800201 case ARCH_RISCV64: {
202 auto it = riscv64_reg_map.find(reg);
203 CHECK(it != riscv64_reg_map.end()) << "unknown reg " << reg;
204 return it->second;
205 }
Yabin Cui3c8c2132015-08-13 20:30:20 -0700206 default:
Yabin Cuica7b9e72015-07-13 19:44:24 -0700207 return "unknown";
Yabin Cui76769e52015-07-13 12:23:54 -0700208 }
Yabin Cui76769e52015-07-13 12:23:54 -0700209}
Yabin Cui3c8c2132015-08-13 20:30:20 -0700210
Thiébaud Weksteen4848ee02020-10-23 16:06:59 +0200211RegSet::RegSet(int abi, uint64_t valid_mask, const uint64_t* valid_regs) : valid_mask(valid_mask) {
Yabin Cuif227b6d2021-01-06 14:01:53 -0800212 arch = GetArchForAbi(ScopedCurrentArch::GetCurrentArch(), abi);
Yabin Cui6e75e1b2018-02-06 13:42:16 -0800213 memset(data, 0, sizeof(data));
Yabin Cui3c8c2132015-08-13 20:30:20 -0700214 for (int i = 0, j = 0; i < 64; ++i) {
215 if ((valid_mask >> i) & 1) {
Yabin Cui6e75e1b2018-02-06 13:42:16 -0800216 data[i] = valid_regs[j++];
Yabin Cui3c8c2132015-08-13 20:30:20 -0700217 }
218 }
Yabin Cui6e75e1b2018-02-06 13:42:16 -0800219 if (ScopedCurrentArch::GetCurrentArch() == ARCH_ARM64 && abi == PERF_SAMPLE_REGS_ABI_32) {
220 // The kernel dumps arm64 regs, but we need arm regs. So map arm64 regs into arm regs.
221 data[PERF_REG_ARM_PC] = data[PERF_REG_ARM64_PC];
Yabin Cui417df292016-11-16 12:26:13 -0800222 }
Yabin Cui3c8c2132015-08-13 20:30:20 -0700223}
224
Yabin Cui6e75e1b2018-02-06 13:42:16 -0800225bool RegSet::GetRegValue(size_t regno, uint64_t* value) const {
Yabin Cui3c8c2132015-08-13 20:30:20 -0700226 CHECK_LT(regno, 64U);
Yabin Cui6e75e1b2018-02-06 13:42:16 -0800227 if ((valid_mask >> regno) & 1) {
228 *value = data[regno];
Yabin Cui3c8c2132015-08-13 20:30:20 -0700229 return true;
230 }
231 return false;
232}
233
Yabin Cui6e75e1b2018-02-06 13:42:16 -0800234bool RegSet::GetSpRegValue(uint64_t* value) const {
Yabin Cui3c8c2132015-08-13 20:30:20 -0700235 size_t regno;
Yabin Cui48460892016-03-18 12:30:31 -0700236 switch (arch) {
237 case ARCH_X86_32:
238 regno = PERF_REG_X86_SP;
239 break;
240 case ARCH_X86_64:
241 regno = PERF_REG_X86_SP;
242 break;
243 case ARCH_ARM:
244 regno = PERF_REG_ARM_SP;
245 break;
246 case ARCH_ARM64:
247 regno = PERF_REG_ARM64_SP;
248 break;
haocheng.zydb13e562022-10-12 22:57:39 +0800249 case ARCH_RISCV64:
250 regno = PERF_REG_RISCV_SP;
251 break;
Yabin Cui48460892016-03-18 12:30:31 -0700252 default:
253 return false;
254 }
Yabin Cui6e75e1b2018-02-06 13:42:16 -0800255 return GetRegValue(regno, value);
Yabin Cui3c8c2132015-08-13 20:30:20 -0700256}
Yabin Cui81a9d332017-12-10 13:09:07 -0800257
Yabin Cui6e75e1b2018-02-06 13:42:16 -0800258bool RegSet::GetIpRegValue(uint64_t* value) const {
Yabin Cui81a9d332017-12-10 13:09:07 -0800259 size_t regno;
260 switch (arch) {
261 case ARCH_X86_64:
262 case ARCH_X86_32:
263 regno = PERF_REG_X86_IP;
264 break;
265 case ARCH_ARM:
266 regno = PERF_REG_ARM_PC;
267 break;
268 case ARCH_ARM64:
269 regno = PERF_REG_ARM64_PC;
270 break;
haocheng.zydb13e562022-10-12 22:57:39 +0800271 case ARCH_RISCV64:
272 regno = PERF_REG_RISCV_PC;
273 break;
Yabin Cui81a9d332017-12-10 13:09:07 -0800274 default:
275 return false;
276 }
Yabin Cui6e75e1b2018-02-06 13:42:16 -0800277 return GetRegValue(regno, value);
Yabin Cui81a9d332017-12-10 13:09:07 -0800278}
Yabin Cuifaa7b922021-01-11 17:35:57 -0800279
280} // namespace simpleperf