blob: d3146018d6ba96f15efc22e3517776f8e4461e41 [file] [log] [blame]
Brian Carlstrom7940e442013-07-12 13:46:57 -07001/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "dex/compiler_ir.h"
18#include "dex/compiler_internals.h"
19#include "dex/quick/mir_to_lir-inl.h"
20#include "invoke_type.h"
21
22namespace art {
23
24/* This file contains target-independent codegen and support. */
25
26/*
27 * Load an immediate value into a fixed or temp register. Target
28 * register is clobbered, and marked in_use.
29 */
buzbee2700f7e2014-03-07 09:46:20 -080030LIR* Mir2Lir::LoadConstant(RegStorage r_dest, int value) {
Brian Carlstrom7940e442013-07-12 13:46:57 -070031 if (IsTemp(r_dest)) {
32 Clobber(r_dest);
33 MarkInUse(r_dest);
34 }
35 return LoadConstantNoClobber(r_dest, value);
36}
37
38/*
39 * Temporary workaround for Issue 7250540. If we're loading a constant zero into a
40 * promoted floating point register, also copy a zero into the int/ref identity of
41 * that sreg.
42 */
buzbee2700f7e2014-03-07 09:46:20 -080043void Mir2Lir::Workaround7250540(RegLocation rl_dest, RegStorage zero_reg) {
Brian Carlstrom7940e442013-07-12 13:46:57 -070044 if (rl_dest.fp) {
45 int pmap_index = SRegToPMap(rl_dest.s_reg_low);
46 if (promotion_map_[pmap_index].fp_location == kLocPhysReg) {
47 // Now, determine if this vreg is ever used as a reference. If not, we're done.
48 bool used_as_reference = false;
49 int base_vreg = mir_graph_->SRegToVReg(rl_dest.s_reg_low);
50 for (int i = 0; !used_as_reference && (i < mir_graph_->GetNumSSARegs()); i++) {
51 if (mir_graph_->SRegToVReg(mir_graph_->reg_location_[i].s_reg_low) == base_vreg) {
52 used_as_reference |= mir_graph_->reg_location_[i].ref;
53 }
54 }
55 if (!used_as_reference) {
56 return;
57 }
buzbee2700f7e2014-03-07 09:46:20 -080058 RegStorage temp_reg = zero_reg;
59 if (!temp_reg.Valid()) {
Brian Carlstrom7940e442013-07-12 13:46:57 -070060 temp_reg = AllocTemp();
61 LoadConstant(temp_reg, 0);
62 }
63 if (promotion_map_[pmap_index].core_location == kLocPhysReg) {
64 // Promoted - just copy in a zero
buzbee2700f7e2014-03-07 09:46:20 -080065 OpRegCopy(RegStorage::Solo32(promotion_map_[pmap_index].core_reg), temp_reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -070066 } else {
67 // Lives in the frame, need to store.
Vladimir Marko8dea81c2014-06-06 14:50:36 +010068 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
Chao-ying Fua77ee512014-07-01 17:43:41 -070069 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), temp_reg, k32, kNotVolatile);
Brian Carlstrom7940e442013-07-12 13:46:57 -070070 }
buzbee2700f7e2014-03-07 09:46:20 -080071 if (!zero_reg.Valid()) {
Brian Carlstrom7940e442013-07-12 13:46:57 -070072 FreeTemp(temp_reg);
73 }
74 }
75 }
76}
77
Brian Carlstrom7940e442013-07-12 13:46:57 -070078/*
79 * Load a Dalvik register into a physical register. Take care when
80 * using this routine, as it doesn't perform any bookkeeping regarding
81 * register liveness. That is the responsibility of the caller.
82 */
buzbee2700f7e2014-03-07 09:46:20 -080083void Mir2Lir::LoadValueDirect(RegLocation rl_src, RegStorage r_dest) {
Brian Carlstrom7940e442013-07-12 13:46:57 -070084 rl_src = UpdateLoc(rl_src);
85 if (rl_src.location == kLocPhysReg) {
buzbee2700f7e2014-03-07 09:46:20 -080086 OpRegCopy(r_dest, rl_src.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -070087 } else if (IsInexpensiveConstant(rl_src)) {
buzbee695d13a2014-04-19 13:32:20 -070088 // On 64-bit targets, will sign extend. Make sure constant reference is always NULL.
89 DCHECK(!rl_src.ref || (mir_graph_->ConstantValue(rl_src) == 0));
Brian Carlstrom7940e442013-07-12 13:46:57 -070090 LoadConstantNoClobber(r_dest, mir_graph_->ConstantValue(rl_src));
91 } else {
92 DCHECK((rl_src.location == kLocDalvikFrame) ||
93 (rl_src.location == kLocCompilerTemp));
Vladimir Marko8dea81c2014-06-06 14:50:36 +010094 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
buzbee695d13a2014-04-19 13:32:20 -070095 if (rl_src.ref) {
Chao-ying Fua77ee512014-07-01 17:43:41 -070096 LoadRefDisp(TargetPtrReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest, kNotVolatile);
buzbee695d13a2014-04-19 13:32:20 -070097 } else {
Chao-ying Fua77ee512014-07-01 17:43:41 -070098 Load32Disp(TargetPtrReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest);
buzbee695d13a2014-04-19 13:32:20 -070099 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700100 }
101}
102
103/*
104 * Similar to LoadValueDirect, but clobbers and allocates the target
105 * register. Should be used when loading to a fixed register (for example,
106 * loading arguments to an out of line call.
107 */
buzbee2700f7e2014-03-07 09:46:20 -0800108void Mir2Lir::LoadValueDirectFixed(RegLocation rl_src, RegStorage r_dest) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700109 Clobber(r_dest);
110 MarkInUse(r_dest);
111 LoadValueDirect(rl_src, r_dest);
112}
113
114/*
115 * Load a Dalvik register pair into a physical register[s]. Take care when
116 * using this routine, as it doesn't perform any bookkeeping regarding
117 * register liveness. That is the responsibility of the caller.
118 */
buzbee2700f7e2014-03-07 09:46:20 -0800119void Mir2Lir::LoadValueDirectWide(RegLocation rl_src, RegStorage r_dest) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700120 rl_src = UpdateLocWide(rl_src);
121 if (rl_src.location == kLocPhysReg) {
buzbee2700f7e2014-03-07 09:46:20 -0800122 OpRegCopyWide(r_dest, rl_src.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700123 } else if (IsInexpensiveConstant(rl_src)) {
buzbee2700f7e2014-03-07 09:46:20 -0800124 LoadConstantWide(r_dest, mir_graph_->ConstantValueWide(rl_src));
Brian Carlstrom7940e442013-07-12 13:46:57 -0700125 } else {
126 DCHECK((rl_src.location == kLocDalvikFrame) ||
127 (rl_src.location == kLocCompilerTemp));
Vladimir Marko8dea81c2014-06-06 14:50:36 +0100128 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
Chao-ying Fua77ee512014-07-01 17:43:41 -0700129 LoadBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest, k64, kNotVolatile);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700130 }
131}
132
133/*
134 * Similar to LoadValueDirect, but clobbers and allocates the target
135 * registers. Should be used when loading to a fixed registers (for example,
136 * loading arguments to an out of line call.
137 */
buzbee2700f7e2014-03-07 09:46:20 -0800138void Mir2Lir::LoadValueDirectWideFixed(RegLocation rl_src, RegStorage r_dest) {
139 Clobber(r_dest);
140 MarkInUse(r_dest);
141 LoadValueDirectWide(rl_src, r_dest);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700142}
143
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700144RegLocation Mir2Lir::LoadValue(RegLocation rl_src, RegisterClass op_kind) {
buzbeea0cd2d72014-06-01 09:33:49 -0700145 DCHECK(!rl_src.ref || op_kind == kRefReg);
Vladimir Marko0dc242d2014-05-12 16:22:14 +0100146 rl_src = UpdateLoc(rl_src);
147 if (rl_src.location == kLocPhysReg) {
148 if (!RegClassMatches(op_kind, rl_src.reg)) {
149 // Wrong register class, realloc, copy and transfer ownership.
150 RegStorage new_reg = AllocTypedTemp(rl_src.fp, op_kind);
151 OpRegCopy(new_reg, rl_src.reg);
Serguei Katkov02c637e2014-10-29 13:48:02 +0600152 // Clobber the old regs and free it.
Vladimir Marko0dc242d2014-05-12 16:22:14 +0100153 Clobber(rl_src.reg);
Serguei Katkov02c637e2014-10-29 13:48:02 +0600154 FreeTemp(rl_src.reg);
buzbee082833c2014-05-17 23:16:26 -0700155 // ...and mark the new one live.
Vladimir Marko0dc242d2014-05-12 16:22:14 +0100156 rl_src.reg = new_reg;
buzbee082833c2014-05-17 23:16:26 -0700157 MarkLive(rl_src);
Vladimir Marko0dc242d2014-05-12 16:22:14 +0100158 }
159 return rl_src;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700160 }
Vladimir Marko0dc242d2014-05-12 16:22:14 +0100161
162 DCHECK_NE(rl_src.s_reg_low, INVALID_SREG);
163 rl_src.reg = AllocTypedTemp(rl_src.fp, op_kind);
164 LoadValueDirect(rl_src, rl_src.reg);
165 rl_src.location = kLocPhysReg;
166 MarkLive(rl_src);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700167 return rl_src;
168}
169
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700170void Mir2Lir::StoreValue(RegLocation rl_dest, RegLocation rl_src) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700171 /*
172 * Sanity checking - should never try to store to the same
173 * ssa name during the compilation of a single instruction
174 * without an intervening ClobberSReg().
175 */
176 if (kIsDebugBuild) {
177 DCHECK((live_sreg_ == INVALID_SREG) ||
178 (rl_dest.s_reg_low != live_sreg_));
179 live_sreg_ = rl_dest.s_reg_low;
180 }
181 LIR* def_start;
182 LIR* def_end;
183 DCHECK(!rl_dest.wide);
184 DCHECK(!rl_src.wide);
185 rl_src = UpdateLoc(rl_src);
186 rl_dest = UpdateLoc(rl_dest);
187 if (rl_src.location == kLocPhysReg) {
buzbee2700f7e2014-03-07 09:46:20 -0800188 if (IsLive(rl_src.reg) ||
189 IsPromoted(rl_src.reg) ||
Brian Carlstrom7940e442013-07-12 13:46:57 -0700190 (rl_dest.location == kLocPhysReg)) {
191 // Src is live/promoted or Dest has assigned reg.
Andreas Gampe4b537a82014-06-30 22:24:53 -0700192 rl_dest = EvalLoc(rl_dest, rl_dest.ref || rl_src.ref ? kRefReg : kAnyReg, false);
buzbee2700f7e2014-03-07 09:46:20 -0800193 OpRegCopy(rl_dest.reg, rl_src.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700194 } else {
195 // Just re-assign the registers. Dest gets Src's regs
Bill Buzbee00e1ec62014-02-27 23:44:13 +0000196 rl_dest.reg = rl_src.reg;
buzbee2700f7e2014-03-07 09:46:20 -0800197 Clobber(rl_src.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700198 }
199 } else {
200 // Load Src either into promoted Dest or temps allocated for Dest
Andreas Gampe4b537a82014-06-30 22:24:53 -0700201 rl_dest = EvalLoc(rl_dest, rl_dest.ref ? kRefReg : kAnyReg, false);
buzbee2700f7e2014-03-07 09:46:20 -0800202 LoadValueDirect(rl_src, rl_dest.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700203 }
204
205 // Dest is now live and dirty (until/if we flush it to home location)
buzbee091cc402014-03-31 10:14:40 -0700206 MarkLive(rl_dest);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700207 MarkDirty(rl_dest);
208
209
210 ResetDefLoc(rl_dest);
buzbee091cc402014-03-31 10:14:40 -0700211 if (IsDirty(rl_dest.reg) && LiveOut(rl_dest.s_reg_low)) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700212 def_start = last_lir_insn_;
Ian Rogerse98297b2014-06-22 07:47:53 +0000213 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
Andreas Gampe2073e752014-06-23 15:39:00 +0000214 if (rl_dest.ref) {
Chao-ying Fua77ee512014-07-01 17:43:41 -0700215 StoreRefDisp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg, kNotVolatile);
Andreas Gampe2073e752014-06-23 15:39:00 +0000216 } else {
Chao-ying Fua77ee512014-07-01 17:43:41 -0700217 Store32Disp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg);
Andreas Gampe2073e752014-06-23 15:39:00 +0000218 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700219 MarkClean(rl_dest);
220 def_end = last_lir_insn_;
221 if (!rl_dest.ref) {
222 // Exclude references from store elimination
223 MarkDef(rl_dest, def_start, def_end);
224 }
225 }
226}
227
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700228RegLocation Mir2Lir::LoadValueWide(RegLocation rl_src, RegisterClass op_kind) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700229 DCHECK(rl_src.wide);
Vladimir Marko0dc242d2014-05-12 16:22:14 +0100230 rl_src = UpdateLocWide(rl_src);
231 if (rl_src.location == kLocPhysReg) {
232 if (!RegClassMatches(op_kind, rl_src.reg)) {
233 // Wrong register class, realloc, copy and transfer ownership.
234 RegStorage new_regs = AllocTypedTempWide(rl_src.fp, op_kind);
235 OpRegCopyWide(new_regs, rl_src.reg);
Serguei Katkov02c637e2014-10-29 13:48:02 +0600236 // Clobber the old regs and free it.
Vladimir Marko0dc242d2014-05-12 16:22:14 +0100237 Clobber(rl_src.reg);
Serguei Katkov02c637e2014-10-29 13:48:02 +0600238 FreeTemp(rl_src.reg);
buzbee082833c2014-05-17 23:16:26 -0700239 // ...and mark the new ones live.
Vladimir Marko0dc242d2014-05-12 16:22:14 +0100240 rl_src.reg = new_regs;
buzbee082833c2014-05-17 23:16:26 -0700241 MarkLive(rl_src);
Vladimir Marko0dc242d2014-05-12 16:22:14 +0100242 }
243 return rl_src;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700244 }
Vladimir Marko0dc242d2014-05-12 16:22:14 +0100245
246 DCHECK_NE(rl_src.s_reg_low, INVALID_SREG);
247 DCHECK_NE(GetSRegHi(rl_src.s_reg_low), INVALID_SREG);
248 rl_src.reg = AllocTypedTempWide(rl_src.fp, op_kind);
249 LoadValueDirectWide(rl_src, rl_src.reg);
250 rl_src.location = kLocPhysReg;
251 MarkLive(rl_src);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700252 return rl_src;
253}
254
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700255void Mir2Lir::StoreValueWide(RegLocation rl_dest, RegLocation rl_src) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700256 /*
257 * Sanity checking - should never try to store to the same
258 * ssa name during the compilation of a single instruction
259 * without an intervening ClobberSReg().
260 */
261 if (kIsDebugBuild) {
262 DCHECK((live_sreg_ == INVALID_SREG) ||
263 (rl_dest.s_reg_low != live_sreg_));
264 live_sreg_ = rl_dest.s_reg_low;
265 }
266 LIR* def_start;
267 LIR* def_end;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700268 DCHECK(rl_dest.wide);
269 DCHECK(rl_src.wide);
Alexei Zavjalovc17ebe82014-02-26 10:38:23 +0700270 rl_src = UpdateLocWide(rl_src);
271 rl_dest = UpdateLocWide(rl_dest);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700272 if (rl_src.location == kLocPhysReg) {
buzbee2700f7e2014-03-07 09:46:20 -0800273 if (IsLive(rl_src.reg) ||
274 IsPromoted(rl_src.reg) ||
Brian Carlstrom7940e442013-07-12 13:46:57 -0700275 (rl_dest.location == kLocPhysReg)) {
buzbee30adc732014-05-09 15:10:18 -0700276 /*
277 * If src reg[s] are tied to the original Dalvik vreg via liveness or promotion, we
278 * can't repurpose them. Similarly, if the dest reg[s] are tied to Dalvik vregs via
279 * promotion, we can't just re-assign. In these cases, we have to copy.
280 */
Brian Carlstrom7940e442013-07-12 13:46:57 -0700281 rl_dest = EvalLoc(rl_dest, kAnyReg, false);
buzbee2700f7e2014-03-07 09:46:20 -0800282 OpRegCopyWide(rl_dest.reg, rl_src.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700283 } else {
284 // Just re-assign the registers. Dest gets Src's regs
Bill Buzbee00e1ec62014-02-27 23:44:13 +0000285 rl_dest.reg = rl_src.reg;
buzbee2700f7e2014-03-07 09:46:20 -0800286 Clobber(rl_src.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700287 }
288 } else {
289 // Load Src either into promoted Dest or temps allocated for Dest
290 rl_dest = EvalLoc(rl_dest, kAnyReg, false);
buzbee2700f7e2014-03-07 09:46:20 -0800291 LoadValueDirectWide(rl_src, rl_dest.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700292 }
293
294 // Dest is now live and dirty (until/if we flush it to home location)
buzbee091cc402014-03-31 10:14:40 -0700295 MarkLive(rl_dest);
296 MarkWide(rl_dest.reg);
297 MarkDirty(rl_dest);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700298
299 ResetDefLocWide(rl_dest);
buzbee091cc402014-03-31 10:14:40 -0700300 if (IsDirty(rl_dest.reg) && (LiveOut(rl_dest.s_reg_low) ||
301 LiveOut(GetSRegHi(rl_dest.s_reg_low)))) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700302 def_start = last_lir_insn_;
303 DCHECK_EQ((mir_graph_->SRegToVReg(rl_dest.s_reg_low)+1),
304 mir_graph_->SRegToVReg(GetSRegHi(rl_dest.s_reg_low)));
Vladimir Marko8dea81c2014-06-06 14:50:36 +0100305 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
Chao-ying Fua77ee512014-07-01 17:43:41 -0700306 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg, k64, kNotVolatile);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700307 MarkClean(rl_dest);
308 def_end = last_lir_insn_;
309 MarkDefWide(rl_dest, def_start, def_end);
310 }
311}
312
Mark Mendellfeb2b4e2014-01-28 12:59:49 -0800313void Mir2Lir::StoreFinalValue(RegLocation rl_dest, RegLocation rl_src) {
314 DCHECK_EQ(rl_src.location, kLocPhysReg);
315
316 if (rl_dest.location == kLocPhysReg) {
buzbee2700f7e2014-03-07 09:46:20 -0800317 OpRegCopy(rl_dest.reg, rl_src.reg);
Mark Mendellfeb2b4e2014-01-28 12:59:49 -0800318 } else {
319 // Just re-assign the register. Dest gets Src's reg.
Mark Mendellfeb2b4e2014-01-28 12:59:49 -0800320 rl_dest.location = kLocPhysReg;
Bill Buzbee00e1ec62014-02-27 23:44:13 +0000321 rl_dest.reg = rl_src.reg;
buzbee2700f7e2014-03-07 09:46:20 -0800322 Clobber(rl_src.reg);
Mark Mendellfeb2b4e2014-01-28 12:59:49 -0800323 }
324
325 // Dest is now live and dirty (until/if we flush it to home location)
buzbee091cc402014-03-31 10:14:40 -0700326 MarkLive(rl_dest);
Mark Mendellfeb2b4e2014-01-28 12:59:49 -0800327 MarkDirty(rl_dest);
328
329
330 ResetDefLoc(rl_dest);
buzbee091cc402014-03-31 10:14:40 -0700331 if (IsDirty(rl_dest.reg) && LiveOut(rl_dest.s_reg_low)) {
Mark Mendellfeb2b4e2014-01-28 12:59:49 -0800332 LIR *def_start = last_lir_insn_;
Vladimir Marko8dea81c2014-06-06 14:50:36 +0100333 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
Chao-ying Fua77ee512014-07-01 17:43:41 -0700334 Store32Disp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg);
Mark Mendellfeb2b4e2014-01-28 12:59:49 -0800335 MarkClean(rl_dest);
336 LIR *def_end = last_lir_insn_;
337 if (!rl_dest.ref) {
338 // Exclude references from store elimination
339 MarkDef(rl_dest, def_start, def_end);
340 }
341 }
342}
343
Mark Mendelle02d48f2014-01-15 11:19:23 -0800344void Mir2Lir::StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src) {
Mark Mendelle02d48f2014-01-15 11:19:23 -0800345 DCHECK(rl_dest.wide);
346 DCHECK(rl_src.wide);
347 DCHECK_EQ(rl_src.location, kLocPhysReg);
348
349 if (rl_dest.location == kLocPhysReg) {
buzbee2700f7e2014-03-07 09:46:20 -0800350 OpRegCopyWide(rl_dest.reg, rl_src.reg);
Mark Mendelle02d48f2014-01-15 11:19:23 -0800351 } else {
352 // Just re-assign the registers. Dest gets Src's regs.
Mark Mendelle02d48f2014-01-15 11:19:23 -0800353 rl_dest.location = kLocPhysReg;
Bill Buzbee00e1ec62014-02-27 23:44:13 +0000354 rl_dest.reg = rl_src.reg;
buzbee091cc402014-03-31 10:14:40 -0700355 Clobber(rl_src.reg);
Mark Mendelle02d48f2014-01-15 11:19:23 -0800356 }
357
358 // Dest is now live and dirty (until/if we flush it to home location).
buzbee091cc402014-03-31 10:14:40 -0700359 MarkLive(rl_dest);
360 MarkWide(rl_dest.reg);
361 MarkDirty(rl_dest);
Mark Mendelle02d48f2014-01-15 11:19:23 -0800362
363 ResetDefLocWide(rl_dest);
buzbee091cc402014-03-31 10:14:40 -0700364 if (IsDirty(rl_dest.reg) && (LiveOut(rl_dest.s_reg_low) ||
365 LiveOut(GetSRegHi(rl_dest.s_reg_low)))) {
Mark Mendelle02d48f2014-01-15 11:19:23 -0800366 LIR *def_start = last_lir_insn_;
367 DCHECK_EQ((mir_graph_->SRegToVReg(rl_dest.s_reg_low)+1),
368 mir_graph_->SRegToVReg(GetSRegHi(rl_dest.s_reg_low)));
Vladimir Marko8dea81c2014-06-06 14:50:36 +0100369 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
Chao-ying Fua77ee512014-07-01 17:43:41 -0700370 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg, k64, kNotVolatile);
Mark Mendelle02d48f2014-01-15 11:19:23 -0800371 MarkClean(rl_dest);
372 LIR *def_end = last_lir_insn_;
373 MarkDefWide(rl_dest, def_start, def_end);
374 }
375}
376
Brian Carlstrom7940e442013-07-12 13:46:57 -0700377/* Utilities to load the current Method* */
buzbee2700f7e2014-03-07 09:46:20 -0800378void Mir2Lir::LoadCurrMethodDirect(RegStorage r_tgt) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700379 LoadValueDirectFixed(mir_graph_->GetMethodLoc(), r_tgt);
380}
381
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700382RegLocation Mir2Lir::LoadCurrMethod() {
buzbeea0cd2d72014-06-01 09:33:49 -0700383 return LoadValue(mir_graph_->GetMethodLoc(), kRefReg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700384}
385
Mark Mendelle02d48f2014-01-15 11:19:23 -0800386RegLocation Mir2Lir::ForceTemp(RegLocation loc) {
387 DCHECK(!loc.wide);
388 DCHECK(loc.location == kLocPhysReg);
buzbee091cc402014-03-31 10:14:40 -0700389 DCHECK(!loc.reg.IsFloat());
buzbee2700f7e2014-03-07 09:46:20 -0800390 if (IsTemp(loc.reg)) {
391 Clobber(loc.reg);
Mark Mendelle02d48f2014-01-15 11:19:23 -0800392 } else {
buzbee2700f7e2014-03-07 09:46:20 -0800393 RegStorage temp_low = AllocTemp();
394 OpRegCopy(temp_low, loc.reg);
395 loc.reg = temp_low;
Mark Mendelle02d48f2014-01-15 11:19:23 -0800396 }
397
398 // Ensure that this doesn't represent the original SR any more.
399 loc.s_reg_low = INVALID_SREG;
400 return loc;
401}
402
403RegLocation Mir2Lir::ForceTempWide(RegLocation loc) {
404 DCHECK(loc.wide);
405 DCHECK(loc.location == kLocPhysReg);
buzbee091cc402014-03-31 10:14:40 -0700406 DCHECK(!loc.reg.IsFloat());
Chao-ying Fue0ccdc02014-06-06 17:32:37 -0700407
408 if (!loc.reg.IsPair()) {
409 if (IsTemp(loc.reg)) {
410 Clobber(loc.reg);
411 } else {
412 RegStorage temp = AllocTempWide();
413 OpRegCopy(temp, loc.reg);
414 loc.reg = temp;
415 }
Mark Mendelle02d48f2014-01-15 11:19:23 -0800416 } else {
Chao-ying Fue0ccdc02014-06-06 17:32:37 -0700417 if (IsTemp(loc.reg.GetLow())) {
418 Clobber(loc.reg.GetLow());
419 } else {
420 RegStorage temp_low = AllocTemp();
421 OpRegCopy(temp_low, loc.reg.GetLow());
422 loc.reg.SetLowReg(temp_low.GetReg());
423 }
424 if (IsTemp(loc.reg.GetHigh())) {
425 Clobber(loc.reg.GetHigh());
426 } else {
427 RegStorage temp_high = AllocTemp();
428 OpRegCopy(temp_high, loc.reg.GetHigh());
429 loc.reg.SetHighReg(temp_high.GetReg());
430 }
Mark Mendelle02d48f2014-01-15 11:19:23 -0800431 }
432
433 // Ensure that this doesn't represent the original SR any more.
434 loc.s_reg_low = INVALID_SREG;
435 return loc;
436}
437
Brian Carlstrom7940e442013-07-12 13:46:57 -0700438} // namespace art