Gitiles
Code Review Sign In
review.blissroms.org / platform_art / 2dd0e2cea360bc9206eb88ecc40d259e796c239d / . / src / compiler / codegen / x86 / codegen_x86.h
blob: 25f4461237f79860abe9e8cb340bb5ecb69f1321 [file] [log] [blame]
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_SRC_COMPILER_CODEGEN_X86_CODEGENX86_H_
18#define ART_SRC_COMPILER_CODEGEN_X86_CODEGENX86_H_
19
20#include "../../compiler_internals.h"
Ian Rogers07ec8e12012-12-01 01:26:51 -0800[diff] [blame]21#include "x86_lir.h"
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]22
23namespace art {
24
25class X86Codegen : public Codegen {
26 public:
27 // Required for target - codegen helpers.
28 virtual bool SmallLiteralDivide(CompilationUnit* cu, Instruction::Code dalvik_opcode,
29 RegLocation rl_src, RegLocation rl_dest, int lit);
30 virtual int LoadHelper(CompilationUnit* cu, int offset);
31 virtual LIR* LoadBaseDisp(CompilationUnit* cu, int rBase, int displacement, int r_dest,
32 OpSize size, int s_reg);
33 virtual LIR* LoadBaseDispWide(CompilationUnit* cu, int rBase, int displacement, int r_dest_lo,
34 int r_dest_hi, int s_reg);
35 virtual LIR* LoadBaseIndexed(CompilationUnit* cu, int rBase, int r_index, int r_dest, int scale,
36 OpSize size);
37 virtual LIR* LoadBaseIndexedDisp(CompilationUnit *cu, int rBase, int r_index, int scale,
38 int displacement, int r_dest, int r_dest_hi, OpSize size,
39 int s_reg);
40 virtual LIR* LoadConstantNoClobber(CompilationUnit* cu, int r_dest, int value);
41 virtual LIR* LoadConstantValueWide(CompilationUnit* cu, int r_dest_lo, int r_dest_hi,
42 int val_lo, int val_hi);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]43 virtual LIR* StoreBaseDisp(CompilationUnit* cu, int rBase, int displacement, int r_src,
44 OpSize size);
45 virtual LIR* StoreBaseDispWide(CompilationUnit* cu, int rBase, int displacement, int r_src_lo,
46 int r_src_hi);
47 virtual LIR* StoreBaseIndexed(CompilationUnit* cu, int rBase, int r_index, int r_src, int scale,
48 OpSize size);
49 virtual LIR* StoreBaseIndexedDisp(CompilationUnit *cu, int rBase, int r_index, int scale,
50 int displacement, int r_src, int r_src_hi, OpSize size,
51 int s_reg);
52 virtual void MarkGCCard(CompilationUnit* cu, int val_reg, int tgt_addr_reg);
53
54 // Required for target - register utilities.
55 virtual bool IsFpReg(int reg);
56 virtual bool SameRegType(int reg1, int reg2);
57 virtual int AllocTypedTemp(CompilationUnit* cu, bool fp_hint, int reg_class);
58 virtual int AllocTypedTempPair(CompilationUnit* cu, bool fp_hint, int reg_class);
59 virtual int S2d(int low_reg, int high_reg);
60 virtual int TargetReg(SpecialTargetRegister reg);
61 virtual RegisterInfo* GetRegInfo(CompilationUnit* cu, int reg);
62 virtual RegLocation GetReturnAlt(CompilationUnit* cu);
63 virtual RegLocation GetReturnWideAlt(CompilationUnit* cu);
64 virtual RegLocation LocCReturn();
65 virtual RegLocation LocCReturnDouble();
66 virtual RegLocation LocCReturnFloat();
67 virtual RegLocation LocCReturnWide();
68 virtual uint32_t FpRegMask();
69 virtual uint64_t GetRegMaskCommon(CompilationUnit* cu, int reg);
70 virtual void AdjustSpillMask(CompilationUnit* cu);
71 virtual void ClobberCalleeSave(CompilationUnit *cu);
72 virtual void FlushReg(CompilationUnit* cu, int reg);
73 virtual void FlushRegWide(CompilationUnit* cu, int reg1, int reg2);
74 virtual void FreeCallTemps(CompilationUnit* cu);
75 virtual void FreeRegLocTemps(CompilationUnit* cu, RegLocation rl_keep, RegLocation rl_free);
76 virtual void LockCallTemps(CompilationUnit* cu);
77 virtual void MarkPreservedSingle(CompilationUnit* cu, int v_reg, int reg);
78 virtual void CompilerInitializeRegAlloc(CompilationUnit* cu);
79
80 // Required for target - miscellaneous.
81 virtual AssemblerStatus AssembleInstructions(CompilationUnit* cu, uintptr_t start_addr);
82 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix);
83 virtual void SetupTargetResourceMasks(CompilationUnit* cu, LIR* lir);
84 virtual const char* GetTargetInstFmt(int opcode);
85 virtual const char* GetTargetInstName(int opcode);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]86 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
87 virtual uint64_t GetPCUseDefEncoding();
88 virtual uint64_t GetTargetInstFlags(int opcode);
89 virtual int GetInsnSize(LIR* lir);
90 virtual bool IsUnconditionalBranch(LIR* lir);
91
92 // Required for target - Dalvik-level generators.
buzbeee6285f92012-12-06 15:57:46 -0800[diff] [blame]93 virtual void GenArrayObjPut(CompilationUnit* cu, int opt_flags, RegLocation rl_array,
94 RegLocation rl_index, RegLocation rl_src, int scale);
95 virtual void GenArrayGet(CompilationUnit* cu, int opt_flags, OpSize size, RegLocation rl_array,
96 RegLocation rl_index, RegLocation rl_dest, int scale);
97 virtual void GenArrayPut(CompilationUnit* cu, int opt_flags, OpSize size, RegLocation rl_array,
98 RegLocation rl_index, RegLocation rl_src, int scale);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]99 virtual bool GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
100 RegLocation rl_src2);
101 virtual bool GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
102 RegLocation rl_src2);
103 virtual bool GenArithOpDouble(CompilationUnit* cu, Instruction::Code opcode,
104 RegLocation rl_dest, RegLocation rl_src1,
105 RegLocation rl_src2);
106 virtual bool GenArithOpFloat(CompilationUnit *cu, Instruction::Code opcode, RegLocation rl_dest,
107 RegLocation rl_src1, RegLocation rl_src2);
108 virtual bool GenCmpFP(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
109 RegLocation rl_src1, RegLocation rl_src2);
110 virtual bool GenConversion(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest,
111 RegLocation rl_src);
112 virtual bool GenInlinedCas32(CompilationUnit* cu, CallInfo* info, bool need_write_barrier);
113 virtual bool GenInlinedMinMaxInt(CompilationUnit *cu, CallInfo* info, bool is_min);
114 virtual bool GenInlinedSqrt(CompilationUnit* cu, CallInfo* info);
115 virtual bool GenNegLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
116 virtual bool GenOrLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
117 RegLocation rl_src2);
118 virtual bool GenSubLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
119 RegLocation rl_src2);
120 virtual bool GenXorLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
121 RegLocation rl_src2);
122 virtual LIR* GenRegMemCheck(CompilationUnit* cu, ConditionCode c_code, int reg1, int base,
123 int offset, ThrowKind kind);
124 virtual RegLocation GenDivRem(CompilationUnit* cu, RegLocation rl_dest, int reg_lo, int reg_hi,
125 bool is_div);
126 virtual RegLocation GenDivRemLit(CompilationUnit* cu, RegLocation rl_dest, int reg_lo, int lit,
127 bool is_div);
128 virtual void GenCmpLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1,
129 RegLocation rl_src2);
130 virtual void GenDivZeroCheck(CompilationUnit* cu, int reg_lo, int reg_hi);
131 virtual void GenEntrySequence(CompilationUnit* cu, RegLocation* ArgLocs,
132 RegLocation rl_method);
133 virtual void GenExitSequence(CompilationUnit* cu);
134 virtual void GenFillArrayData(CompilationUnit* cu, uint32_t table_offset,
135 RegLocation rl_src);
136 virtual void GenFusedFPCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir, bool gt_bias,
137 bool is_double);
138 virtual void GenFusedLongCmpBranch(CompilationUnit* cu, BasicBlock* bb, MIR* mir);
139 virtual void GenMemBarrier(CompilationUnit* cu, MemBarrierKind barrier_kind);
140 virtual void GenMonitorEnter(CompilationUnit* cu, int opt_flags, RegLocation rl_src);
141 virtual void GenMonitorExit(CompilationUnit* cu, int opt_flags, RegLocation rl_src);
jeffhao1eab9582013-01-22 13:33:52 -0800[diff] [blame]142 virtual void GenMoveException(CompilationUnit* cu, RegLocation rl_dest);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]143 virtual void GenMultiplyByTwoBitMultiplier(CompilationUnit* cu, RegLocation rl_src,
144 RegLocation rl_result, int lit, int first_bit,
145 int second_bit);
146 virtual void GenNegDouble(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
147 virtual void GenNegFloat(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src);
148 virtual void GenPackedSwitch(CompilationUnit* cu, uint32_t table_offset,
149 RegLocation rl_src);
150 virtual void GenSparseSwitch(CompilationUnit* cu, uint32_t table_offset,
151 RegLocation rl_src);
152 virtual void GenSpecialCase(CompilationUnit* cu, BasicBlock* bb, MIR* mir,
153 SpecialCaseHandler special_case);
154
155 // Single operation generators.
156 virtual LIR* OpUnconditionalBranch(CompilationUnit* cu, LIR* target);
157 virtual LIR* OpCmpBranch(CompilationUnit* cu, ConditionCode cond, int src1, int src2,
158 LIR* target);
159 virtual LIR* OpCmpImmBranch(CompilationUnit* cu, ConditionCode cond, int reg, int check_value,
160 LIR* target);
161 virtual LIR* OpCondBranch(CompilationUnit* cu, ConditionCode cc, LIR* target);
162 virtual LIR* OpDecAndBranch(CompilationUnit* cu, ConditionCode c_code, int reg,
163 LIR* target);
164 virtual LIR* OpFpRegCopy(CompilationUnit* cu, int r_dest, int r_src);
165 virtual LIR* OpIT(CompilationUnit* cu, ConditionCode cond, const char* guide);
166 virtual LIR* OpMem(CompilationUnit* cu, OpKind op, int rBase, int disp);
167 virtual LIR* OpPcRelLoad(CompilationUnit* cu, int reg, LIR* target);
168 virtual LIR* OpReg(CompilationUnit* cu, OpKind op, int r_dest_src);
169 virtual LIR* OpRegCopy(CompilationUnit* cu, int r_dest, int r_src);
170 virtual LIR* OpRegCopyNoInsert(CompilationUnit* cu, int r_dest, int r_src);
171 virtual LIR* OpRegImm(CompilationUnit* cu, OpKind op, int r_dest_src1, int value);
172 virtual LIR* OpRegMem(CompilationUnit* cu, OpKind op, int r_dest, int rBase, int offset);
173 virtual LIR* OpRegReg(CompilationUnit* cu, OpKind op, int r_dest_src1, int r_src2);
174 virtual LIR* OpRegRegImm(CompilationUnit* cu, OpKind op, int r_dest, int r_src1, int value);
175 virtual LIR* OpRegRegReg(CompilationUnit* cu, OpKind op, int r_dest, int r_src1,
176 int r_src2);
177 virtual LIR* OpTestSuspend(CompilationUnit* cu, LIR* target);
178 virtual LIR* OpThreadMem(CompilationUnit* cu, OpKind op, int thread_offset);
179 virtual LIR* OpVldm(CompilationUnit* cu, int rBase, int count);
180 virtual LIR* OpVstm(CompilationUnit* cu, int rBase, int count);
181 virtual void OpLea(CompilationUnit* cu, int rBase, int reg1, int reg2, int scale,
182 int offset);
183 virtual void OpRegCopyWide(CompilationUnit* cu, int dest_lo, int dest_hi, int src_lo,
184 int src_hi);
185 virtual void OpTlsCmp(CompilationUnit* cu, int offset, int val);
186
187 void OpRegThreadMem(CompilationUnit* cu, OpKind op, int r_dest, int thread_offset);
188 void SpillCoreRegs(CompilationUnit* cu);
189 void UnSpillCoreRegs(CompilationUnit* cu);
190 static const X86EncodingMap EncodingMap[kX86Last];
buzbeee6285f92012-12-06 15:57:46 -0800[diff] [blame]191 bool InexpensiveConstant(int reg, int value);
buzbee02031b12012-11-23 09:41:35 -0800[diff] [blame]192};
193
194} // namespace art
195
196#endif // ART_SRC_COMPILER_CODEGEN_X86_CODEGENX86_H_