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review.blissroms.org / platform_art / 5bd05a5c9492189ec28edaf6396d6a39ddf03367 / . / compiler / utils / arm / assembler_arm32.h
blob: b40c0930ce6e49ccb4925fa32880e32cc4f77607 [file] [log] [blame]
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]1/*
2 * Copyright (C) 2014 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_UTILS_ARM_ASSEMBLER_ARM32_H_
18#define ART_COMPILER_UTILS_ARM_ASSEMBLER_ARM32_H_
19
20#include <vector>
21
22#include "base/logging.h"
23#include "constants_arm.h"
24#include "utils/arm/managed_register_arm.h"
25#include "utils/arm/assembler_arm.h"
26#include "offsets.h"
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]27
28namespace art {
29namespace arm {
30
31class Arm32Assembler FINAL : public ArmAssembler {
32 public:
33 Arm32Assembler() {
34 }
35 virtual ~Arm32Assembler() {}
36
37 bool IsThumb() const OVERRIDE {
38 return false;
39 }
40
41 // Data-processing instructions.
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]42 virtual void and_(Register rd, Register rn, const ShifterOperand& so,
43 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]44
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]45 virtual void eor(Register rd, Register rn, const ShifterOperand& so,
46 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]47
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]48 virtual void sub(Register rd, Register rn, const ShifterOperand& so,
49 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]50
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]51 virtual void rsb(Register rd, Register rn, const ShifterOperand& so,
52 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]53
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]54 virtual void add(Register rd, Register rn, const ShifterOperand& so,
55 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]56
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]57 virtual void adc(Register rd, Register rn, const ShifterOperand& so,
58 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]59
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]60 virtual void sbc(Register rd, Register rn, const ShifterOperand& so,
61 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]62
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]63 virtual void rsc(Register rd, Register rn, const ShifterOperand& so,
64 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]65
66 void tst(Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
67
68 void teq(Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
69
70 void cmp(Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
71
72 void cmn(Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
73
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]74 virtual void orr(Register rd, Register rn, const ShifterOperand& so,
75 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]76
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]77 virtual void mov(Register rd, const ShifterOperand& so,
78 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]79
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]80 virtual void bic(Register rd, Register rn, const ShifterOperand& so,
81 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]82
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]83 virtual void mvn(Register rd, const ShifterOperand& so,
84 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]85
86 // Miscellaneous data-processing instructions.
87 void clz(Register rd, Register rm, Condition cond = AL) OVERRIDE;
88 void movw(Register rd, uint16_t imm16, Condition cond = AL) OVERRIDE;
89 void movt(Register rd, uint16_t imm16, Condition cond = AL) OVERRIDE;
Scott Wakeling9ee23f42015-07-23 10:44:35 +0100[diff] [blame]90 void rbit(Register rd, Register rm, Condition cond = AL) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]91
92 // Multiply instructions.
93 void mul(Register rd, Register rn, Register rm, Condition cond = AL) OVERRIDE;
94 void mla(Register rd, Register rn, Register rm, Register ra,
95 Condition cond = AL) OVERRIDE;
96 void mls(Register rd, Register rn, Register rm, Register ra,
97 Condition cond = AL) OVERRIDE;
Zheng Xuc6667102015-05-15 16:08:45 +0800[diff] [blame]98 void smull(Register rd_lo, Register rd_hi, Register rn, Register rm,
99 Condition cond = AL) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]100 void umull(Register rd_lo, Register rd_hi, Register rn, Register rm,
101 Condition cond = AL) OVERRIDE;
102
103 void sdiv(Register rd, Register rn, Register rm, Condition cond = AL) OVERRIDE;
104 void udiv(Register rd, Register rn, Register rm, Condition cond = AL) OVERRIDE;
105
Roland Levillain981e4542014-11-14 11:47:14 +0000[diff] [blame]106 // Bit field extract instructions.
Roland Levillain51d3fc42014-11-13 14:11:42 +0000[diff] [blame]107 void sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond = AL) OVERRIDE;
Roland Levillain981e4542014-11-14 11:47:14 +0000[diff] [blame]108 void ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond = AL) OVERRIDE;
Roland Levillain51d3fc42014-11-13 14:11:42 +0000[diff] [blame]109
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]110 // Load/store instructions.
111 void ldr(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
112 void str(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
113
114 void ldrb(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
115 void strb(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
116
117 void ldrh(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
118 void strh(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
119
120 void ldrsb(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
121 void ldrsh(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
122
123 void ldrd(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
124 void strd(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
125
126 void ldm(BlockAddressMode am, Register base,
127 RegList regs, Condition cond = AL) OVERRIDE;
128 void stm(BlockAddressMode am, Register base,
129 RegList regs, Condition cond = AL) OVERRIDE;
130
131 void ldrex(Register rd, Register rn, Condition cond = AL) OVERRIDE;
132 void strex(Register rd, Register rt, Register rn, Condition cond = AL) OVERRIDE;
Calin Juravle52c48962014-12-16 17:02:57 +0000[diff] [blame]133 void ldrexd(Register rt, Register rt2, Register rn, Condition cond = AL) OVERRIDE;
134 void strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond = AL) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]135
136 // Miscellaneous instructions.
137 void clrex(Condition cond = AL) OVERRIDE;
138 void nop(Condition cond = AL) OVERRIDE;
139
140 // Note that gdb sets breakpoints using the undefined instruction 0xe7f001f0.
141 void bkpt(uint16_t imm16) OVERRIDE;
142 void svc(uint32_t imm24) OVERRIDE;
143
144 void cbz(Register rn, Label* target) OVERRIDE;
145 void cbnz(Register rn, Label* target) OVERRIDE;
146
147 // Floating point instructions (VFPv3-D16 and VFPv3-D32 profiles).
148 void vmovsr(SRegister sn, Register rt, Condition cond = AL) OVERRIDE;
149 void vmovrs(Register rt, SRegister sn, Condition cond = AL) OVERRIDE;
150 void vmovsrr(SRegister sm, Register rt, Register rt2, Condition cond = AL) OVERRIDE;
151 void vmovrrs(Register rt, Register rt2, SRegister sm, Condition cond = AL) OVERRIDE;
152 void vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond = AL) OVERRIDE;
153 void vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond = AL) OVERRIDE;
154 void vmovs(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
155 void vmovd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE;
156
157 // Returns false if the immediate cannot be encoded.
158 bool vmovs(SRegister sd, float s_imm, Condition cond = AL) OVERRIDE;
159 bool vmovd(DRegister dd, double d_imm, Condition cond = AL) OVERRIDE;
160
161 void vldrs(SRegister sd, const Address& ad, Condition cond = AL) OVERRIDE;
162 void vstrs(SRegister sd, const Address& ad, Condition cond = AL) OVERRIDE;
163 void vldrd(DRegister dd, const Address& ad, Condition cond = AL) OVERRIDE;
164 void vstrd(DRegister dd, const Address& ad, Condition cond = AL) OVERRIDE;
165
166 void vadds(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE;
167 void vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE;
168 void vsubs(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE;
169 void vsubd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE;
170 void vmuls(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE;
171 void vmuld(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE;
172 void vmlas(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE;
173 void vmlad(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE;
174 void vmlss(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE;
175 void vmlsd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE;
176 void vdivs(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE;
177 void vdivd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE;
178
179 void vabss(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
180 void vabsd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE;
181 void vnegs(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
182 void vnegd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE;
183 void vsqrts(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
184 void vsqrtd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE;
185
186 void vcvtsd(SRegister sd, DRegister dm, Condition cond = AL) OVERRIDE;
187 void vcvtds(DRegister dd, SRegister sm, Condition cond = AL) OVERRIDE;
188 void vcvtis(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
189 void vcvtid(SRegister sd, DRegister dm, Condition cond = AL) OVERRIDE;
190 void vcvtsi(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
191 void vcvtdi(DRegister dd, SRegister sm, Condition cond = AL) OVERRIDE;
192 void vcvtus(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
193 void vcvtud(SRegister sd, DRegister dm, Condition cond = AL) OVERRIDE;
194 void vcvtsu(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
195 void vcvtdu(DRegister dd, SRegister sm, Condition cond = AL) OVERRIDE;
196
197 void vcmps(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
198 void vcmpd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE;
199 void vcmpsz(SRegister sd, Condition cond = AL) OVERRIDE;
200 void vcmpdz(DRegister dd, Condition cond = AL) OVERRIDE;
201 void vmstat(Condition cond = AL) OVERRIDE; // VMRS APSR_nzcv, FPSCR
202
203 void vpushs(SRegister reg, int nregs, Condition cond = AL) OVERRIDE;
204 void vpushd(DRegister reg, int nregs, Condition cond = AL) OVERRIDE;
205 void vpops(SRegister reg, int nregs, Condition cond = AL) OVERRIDE;
206 void vpopd(DRegister reg, int nregs, Condition cond = AL) OVERRIDE;
207
208 // Branch instructions.
Nicolas Geoffrayd56376c2015-05-21 12:32:34 +0000[diff] [blame]209 void b(Label* label, Condition cond = AL) OVERRIDE;
210 void bl(Label* label, Condition cond = AL) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]211 void blx(Register rm, Condition cond = AL) OVERRIDE;
212 void bx(Register rm, Condition cond = AL) OVERRIDE;
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]213 virtual void Lsl(Register rd, Register rm, uint32_t shift_imm,
214 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
215 virtual void Lsr(Register rd, Register rm, uint32_t shift_imm,
216 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
217 virtual void Asr(Register rd, Register rm, uint32_t shift_imm,
218 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
219 virtual void Ror(Register rd, Register rm, uint32_t shift_imm,
220 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
221 virtual void Rrx(Register rd, Register rm,
222 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison45fdb932014-06-25 12:37:10 -0700[diff] [blame]223
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]224 virtual void Lsl(Register rd, Register rm, Register rn,
225 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
226 virtual void Lsr(Register rd, Register rm, Register rn,
227 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
228 virtual void Asr(Register rd, Register rm, Register rn,
229 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
230 virtual void Ror(Register rd, Register rm, Register rn,
231 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]232
233 void Push(Register rd, Condition cond = AL) OVERRIDE;
234 void Pop(Register rd, Condition cond = AL) OVERRIDE;
235
236 void PushList(RegList regs, Condition cond = AL) OVERRIDE;
237 void PopList(RegList regs, Condition cond = AL) OVERRIDE;
238
239 void Mov(Register rd, Register rm, Condition cond = AL) OVERRIDE;
240
241 void CompareAndBranchIfZero(Register r, Label* label) OVERRIDE;
242 void CompareAndBranchIfNonZero(Register r, Label* label) OVERRIDE;
243
Nicolas Geoffray19a19cf2014-10-22 16:07:05 +0100[diff] [blame]244 // Memory barriers.
245 void dmb(DmbOptions flavor) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]246
Vladimir Markocf93a5c2015-06-16 11:33:24 +0000[diff] [blame]247 // Get the final position of a label after local fixup based on the old position
248 // recorded before FinalizeCode().
249 uint32_t GetAdjustedPosition(uint32_t old_position) OVERRIDE;
250
251 Literal* NewLiteral(size_t size, const uint8_t* data) OVERRIDE;
252 void LoadLiteral(Register rt, Literal* literal) OVERRIDE;
253 void LoadLiteral(Register rt, Register rt2, Literal* literal) OVERRIDE;
254 void LoadLiteral(SRegister sd, Literal* literal) OVERRIDE;
255 void LoadLiteral(DRegister dd, Literal* literal) OVERRIDE;
256
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]257 // Add signed constant value to rd. May clobber IP.
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]258 void AddConstant(Register rd, Register rn, int32_t value,
Vladimir Marko449b1092015-09-08 12:16:45 +0100[diff] [blame]259 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]260
261 // Load and Store. May clobber IP.
262 void LoadImmediate(Register rd, int32_t value, Condition cond = AL) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]263 void MarkExceptionHandler(Label* label) OVERRIDE;
264 void LoadFromOffset(LoadOperandType type,
265 Register reg,
266 Register base,
267 int32_t offset,
268 Condition cond = AL) OVERRIDE;
269 void StoreToOffset(StoreOperandType type,
270 Register reg,
271 Register base,
272 int32_t offset,
273 Condition cond = AL) OVERRIDE;
274 void LoadSFromOffset(SRegister reg,
275 Register base,
276 int32_t offset,
277 Condition cond = AL) OVERRIDE;
278 void StoreSToOffset(SRegister reg,
279 Register base,
280 int32_t offset,
281 Condition cond = AL) OVERRIDE;
282 void LoadDFromOffset(DRegister reg,
283 Register base,
284 int32_t offset,
285 Condition cond = AL) OVERRIDE;
286 void StoreDToOffset(DRegister reg,
287 Register base,
288 int32_t offset,
289 Condition cond = AL) OVERRIDE;
290
Nicolas Geoffray3bcc8ea2014-11-28 15:00:02 +0000[diff] [blame]291 bool ShifterOperandCanHold(Register rd,
292 Register rn,
293 Opcode opcode,
294 uint32_t immediate,
295 ShifterOperand* shifter_op) OVERRIDE;
296
Nicolas Geoffray5bd05a52015-10-13 09:48:30 +0100[diff] [blame^]297 bool ShifterOperandCanAlwaysHold(uint32_t immediate) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]298
Ian Rogers13735952014-10-08 12:43:28 -0700[diff] [blame]299 static bool IsInstructionForExceptionHandling(uintptr_t pc);
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]300
301 // Emit data (e.g. encoded instruction or immediate) to the
302 // instruction stream.
303 void Emit(int32_t value);
304 void Bind(Label* label) OVERRIDE;
305
306 void MemoryBarrier(ManagedRegister scratch) OVERRIDE;
307
308 private:
309 void EmitType01(Condition cond,
310 int type,
311 Opcode opcode,
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]312 SetCc set_cc,
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]313 Register rn,
314 Register rd,
315 const ShifterOperand& so);
316
317 void EmitType5(Condition cond, int offset, bool link);
318
319 void EmitMemOp(Condition cond,
320 bool load,
321 bool byte,
322 Register rd,
323 const Address& ad);
324
325 void EmitMemOpAddressMode3(Condition cond,
326 int32_t mode,
327 Register rd,
328 const Address& ad);
329
330 void EmitMultiMemOp(Condition cond,
331 BlockAddressMode am,
332 bool load,
333 Register base,
334 RegList regs);
335
336 void EmitShiftImmediate(Condition cond,
337 Shift opcode,
338 Register rd,
339 Register rm,
340 const ShifterOperand& so);
341
342 void EmitShiftRegister(Condition cond,
343 Shift opcode,
344 Register rd,
345 Register rm,
346 const ShifterOperand& so);
347
348 void EmitMulOp(Condition cond,
349 int32_t opcode,
350 Register rd,
351 Register rn,
352 Register rm,
353 Register rs);
354
355 void EmitVFPsss(Condition cond,
356 int32_t opcode,
357 SRegister sd,
358 SRegister sn,
359 SRegister sm);
360
361 void EmitVFPddd(Condition cond,
362 int32_t opcode,
363 DRegister dd,
364 DRegister dn,
365 DRegister dm);
366
367 void EmitVFPsd(Condition cond,
368 int32_t opcode,
369 SRegister sd,
370 DRegister dm);
371
372 void EmitVFPds(Condition cond,
373 int32_t opcode,
374 DRegister dd,
375 SRegister sm);
376
377 void EmitVPushPop(uint32_t reg, int nregs, bool push, bool dbl, Condition cond);
378
379 void EmitBranch(Condition cond, Label* label, bool link);
380 static int32_t EncodeBranchOffset(int offset, int32_t inst);
381 static int DecodeBranchOffset(int32_t inst);
382 int32_t EncodeTstOffset(int offset, int32_t inst);
383 int DecodeTstOffset(int32_t inst);
Nicolas Geoffray3bcc8ea2014-11-28 15:00:02 +0000[diff] [blame]384 bool ShifterOperandCanHoldArm32(uint32_t immediate, ShifterOperand* shifter_op);
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]385};
386
387} // namespace arm
388} // namespace art
389
390#endif // ART_COMPILER_UTILS_ARM_ASSEMBLER_ARM32_H_