Blame - src/compiler/codegen/x86/Assemble.cc - platform_art

2012-03-05 19:51:02 -0800

[diff] [blame]

84

0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */,

85

0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */,

86

0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */,

87

0x80, 0x0 /* RegMem8/imm8 */,

88

0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */),

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

89

ENCODING_MAP(Or,

Ian Rogers

2012-03-05 19:51:02 -0800

[diff] [blame]

90

0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */,

91

0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */,

92

0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */,

93

0x80, 0x1 /* RegMem8/imm8 */,

94

0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */),

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

95

ENCODING_MAP(Adc,

Ian Rogers

2012-03-05 19:51:02 -0800

[diff] [blame]

96

0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */,

97

0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */,

98

0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */,

99

0x80, 0x2 /* RegMem8/imm8 */,

100

0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */),

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

101

ENCODING_MAP(Sbb,

Ian Rogers

2012-03-05 19:51:02 -0800

[diff] [blame]

102

0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */,

103

0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */,

104

0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */,

105

0x80, 0x3 /* RegMem8/imm8 */,

106

0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */),

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

107

ENCODING_MAP(And,

Ian Rogers

2012-03-05 19:51:02 -0800

[diff] [blame]

108

0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */,

109

0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */,

110

0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */,

111

0x80, 0x4 /* RegMem8/imm8 */,

112

0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */),

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

113

ENCODING_MAP(Sub,

Ian Rogers

2012-03-05 19:51:02 -0800

[diff] [blame]

114

0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */,

115

0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */,

116

0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */,

117

0x80, 0x5 /* RegMem8/imm8 */,

118

0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */),

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

119

ENCODING_MAP(Xor,

Ian Rogers

2012-03-05 19:51:02 -0800

[diff] [blame]

120

0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */,

121

0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */,

122

0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */,

123

0x80, 0x6 /* RegMem8/imm8 */,

124

0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */),

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

125

ENCODING_MAP(Cmp,

Ian Rogers

2012-03-05 19:51:02 -0800

[diff] [blame]

126

0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */,

127

0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */,

128

0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */,

129

0x80, 0x7 /* RegMem8/imm8 */,

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

130

0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */),

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

131

#undef ENCODING_MAP

132

133

{ kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RRI", "" },

134

{ kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RMI", "" },

135

{ kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RAI", "" },

136

137

{ kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul32RRI", "" },

138

{ kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul32RMI", "" },

139

{ kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul32RAI", "" },

140

{ kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RRI8", "" },

141

{ kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RMI8", "" },

142

{ kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RAI8", "" },

143

144

{ kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8MR", "[!0r+!1d],!2r" },

145

{ kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" },

146

{ kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8TR", "fs:[!0d],!1r" },

147

{ kX86Mov8RR, kRegReg, IS_BINARY_OP, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RR", "!0r,!1r" },

148

{ kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RM", "!0r,[!1r+!2d]" },

149

{ kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" },

150

{ kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RT", "!0r,fs:[!1d]" },

151

{ kX86Mov8RI, kMovRegImm, IS_BINARY_OP, { 0, 0, 0xB0, 0, 0, 0, 0, 1 }, "Mov8RI", "!0r,!1d" },

152

{ kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8MI", "[!0r+!1d],!2r" },

153

{ kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" },

154

{ kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8TI", "fs:[!0d],!1d" },

155

156

{ kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16MR", "[!0r+!1d],!2r" },

157

{ kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" },

158

{ kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0 }, "Mov16TR", "fs:[!0d],!1r" },

159

{ kX86Mov16RR, kRegReg, IS_BINARY_OP, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RR", "!0r,!1r" },

160

{ kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RM", "!0r,[!1r+!2d]" },

161

{ kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" },

162

{ kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RT", "!0r,fs:[!1d]" },

163

{ kX86Mov16RI, kMovRegImm, IS_BINARY_OP, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2 }, "Mov16RI", "!0r,!1d" },

164

{ kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16MI", "[!0r+!1d],!2r" },

165

{ kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" },

166

{ kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2 }, "Mov16TI", "fs:[!0d],!1d" },

167

168

{ kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32MR", "[!0r+!1d],!2r" },

169

{ kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" },

170

{ kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32TR", "fs:[!0d],!1r" },

171

{ kX86Mov32RR, kRegReg, IS_BINARY_OP, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RR", "!0r,!1r" },

172

{ kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RM", "!0r,[!1r+!2d]" },

173

{ kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

174

{ kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RT", "!0r,fs:[!1d]" },

175

{ kX86Mov32RI, kMovRegImm, IS_BINARY_OP, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "Mov32RI", "!0r,!1d" },

176

{ kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32MI", "[!0r+!1d],!2r" },

177

{ kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" },

178

{ kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32TI", "fs:[!0d],!1d" },

179

180

{ kX86Lea32RA, kRegArray, IS_QUIN_OP, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

181

182

#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \

183

{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \

184

{ kX86 ## opname ## 8MI, kShiftMemImm, IS_TERTIARY_OP | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2r" }, \

185

{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_QUIN_OP | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

186

{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "" }, \

187

{ kX86 ## opname ## 8MC, kShiftMemCl, IS_TERTIARY_OP | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "" }, \

188

{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_QUIN_OP | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "" }, \

189

\

190

{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \

191

{ kX86 ## opname ## 16MI, kShiftMemImm, IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2r" }, \

192

{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_QUIN_OP | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

193

{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "" }, \

194

{ kX86 ## opname ## 16MC, kShiftMemCl, IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "" }, \

195

{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_QUIN_OP | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "" }, \

196

\

197

{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \

198

{ kX86 ## opname ## 32MI, kShiftMemImm, IS_TERTIARY_OP | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2r" }, \

199

{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_QUIN_OP | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

200

{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "32RC", "" }, \

201

{ kX86 ## opname ## 32MC, kShiftMemCl, IS_TERTIARY_OP | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "32MC", "" }, \

202

{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_QUIN_OP | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "32AC", "" }

203

204

SHIFT_ENCODING_MAP(Rol, 0x0),

205

SHIFT_ENCODING_MAP(Ror, 0x1),

206

SHIFT_ENCODING_MAP(Rcl, 0x2),

207

SHIFT_ENCODING_MAP(Rcr, 0x3),

208

SHIFT_ENCODING_MAP(Sal, 0x4),

209

SHIFT_ENCODING_MAP(Shl, 0x5),

210

SHIFT_ENCODING_MAP(Shr, 0x6),

211

SHIFT_ENCODING_MAP(Sar, 0x7),

212

#undef SHIFT_ENCODING_MAP

213

214

#define UNARY_ENCODING_MAP(opname, modrm, \

215

reg, reg_kind, reg_flags, \

216

mem, mem_kind, mem_flags, \

217

arr, arr_kind, arr_flags, imm) \

218

{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, "" }, \

219

{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | mem_flags, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, "" }, \

220

{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | arr_flags, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, "" }, \

221

{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, "" }, \

222

{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | mem_flags, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, "" }, \

223

{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | arr_flags, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, "" }, \

224

{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, "" }, \

225

{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | mem_flags, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, "" }, \

226

{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | arr_flags, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, "" }

227

228

UNARY_ENCODING_MAP(Test, 0x0, RI, kRegImm, IS_BINARY_OP, MI, kMemImm, IS_TERTIARY_OP, AI, kArrayImm, IS_QUIN_OP, 1),

229

UNARY_ENCODING_MAP(Not, 0x2, R, kReg, IS_UNARY_OP, M, kMem, IS_BINARY_OP, A, kArray, IS_QUAD_OP, 0),

230

UNARY_ENCODING_MAP(Neg, 0x3, R, kReg, IS_UNARY_OP, M, kMem, IS_BINARY_OP, A, kArray, IS_QUAD_OP, 0),

231

UNARY_ENCODING_MAP(Mul, 0x4, DaR, kRegRegReg, IS_TERTIARY_OP, DaM, kRegRegMem, IS_QUAD_OP, DaA, kRegRegArray, IS_SEXTUPLE_OP, 0),

232

UNARY_ENCODING_MAP(Imul, 0x5, DaR, kRegRegReg, IS_TERTIARY_OP, DaM, kRegRegMem, IS_QUAD_OP, DaA, kRegRegArray, IS_SEXTUPLE_OP, 0),

233

UNARY_ENCODING_MAP(Divmod, 0x6, DaR, kRegRegReg, IS_TERTIARY_OP, DaM, kRegRegMem, IS_QUAD_OP, DaA, kRegRegArray, IS_SEXTUPLE_OP, 0),

234

UNARY_ENCODING_MAP(Idivmod, 0x7, DaR, kRegRegReg, IS_TERTIARY_OP, DaM, kRegRegMem, IS_QUAD_OP, DaA, kRegRegArray, IS_SEXTUPLE_OP, 0),

235

#undef UNARY_ENCODING_MAP

236

237

#define EXT_0F_ENCODING_MAP(opname, prefix, opcode) \

238

{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

239

{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

240

{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

241

242

EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10),

243

{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

244

{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

245

246

EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10),

247

{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

248

{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

249

250

EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A),

251

EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A),

252

EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C),

253

EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C),

254

EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D),

255

EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D),

256

EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E),

257

EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E),

258

EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F),

259

EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F),

260

EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58),

261

EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58),

262

EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59),

263

EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59),

264

EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF2, 0x5A),

265

EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF3, 0x5A),

266

EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C),

267

EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C),

268

EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E),

269

EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E),

270

271

EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E),

272

EXT_0F_ENCODING_MAP(Movdrx, 0x66, 0x7E),

273

274

{ kX86Set8R, kRegCond, IS_BINARY_OP, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

275

{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

276

{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

277

278

EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF),

279

EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF),

280

EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6),

281

EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7),

282

EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE),

283

EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF),

284

#undef EXT_0F_ENCODING_MAP

285

Ian Rogers

6cbb2bd

2012-03-16 13:45:30 -0700

[diff] [blame^]

286

{ kX86Jcc, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc", "!1c" },

287

{ kX86Jmp, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp", "" },

288

{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

289

{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

290

{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

291

{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

292

{ kX86Ret, kNullary,NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

293

};

294

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

295

static size_t computeSize(X86EncodingMap* entry, int displacement, bool has_sib) {

296

size_t size = 0;

297

if (entry->skeleton.prefix1 > 0) {

298

++size;

299

if (entry->skeleton.prefix2 > 0) {

300

++size;

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

301

}

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

302

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

303

++size; // opcode

304

if (entry->skeleton.opcode == 0x0F) {

305

++size;

306

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

if (has_sib) {

++size;

}

if (displacement != 0) {

315

if (entry->opcode != kX86Lea32RA) {

316

DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0);

317

}

318

size += IS_SIMM8(displacement) ? 1 : 4;

319

}

320

size += entry->skeleton.immediate_bytes;

return size;

}

int oatGetInsnSize(LIR* lir) {

325

X86EncodingMap* entry = &EncodingMap[lir->opcode];

326

switch (entry->kind) {

327

case kData:

328

return 4; // 4 bytes of data

329

case kNop:

330

return lir->operands[0]; // length of nop is sole operand

331

case kNullary:

332

return 1; // 1 byte of opcode

333

case kReg: // lir operands - 0: reg

334

return computeSize(entry, 0, false);

335

case kMem: { // lir operands - 0: base, 1: disp

336

int base = lir->operands[0];

337

// SP requires a special extra SIB byte

338

return computeSize(entry, lir->operands[1], false) + (base == rSP ? 1 : 0);

339

}

340

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

341

return computeSize(entry, lir->operands[3], true);

342

case kMemReg: { // lir operands - 0: base, 1: disp, 2: reg

343

int base = lir->operands[0];

344

// SP requires a special extra SIB byte

345

return computeSize(entry, lir->operands[1], false) + (base == rSP ? 1 : 0);

346

}

347

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

348

return computeSize(entry, lir->operands[3], true);

349

case kThreadReg: // lir operands - 0: disp, 1: reg

350

return computeSize(entry, lir->operands[0], false);

351

case kRegReg:

352

return computeSize(entry, 0, false);

353

case kRegMem: { // lir operands - 0: reg, 1: base, 2: disp

354

int base = lir->operands[1];

355

return computeSize(entry, lir->operands[2], false) + (base == rSP ? 1 : 0);

356

}

357

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

358

return computeSize(entry, lir->operands[4], true);

359

case kRegThread: // lir operands - 0: reg, 1: disp

360

return computeSize(entry, lir->operands[1], false);

361

case kRegImm: { // lir operands - 0: reg, 1: immediate

362

int reg = lir->operands[0];

363

// AX opcodes don't require the modrm byte.

364

return computeSize(entry, 0, false) - (reg == rAX ? 1 : 0);

365

}

366

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

367

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

368

return computeSize(entry, lir->operands[1], false);

369

case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

370

return computeSize(entry, lir->operands[3], true);

371

case kThreadImm: // lir operands - 0: disp, 1: imm

372

return computeSize(entry, lir->operands[0], false);

373

case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

374

return computeSize(entry, 0, false);

375

case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

376

CHECK_NE(lir->operands[1], static_cast<int>(rSP)); // TODO: add extra SIB byte

377

return computeSize(entry, lir->operands[2], false);

378

case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

379

return computeSize(entry, lir->operands[4], true);

380

case kMovRegImm: // lir operands - 0: reg, 1: immediate

381

return 1 + entry->skeleton.immediate_bytes;

382

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

383

// Shift by immediate one has a shorter opcode.

384

return computeSize(entry, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

385

case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

386

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

387

// Shift by immediate one has a shorter opcode.

388

return computeSize(entry, lir->operands[1], false) - (lir->operands[2] == 1 ? 1 : 0);

389

case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

390

// Shift by immediate one has a shorter opcode.

391

return computeSize(entry, lir->operands[3], true) - (lir->operands[4] == 1 ? 1 : 0);

392

case kShiftRegCl:

393

return computeSize(entry, 0, false);

394

case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

395

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

396

return computeSize(entry, lir->operands[1], false);

397

case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

398

return computeSize(entry, lir->operands[3], true);

399

case kRegCond: // lir operands - 0: reg, 1: cond

400

return computeSize(entry, 0, false);

401

case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

402

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

403

return computeSize(entry, lir->operands[1], false);

404

case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

405

return computeSize(entry, lir->operands[3], true);

406

case kJcc: case kJmp:

407

// Jumps only return the short form length, the correct length will be assigned to LIR

408

// flags.size during assembly.

409

return 2;

410

case kCall:

411

switch(lir->opcode) {

412

case kX86CallR: return 2; // opcode modrm

413

case kX86CallM: // lir operands - 0: base, 1: disp

414

return computeSize(entry, lir->operands[1], false);

415

case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

416

return computeSize(entry, lir->operands[3], true);

Ian Rogers

6cbb2bd

2012-03-16 13:45:30 -0700

[diff] [blame^]

417

case kX86CallT: // lir operands - 0: disp

418

return computeSize(entry, lir->operands[0], true);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

default:

break;

}

break;

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

427

return 0;

428

}

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

429

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

430

static uint8_t modrmForDisp(int disp) {

431

if (disp == 0) {

432

return 0;

433

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

static void emitDisp(CompilationUnit* cUnit, int disp) {

441

if (disp == 0) {

442

return;

443

} else if (IS_SIMM8(disp)) {

444

cUnit->codeBuffer.push_back(disp & 0xFF);

445

} else {

446

cUnit->codeBuffer.push_back(disp & 0xFF);

447

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

448

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

449

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

}

}

static void emitOpReg(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg) {

454

if (entry->skeleton.prefix1 != 0) {

455

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

456

if (entry->skeleton.prefix2 != 0) {

457

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

458

}

459

} else {

460

DCHECK_EQ(0, entry->skeleton.prefix2);

461

}

462

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

463

if (entry->skeleton.opcode == 0x0F) {

464

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

465

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

466

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

467

} else {

468

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

469

}

470

} else {

471

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

472

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

473

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

474

if (FPREG(reg)) {

475

reg = reg & FP_REG_MASK;

476

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

477

DCHECK_LT(reg, 8);

478

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

479

cUnit->codeBuffer.push_back(modrm);

480

DCHECK_EQ(0, entry->skeleton.ax_opcode);

481

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

482

}

483

484

static void emitOpMem(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t base, int disp) {

485

if (entry->skeleton.prefix1 != 0) {

486

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

487

if (entry->skeleton.prefix2 != 0) {

488

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

489

}

490

} else {

491

DCHECK_EQ(0, entry->skeleton.prefix2);

492

}

493

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

494

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

495

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

496

DCHECK_LT(entry->skeleton.modrm_opcode, 8);

497

DCHECK_LT(base, 8);

498

uint8_t modrm = (modrmForDisp(disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;

499

cUnit->codeBuffer.push_back(modrm);

500

emitDisp(cUnit, disp);

501

DCHECK_EQ(0, entry->skeleton.ax_opcode);

502

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

503

}

504

505

static void emitMemReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

506

uint8_t base, int disp, uint8_t reg) {

507

if (entry->skeleton.prefix1 != 0) {

508

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

509

if (entry->skeleton.prefix2 != 0) {

510

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

511

}

512

} else {

513

DCHECK_EQ(0, entry->skeleton.prefix2);

514

}

515

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

516

if (entry->skeleton.opcode == 0x0F) {

517

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

518

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

519

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

520

} else {

521

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

522

}

523

} else {

524

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

525

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

526

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

527

if (FPREG(reg)) {

528

reg = reg & FP_REG_MASK;

529

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

530

DCHECK_LT(reg, 8);

531

DCHECK_LT(base, 8);

532

uint8_t modrm = (modrmForDisp(disp) << 6) | (reg << 3) | base;

533

cUnit->codeBuffer.push_back(modrm);

534

if (base == rSP) {

535

// Special SIB for SP base

536

cUnit->codeBuffer.push_back(0 << 6 | (rSP << 3) | rSP);

537

}

538

emitDisp(cUnit, disp);

539

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

540

DCHECK_EQ(0, entry->skeleton.ax_opcode);

541

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

542

}

543

544

static void emitRegMem(CompilationUnit* cUnit, const X86EncodingMap* entry,

545

uint8_t reg, uint8_t base, int disp) {

546

// Opcode will flip operands.

547

emitMemReg(cUnit, entry, base, disp, reg);

548

}

549

550

static void emitRegArray(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg,

551

uint8_t base, uint8_t index, int scale, int disp) {

552

if (entry->skeleton.prefix1 != 0) {

553

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

554

if (entry->skeleton.prefix2 != 0) {

555

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

556

}

557

} else {

558

DCHECK_EQ(0, entry->skeleton.prefix2);

559

}

560

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

561

if (entry->skeleton.opcode == 0x0F) {

562

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

563

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

564

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

565

} else {

566

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

567

}

568

} else {

569

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

570

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

571

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

572

if (FPREG(reg)) {

573

reg = reg & FP_REG_MASK;

574

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

575

DCHECK_LT(reg, 8);

576

uint8_t modrm = (modrmForDisp(disp) << 6) | (reg << 3) | rSP;

577

cUnit->codeBuffer.push_back(modrm);

DCHECK_LT(scale, 4);

DCHECK_LT(index, 8);

DCHECK_LT(base, 8);

uint8_t sib = (scale << 6) | (index << 3) | base;

582

cUnit->codeBuffer.push_back(sib);

583

emitDisp(cUnit, disp);

584

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

585

DCHECK_EQ(0, entry->skeleton.ax_opcode);

586

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

587

}

588

589

static void emitRegReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

590

uint8_t reg1, uint8_t reg2) {

591

if (entry->skeleton.prefix1 != 0) {

592

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

593

if (entry->skeleton.prefix2 != 0) {

594

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

595

}

596

} else {

597

DCHECK_EQ(0, entry->skeleton.prefix2);

598

}

599

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

600

if (entry->skeleton.opcode == 0x0F) {

601

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

602

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

603

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

604

} else {

605

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

606

}

607

} else {

608

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

609

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

610

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

611

if (FPREG(reg1)) {

612

reg1 = reg1 & FP_REG_MASK;

613

}

614

if (FPREG(reg2)) {

615

reg2 = reg2 & FP_REG_MASK;

616

}

617

DCHECK_LT(reg1, 8);

618

DCHECK_LT(reg2, 8);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

619

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

620

cUnit->codeBuffer.push_back(modrm);

621

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

622

DCHECK_EQ(0, entry->skeleton.ax_opcode);

623

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

624

}

625

626

static void emitRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

627

uint8_t reg, int imm) {

628

if (entry->skeleton.prefix1 != 0) {

629

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

630

if (entry->skeleton.prefix2 != 0) {

631

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

632

}

633

} else {

634

DCHECK_EQ(0, entry->skeleton.prefix2);

635

}

636

if (reg == rAX && entry->skeleton.ax_opcode != 0) {

637

cUnit->codeBuffer.push_back(entry->skeleton.ax_opcode);

638

} else {

639

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

640

if (entry->skeleton.opcode == 0x0F) {

641

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

642

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

643

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

644

} else {

645

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

646

}

647

} else {

648

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

649

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

650

}

651

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

652

cUnit->codeBuffer.push_back(modrm);

653

}

654

switch (entry->skeleton.immediate_bytes) {

655

case 1:

656

DCHECK(IS_SIMM8(imm));

657

cUnit->codeBuffer.push_back(imm & 0xFF);

658

break;

659

case 2:

660

DCHECK(IS_SIMM16(imm));

661

cUnit->codeBuffer.push_back(imm & 0xFF);

662

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

663

break;

664

case 4:

665

cUnit->codeBuffer.push_back(imm & 0xFF);

666

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

667

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

668

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

669

break;

670

default:

671

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

672

<< ") for instruction: " << entry->name;

break;

}

}

Ian Rogers

2012-03-16 13:45:30 -0700

[diff] [blame^]

677

void emitUnimplemented(CompilationUnit* cUnit, const X86EncodingMap* entry, LIR* lir) {

678

UNIMPLEMENTED(WARNING) << "Unimplemented encoding for: " << entry->name;

Ian Rogers

141b0c7

2012-03-15 18:18:52 -0700

[diff] [blame]

679

for (int i = 0; i < oatGetInsnSize(lir); ++i) {

680

cUnit->codeBuffer.push_back(0xCC); // push breakpoint instruction - int 3

}

}

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

684

/*

685

* Assemble the LIR into binary instruction format. Note that we may

686

* discover that pc-relative displacements may not fit the selected

687

* instruction. In those cases we will try to substitute a new code

688

* sequence or request that the trace be shortened and retried.

689

*/

690

AssemblerStatus oatAssembleInstructions(CompilationUnit *cUnit,

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

691

intptr_t startAddr) {

692

LIR *lir;

693

AssemblerStatus res = kSuccess; // Assume success

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

694

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

695

for (lir = (LIR *) cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {

696

if (lir->opcode < 0) {

697

continue;

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

698

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

699

700

701

if (lir->flags.isNop) {

continue;

}

if (lir->flags.pcRelFixup) {

706

UNIMPLEMENTED(WARNING) << "PC relative fix up";

}

/*

* If one of the pc-relative instructions expanded we'll have

711

* to make another pass. Don't bother to fully assemble the

712

* instruction.

713

*/

714

if (res != kSuccess) {

715

continue;

716

}

717

const X86EncodingMap *entry = &EncodingMap[lir->opcode];

Ian Rogers

141b0c7

2012-03-15 18:18:52 -0700

[diff] [blame]

718

size_t starting_cbuf_size = cUnit->codeBuffer.size();

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

719

switch(entry->kind) {

720

case kData: // 4 bytes of data

721

cUnit->codeBuffer.push_back(lir->operands[0]);

722

break;

723

case kNullary: // 1 byte of opcode

724

DCHECK_EQ(0, entry->skeleton.prefix1);

725

DCHECK_EQ(0, entry->skeleton.prefix2);

726

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

727

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

728

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

729

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

730

DCHECK_EQ(0, entry->skeleton.ax_opcode);

731

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

732

break;

733

case kReg: // lir operands - 0: reg

734

emitOpReg(cUnit, entry, lir->operands[0]);

735

break;

736

case kMem: // lir operands - 0: base, 1: disp

737

emitOpMem(cUnit, entry, lir->operands[0], lir->operands[1]);

738

break;

739

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

740

emitMemReg(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

741

break;

742

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

743

emitRegMem(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

744

break;

745

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

746

emitRegArray(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

747

lir->operands[3], lir->operands[4]);

748

break;

749

case kRegReg: // lir operands - 0: reg1, 1: reg2

750

emitRegReg(cUnit, entry, lir->operands[0], lir->operands[1]);

751

break;

752

case kRegImm: // lir operands - 0: reg, 1: immediate

753

emitRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

754

break;

755

default:

Ian Rogers

6cbb2bd

2012-03-16 13:45:30 -0700

[diff] [blame^]

756

emitUnimplemented(cUnit, entry, lir);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

757

break;

758

}

Ian Rogers

141b0c7

2012-03-15 18:18:52 -0700

[diff] [blame]

759

CHECK_EQ(static_cast<size_t>(oatGetInsnSize(lir)),

760

cUnit->codeBuffer.size() - starting_cbuf_size);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

761

}

762

return res;

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

763

}

764

buzbee