Blame - src/compiler/codegen/x86/Assemble.cc - platform_art

2012-03-06 22:14:17 -0800

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{ kX86 ## opname ## 8RR, kRegReg, IS_BINARY_OP | SETS_CCODES, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RR", "!0r,!1r" }, \

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{ kX86 ## opname ## 8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## 8RA, kRegArray, IS_LOAD | IS_QUIN_OP | SETS_CCODES, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \

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{ kX86 ## opname ## 8RT, kRegThread, IS_LOAD | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RT", "!0r,fs:[!1d]" }, \

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{ kX86 ## opname ## 8RI, kRegImm, IS_BINARY_OP | SETS_CCODES, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, ax8_i8, 1 }, #opname "8RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 8MI, kMemImm, is_store | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8MI", "[!0r+!1d],!2r" }, \

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{ kX86 ## opname ## 8AI, kArrayImm, is_store | IS_QUIN_OP | SETS_CCODES, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4r" }, \

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{ kX86 ## opname ## 8TI, kThreadImm,is_store | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8TI", "fs:[!0d],!1r" }, \

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\

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{ kX86 ## opname ## 16MR, kMemReg, is_store | IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16MR", "[!0r+!1d],!2r" }, \

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{ kX86 ## opname ## 16AR, kArrayReg, is_store | IS_QUIN_OP | SETS_CCODES, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \

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{ kX86 ## opname ## 16TR, kThreadReg,is_store | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16TR", "fs:[!0d],!1r" }, \

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{ kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | SETS_CCODES, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RR", "!0r,!1r" }, \

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{ kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | SETS_CCODES, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \

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{ kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RT", "!0r,fs:[!1d]" }, \

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{ kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | SETS_CCODES, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kMemImm, is_store | IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kArrayImm, is_store | IS_QUIN_OP | SETS_CCODES, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16TI, kThreadImm,is_store | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16TI", "fs:[!0d],!1d" }, \

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{ kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | SETS_CCODES, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16RI8", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI8, kMemImm, is_store | IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16MI8", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI8, kArrayImm, is_store | IS_QUIN_OP | SETS_CCODES, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16TI8, kThreadImm,is_store | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16TI8", "fs:[!0d],!1d" }, \

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\

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{ kX86 ## opname ## 32MR, kMemReg, is_store | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32MR", "[!0r+!1d],!2r" }, \

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{ kX86 ## opname ## 32AR, kArrayReg, is_store | IS_QUIN_OP | SETS_CCODES, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \

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{ kX86 ## opname ## 32TR, kThreadReg,is_store | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32TR", "fs:[!0d],!1r" }, \

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{ kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | SETS_CCODES, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RR", "!0r,!1r" }, \

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{ kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | SETS_CCODES, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \

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{ kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RT", "!0r,fs:[!1d]" }, \

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{ kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | SETS_CCODES, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kMemImm, is_store | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32MI", "[!0r+!1d],!2r" }, \

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{ kX86 ## opname ## 32AI, kArrayImm, is_store | IS_QUIN_OP | SETS_CCODES, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32TI, kThreadImm,is_store | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32TI", "fs:[!0d],!1d" }, \

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{ kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | SETS_CCODES, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32RI8", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI8, kMemImm, is_store | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32MI8", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI8, kArrayImm, is_store | IS_QUIN_OP | SETS_CCODES, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32TI8, kThreadImm,is_store | IS_BINARY_OP | SETS_CCODES, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32TI8", "fs:[!0d],!1d" }

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ENCODING_MAP(Add, IS_STORE,

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0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */,

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0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */,

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0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */,

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0x80, 0x0 /* RegMem8/imm8 */,

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0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */),

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ENCODING_MAP(Or, IS_STORE,

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0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */,

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0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */,

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0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */,

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0x80, 0x1 /* RegMem8/imm8 */,

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0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */),

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ENCODING_MAP(Adc, IS_STORE,

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0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */,

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0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */,

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0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */,

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0x80, 0x2 /* RegMem8/imm8 */,

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0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */),

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ENCODING_MAP(Sbb, IS_STORE,

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0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */,

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0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */,

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0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */,

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0x80, 0x3 /* RegMem8/imm8 */,

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0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */),

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ENCODING_MAP(And, IS_STORE,

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0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */,

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0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */,

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0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */,

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0x80, 0x4 /* RegMem8/imm8 */,

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0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */),

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ENCODING_MAP(Sub, IS_STORE,

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0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */,

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0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */,

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0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */,

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0x80, 0x5 /* RegMem8/imm8 */,

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0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */),

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ENCODING_MAP(Xor, IS_STORE,

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0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */,

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0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */,

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0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */,

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0x80, 0x6 /* RegMem8/imm8 */,

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0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */),

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ENCODING_MAP(Cmp, IS_LOAD,

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0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */,

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0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */,

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0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */,

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0x80, 0x7 /* RegMem8/imm8 */,

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0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */),

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#undef ENCODING_MAP

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{ kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RRI", "" },

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{ kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RMI", "" },

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{ kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RAI", "" },

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{ kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul32RRI", "" },

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{ kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul32RMI", "" },

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{ kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul32RAI", "" },

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{ kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RRI8", "" },

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{ kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RMI8", "" },

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{ kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RAI8", "" },

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{ kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8MR", "[!0r+!1d],!2r" },

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{ kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8TR", "fs:[!0d],!1r" },

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{ kX86Mov8RR, kRegReg, IS_BINARY_OP, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RR", "!0r,!1r" },

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{ kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RM", "!0r,[!1r+!2d]" },

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{ kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RT", "!0r,fs:[!1d]" },

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{ kX86Mov8RI, kMovRegImm, IS_BINARY_OP, { 0, 0, 0xB0, 0, 0, 0, 0, 1 }, "Mov8RI", "!0r,!1d" },

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{ kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8MI", "[!0r+!1d],!2r" },

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{ kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8TI", "fs:[!0d],!1d" },

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{ kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16MR", "[!0r+!1d],!2r" },

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{ kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0 }, "Mov16TR", "fs:[!0d],!1r" },

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{ kX86Mov16RR, kRegReg, IS_BINARY_OP, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RR", "!0r,!1r" },

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{ kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RM", "!0r,[!1r+!2d]" },

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{ kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RT", "!0r,fs:[!1d]" },

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{ kX86Mov16RI, kMovRegImm, IS_BINARY_OP, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2 }, "Mov16RI", "!0r,!1d" },

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{ kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16MI", "[!0r+!1d],!2r" },

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{ kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2 }, "Mov16TI", "fs:[!0d],!1d" },

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{ kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32MR", "[!0r+!1d],!2r" },

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{ kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32TR", "fs:[!0d],!1r" },

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{ kX86Mov32RR, kRegReg, IS_BINARY_OP, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RR", "!0r,!1r" },

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{ kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RM", "!0r,[!1r+!2d]" },

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{ kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

174

{ kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RT", "!0r,fs:[!1d]" },

175

{ kX86Mov32RI, kMovRegImm, IS_BINARY_OP, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "Mov32RI", "!0r,!1d" },

176

{ kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32MI", "[!0r+!1d],!2r" },

177

{ kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" },

178

{ kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32TI", "fs:[!0d],!1d" },

179

180

{ kX86Lea32RA, kRegArray, IS_QUIN_OP, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

181

182

#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \

183

{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \

184

{ kX86 ## opname ## 8MI, kShiftMemImm, IS_TERTIARY_OP | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2r" }, \

185

{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_QUIN_OP | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

186

{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "" }, \

187

{ kX86 ## opname ## 8MC, kShiftMemCl, IS_TERTIARY_OP | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "" }, \

188

{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_QUIN_OP | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "" }, \

189

\

190

{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \

191

{ kX86 ## opname ## 16MI, kShiftMemImm, IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2r" }, \

192

{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_QUIN_OP | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

193

{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "" }, \

194

{ kX86 ## opname ## 16MC, kShiftMemCl, IS_TERTIARY_OP | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "" }, \

195

{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_QUIN_OP | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "" }, \

196

\

197

{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \

198

{ kX86 ## opname ## 32MI, kShiftMemImm, IS_TERTIARY_OP | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2r" }, \

199

{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_QUIN_OP | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

200

{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "32RC", "" }, \

201

{ kX86 ## opname ## 32MC, kShiftMemCl, IS_TERTIARY_OP | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "32MC", "" }, \

202

{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_QUIN_OP | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "32AC", "" }

203

204

SHIFT_ENCODING_MAP(Rol, 0x0),

205

SHIFT_ENCODING_MAP(Ror, 0x1),

206

SHIFT_ENCODING_MAP(Rcl, 0x2),

207

SHIFT_ENCODING_MAP(Rcr, 0x3),

208

SHIFT_ENCODING_MAP(Sal, 0x4),

209

SHIFT_ENCODING_MAP(Shl, 0x5),

210

SHIFT_ENCODING_MAP(Shr, 0x6),

211

SHIFT_ENCODING_MAP(Sar, 0x7),

212

#undef SHIFT_ENCODING_MAP

213

214

#define UNARY_ENCODING_MAP(opname, modrm, \

215

reg, reg_kind, reg_flags, \

216

mem, mem_kind, mem_flags, \

217

arr, arr_kind, arr_flags, imm) \

218

{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, "" }, \

219

{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | mem_flags, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, "" }, \

220

{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | arr_flags, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, "" }, \

221

{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, "" }, \

222

{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | mem_flags, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, "" }, \

223

{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | arr_flags, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, "" }, \

224

{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, "" }, \

225

{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | mem_flags, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, "" }, \

226

{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | arr_flags, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, "" }

227

228

UNARY_ENCODING_MAP(Test, 0x0, RI, kRegImm, IS_BINARY_OP, MI, kMemImm, IS_TERTIARY_OP, AI, kArrayImm, IS_QUIN_OP, 1),

229

UNARY_ENCODING_MAP(Not, 0x2, R, kReg, IS_UNARY_OP, M, kMem, IS_BINARY_OP, A, kArray, IS_QUAD_OP, 0),

230

UNARY_ENCODING_MAP(Neg, 0x3, R, kReg, IS_UNARY_OP, M, kMem, IS_BINARY_OP, A, kArray, IS_QUAD_OP, 0),

231

UNARY_ENCODING_MAP(Mul, 0x4, DaR, kRegRegReg, IS_TERTIARY_OP, DaM, kRegRegMem, IS_QUAD_OP, DaA, kRegRegArray, IS_SEXTUPLE_OP, 0),

232

UNARY_ENCODING_MAP(Imul, 0x5, DaR, kRegRegReg, IS_TERTIARY_OP, DaM, kRegRegMem, IS_QUAD_OP, DaA, kRegRegArray, IS_SEXTUPLE_OP, 0),

233

UNARY_ENCODING_MAP(Divmod, 0x6, DaR, kRegRegReg, IS_TERTIARY_OP, DaM, kRegRegMem, IS_QUAD_OP, DaA, kRegRegArray, IS_SEXTUPLE_OP, 0),

234

UNARY_ENCODING_MAP(Idivmod, 0x7, DaR, kRegRegReg, IS_TERTIARY_OP, DaM, kRegRegMem, IS_QUAD_OP, DaA, kRegRegArray, IS_SEXTUPLE_OP, 0),

235

#undef UNARY_ENCODING_MAP

236

237

#define EXT_0F_ENCODING_MAP(opname, prefix, opcode) \

238

{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

239

{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

240

{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

241

242

EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10),

243

{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

244

{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

245

246

EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10),

247

{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

248

{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

249

250

EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A),

251

EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A),

252

EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C),

253

EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C),

254

EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D),

255

EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D),

256

EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E),

257

EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E),

258

EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F),

259

EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F),

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2012-03-20 14:22:54 -0700

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260

EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56),

261

EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57),

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2012-03-06 22:14:17 -0800

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262

EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58),

263

EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58),

264

EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59),

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EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59),

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EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF2, 0x5A),

267

EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF3, 0x5A),

268

EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C),

269

EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C),

270

EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E),

271

EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E),

272

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2012-03-20 14:22:54 -0700

[diff] [blame]

273

{ kX86PsllqRI, kRegImm, IS_BINARY_OP, { 0, 0, 0x0F, 0x73, 0, 7, 0, 1 }, "PsllqRI", "!0r, !1d" },

274

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2012-03-06 22:14:17 -0800

[diff] [blame]

275

EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E),

276

EXT_0F_ENCODING_MAP(Movdrx, 0x66, 0x7E),

277

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{ kX86Set8R, kRegCond, IS_BINARY_OP, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

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{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

280

{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

281

282

EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF),

283

EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF),

284

EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6),

285

EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7),

286

EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE),

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EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF),

288

#undef EXT_0F_ENCODING_MAP

289

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2012-03-20 14:22:54 -0700

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290

{ kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },

291

{ kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },

292

{ kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },

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{ kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },

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2012-03-16 13:45:30 -0700

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{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

295

{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

296

{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

297

{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

298

{ kX86Ret, kNullary,NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

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2012-03-05 11:19:57 -0800

[diff] [blame]

299

};

300

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2012-03-06 22:14:17 -0800

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301

static size_t computeSize(X86EncodingMap* entry, int displacement, bool has_sib) {

302

size_t size = 0;

303

if (entry->skeleton.prefix1 > 0) {

304

++size;

305

if (entry->skeleton.prefix2 > 0) {

306

++size;

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2012-03-06 10:18:10 -0800

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307

}

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2012-03-06 10:18:10 -0800

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}

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++size; // opcode

310

if (entry->skeleton.opcode == 0x0F) {

311

++size;

312

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

if (has_sib) {

++size;

}

if (displacement != 0) {

321

if (entry->opcode != kX86Lea32RA) {

322

DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0);

323

}

324

size += IS_SIMM8(displacement) ? 1 : 4;

325

}

326

size += entry->skeleton.immediate_bytes;

return size;

}

int oatGetInsnSize(LIR* lir) {

331

X86EncodingMap* entry = &EncodingMap[lir->opcode];

332

switch (entry->kind) {

333

case kData:

334

return 4; // 4 bytes of data

335

case kNop:

336

return lir->operands[0]; // length of nop is sole operand

337

case kNullary:

338

return 1; // 1 byte of opcode

339

case kReg: // lir operands - 0: reg

340

return computeSize(entry, 0, false);

341

case kMem: { // lir operands - 0: base, 1: disp

342

int base = lir->operands[0];

343

// SP requires a special extra SIB byte

344

return computeSize(entry, lir->operands[1], false) + (base == rSP ? 1 : 0);

345

}

346

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

347

return computeSize(entry, lir->operands[3], true);

348

case kMemReg: { // lir operands - 0: base, 1: disp, 2: reg

349

int base = lir->operands[0];

350

// SP requires a special extra SIB byte

351

return computeSize(entry, lir->operands[1], false) + (base == rSP ? 1 : 0);

352

}

353

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

354

return computeSize(entry, lir->operands[3], true);

355

case kThreadReg: // lir operands - 0: disp, 1: reg

356

return computeSize(entry, lir->operands[0], false);

357

case kRegReg:

358

return computeSize(entry, 0, false);

359

case kRegMem: { // lir operands - 0: reg, 1: base, 2: disp

360

int base = lir->operands[1];

361

return computeSize(entry, lir->operands[2], false) + (base == rSP ? 1 : 0);

362

}

363

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

364

return computeSize(entry, lir->operands[4], true);

365

case kRegThread: // lir operands - 0: reg, 1: disp

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2012-03-19 01:12:01 -0700

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366

return computeSize(entry, 0x12345678, false); // displacement size is always 32bit

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2012-03-06 22:14:17 -0800

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367

case kRegImm: { // lir operands - 0: reg, 1: immediate

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2012-03-20 14:22:54 -0700

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368

size_t size = computeSize(entry, 0, false);

369

if (entry->skeleton.ax_opcode == 0) {

370

return size;

371

} else {

372

// AX opcodes don't require the modrm byte.

373

int reg = lir->operands[0];

374

return size - (reg == rAX ? 1 : 0);

375

}

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2012-03-06 22:14:17 -0800

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376

}

377

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

378

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

379

return computeSize(entry, lir->operands[1], false);

380

case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

381

return computeSize(entry, lir->operands[3], true);

382

case kThreadImm: // lir operands - 0: disp, 1: imm

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383

return computeSize(entry, 0x12345678, false); // displacement size is always 32bit

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2012-03-06 22:14:17 -0800

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case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

385

return computeSize(entry, 0, false);

386

case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

387

CHECK_NE(lir->operands[1], static_cast<int>(rSP)); // TODO: add extra SIB byte

388

return computeSize(entry, lir->operands[2], false);

389

case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

390

return computeSize(entry, lir->operands[4], true);

391

case kMovRegImm: // lir operands - 0: reg, 1: immediate

392

return 1 + entry->skeleton.immediate_bytes;

393

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

394

// Shift by immediate one has a shorter opcode.

395

return computeSize(entry, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

396

case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

397

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

398

// Shift by immediate one has a shorter opcode.

399

return computeSize(entry, lir->operands[1], false) - (lir->operands[2] == 1 ? 1 : 0);

400

case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

401

// Shift by immediate one has a shorter opcode.

402

return computeSize(entry, lir->operands[3], true) - (lir->operands[4] == 1 ? 1 : 0);

403

case kShiftRegCl:

404

return computeSize(entry, 0, false);

405

case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

406

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

407

return computeSize(entry, lir->operands[1], false);

408

case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

409

return computeSize(entry, lir->operands[3], true);

410

case kRegCond: // lir operands - 0: reg, 1: cond

411

return computeSize(entry, 0, false);

412

case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

413

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

414

return computeSize(entry, lir->operands[1], false);

415

case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

416

return computeSize(entry, lir->operands[3], true);

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

417

case kJcc:

418

if (lir->opcode == kX86Jcc8) {

419

return 2; // opcode + rel8

420

} else {

421

DCHECK(lir->opcode == kX86Jcc32);

422

return 6; // 2 byte opcode + rel32

423

}

424

case kJmp:

425

if (lir->opcode == kX86Jmp8) {

426

return 2; // opcode + rel8

427

} else {

428

DCHECK(lir->opcode == kX86Jmp32);

429

return 5; // opcode + rel32

430

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

431

case kCall:

432

switch(lir->opcode) {

433

case kX86CallR: return 2; // opcode modrm

434

case kX86CallM: // lir operands - 0: base, 1: disp

435

return computeSize(entry, lir->operands[1], false);

436

case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

437

return computeSize(entry, lir->operands[3], true);

Ian Rogers

2012-03-16 13:45:30 -0700

[diff] [blame]

438

case kX86CallT: // lir operands - 0: disp

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

439

return computeSize(entry, 0x12345678, false); // displacement size is always 32bit

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

default:

break;

}

break;

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

448

return 0;

449

}

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

450

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

451

static uint8_t modrmForDisp(int disp) {

452

if (disp == 0) {

453

return 0;

454

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

static void emitDisp(CompilationUnit* cUnit, int disp) {

462

if (disp == 0) {

463

return;

464

} else if (IS_SIMM8(disp)) {

465

cUnit->codeBuffer.push_back(disp & 0xFF);

466

} else {

467

cUnit->codeBuffer.push_back(disp & 0xFF);

468

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

469

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

470

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

}

}

static void emitOpReg(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg) {

475

if (entry->skeleton.prefix1 != 0) {

476

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

477

if (entry->skeleton.prefix2 != 0) {

478

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

479

}

480

} else {

481

DCHECK_EQ(0, entry->skeleton.prefix2);

482

}

483

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

484

if (entry->skeleton.opcode == 0x0F) {

485

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

486

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

487

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

488

} else {

489

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

490

}

491

} else {

492

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

493

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

494

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

495

if (FPREG(reg)) {

496

reg = reg & FP_REG_MASK;

497

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

498

DCHECK_LT(reg, 8);

499

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

500

cUnit->codeBuffer.push_back(modrm);

501

DCHECK_EQ(0, entry->skeleton.ax_opcode);

502

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

503

}

504

505

static void emitOpMem(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t base, int disp) {

506

if (entry->skeleton.prefix1 != 0) {

507

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

508

if (entry->skeleton.prefix2 != 0) {

509

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

510

}

511

} else {

512

DCHECK_EQ(0, entry->skeleton.prefix2);

513

}

514

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

515

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

516

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

517

DCHECK_LT(entry->skeleton.modrm_opcode, 8);

518

DCHECK_LT(base, 8);

519

uint8_t modrm = (modrmForDisp(disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;

520

cUnit->codeBuffer.push_back(modrm);

521

emitDisp(cUnit, disp);

522

DCHECK_EQ(0, entry->skeleton.ax_opcode);

523

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

524

}

525

526

static void emitMemReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

527

uint8_t base, int disp, uint8_t reg) {

528

if (entry->skeleton.prefix1 != 0) {

529

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

530

if (entry->skeleton.prefix2 != 0) {

531

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

532

}

533

} else {

534

DCHECK_EQ(0, entry->skeleton.prefix2);

535

}

536

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

537

if (entry->skeleton.opcode == 0x0F) {

538

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

539

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

540

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

541

} else {

542

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

543

}

544

} else {

545

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

546

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

547

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

548

if (FPREG(reg)) {

549

reg = reg & FP_REG_MASK;

550

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

551

DCHECK_LT(reg, 8);

552

DCHECK_LT(base, 8);

553

uint8_t modrm = (modrmForDisp(disp) << 6) | (reg << 3) | base;

554

cUnit->codeBuffer.push_back(modrm);

555

if (base == rSP) {

556

// Special SIB for SP base

557

cUnit->codeBuffer.push_back(0 << 6 | (rSP << 3) | rSP);

558

}

559

emitDisp(cUnit, disp);

560

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

561

DCHECK_EQ(0, entry->skeleton.ax_opcode);

562

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

563

}

564

565

static void emitRegMem(CompilationUnit* cUnit, const X86EncodingMap* entry,

566

uint8_t reg, uint8_t base, int disp) {

567

// Opcode will flip operands.

568

emitMemReg(cUnit, entry, base, disp, reg);

569

}

570

571

static void emitRegArray(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg,

572

uint8_t base, uint8_t index, int scale, int disp) {

573

if (entry->skeleton.prefix1 != 0) {

574

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

575

if (entry->skeleton.prefix2 != 0) {

576

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

577

}

578

} else {

579

DCHECK_EQ(0, entry->skeleton.prefix2);

580

}

581

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

582

if (entry->skeleton.opcode == 0x0F) {

583

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

584

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

585

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

586

} else {

587

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

588

}

589

} else {

590

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

591

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

592

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

593

if (FPREG(reg)) {

594

reg = reg & FP_REG_MASK;

595

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

596

DCHECK_LT(reg, 8);

597

uint8_t modrm = (modrmForDisp(disp) << 6) | (reg << 3) | rSP;

598

cUnit->codeBuffer.push_back(modrm);

DCHECK_LT(scale, 4);

DCHECK_LT(index, 8);

DCHECK_LT(base, 8);

uint8_t sib = (scale << 6) | (index << 3) | base;

603

cUnit->codeBuffer.push_back(sib);

604

emitDisp(cUnit, disp);

605

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

606

DCHECK_EQ(0, entry->skeleton.ax_opcode);

607

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

608

}

609

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

610

static void emitArrayReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

611

uint8_t base, uint8_t index, int scale, int disp, uint8_t reg) {

612

// Opcode will flip operands.

613

emitRegArray(cUnit, entry, reg, base, index, scale, disp);

614

}

615

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

616

static void emitRegThread(CompilationUnit* cUnit, const X86EncodingMap* entry,

617

uint8_t reg, int disp) {

618

DCHECK_NE(entry->skeleton.prefix1, 0);

619

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

620

if (entry->skeleton.prefix2 != 0) {

621

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

622

}

623

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

624

if (entry->skeleton.opcode == 0x0F) {

625

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

626

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

627

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

628

} else {

629

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

630

}

631

} else {

632

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

633

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

634

}

635

if (FPREG(reg)) {

636

reg = reg & FP_REG_MASK;

637

}

638

DCHECK_LT(reg, 8);

639

uint8_t modrm = (0 << 6) | (reg << 3) | rBP;

640

cUnit->codeBuffer.push_back(modrm);

641

cUnit->codeBuffer.push_back(disp & 0xFF);

642

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

643

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

644

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

645

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

646

DCHECK_EQ(0, entry->skeleton.ax_opcode);

647

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

648

}

649

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

650

static void emitRegReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

651

uint8_t reg1, uint8_t reg2) {

652

if (entry->skeleton.prefix1 != 0) {

653

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

654

if (entry->skeleton.prefix2 != 0) {

655

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

656

}

657

} else {

658

DCHECK_EQ(0, entry->skeleton.prefix2);

659

}

660

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

661

if (entry->skeleton.opcode == 0x0F) {

662

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

663

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

664

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

665

} else {

666

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

667

}

668

} else {

669

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

670

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

671

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

672

if (FPREG(reg1)) {

673

reg1 = reg1 & FP_REG_MASK;

674

}

675

if (FPREG(reg2)) {

676

reg2 = reg2 & FP_REG_MASK;

677

}

678

DCHECK_LT(reg1, 8);

679

DCHECK_LT(reg2, 8);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

680

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

681

cUnit->codeBuffer.push_back(modrm);

682

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

683

DCHECK_EQ(0, entry->skeleton.ax_opcode);

684

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

685

}

686

687

static void emitRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

688

uint8_t reg, int imm) {

689

if (entry->skeleton.prefix1 != 0) {

690

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

691

if (entry->skeleton.prefix2 != 0) {

692

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

693

}

694

} else {

695

DCHECK_EQ(0, entry->skeleton.prefix2);

696

}

697

if (reg == rAX && entry->skeleton.ax_opcode != 0) {

698

cUnit->codeBuffer.push_back(entry->skeleton.ax_opcode);

699

} else {

700

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

701

if (entry->skeleton.opcode == 0x0F) {

702

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

703

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

704

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

705

} else {

706

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

707

}

708

} else {

709

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

710

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

711

}

712

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

713

cUnit->codeBuffer.push_back(modrm);

714

}

715

switch (entry->skeleton.immediate_bytes) {

716

case 1:

717

DCHECK(IS_SIMM8(imm));

718

cUnit->codeBuffer.push_back(imm & 0xFF);

719

break;

720

case 2:

721

DCHECK(IS_SIMM16(imm));

722

cUnit->codeBuffer.push_back(imm & 0xFF);

723

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

724

break;

725

case 4:

726

cUnit->codeBuffer.push_back(imm & 0xFF);

727

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

728

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

729

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

730

break;

731

default:

732

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

733

<< ") for instruction: " << entry->name;

break;

}

}

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

738

static void emitThreadImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

739

int disp, int imm) {

740

if (entry->skeleton.prefix1 != 0) {

741

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

742

if (entry->skeleton.prefix2 != 0) {

743

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

744

}

745

} else {

746

DCHECK_EQ(0, entry->skeleton.prefix2);

747

}

748

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

749

if (entry->skeleton.opcode == 0x0F) {

750

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

751

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

752

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

753

} else {

754

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

755

}

756

} else {

757

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

758

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

759

}

760

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

761

cUnit->codeBuffer.push_back(modrm);

762

cUnit->codeBuffer.push_back(disp & 0xFF);

763

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

764

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

765

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

766

switch (entry->skeleton.immediate_bytes) {

767

case 1:

768

DCHECK(IS_SIMM8(imm));

769

cUnit->codeBuffer.push_back(imm & 0xFF);

770

break;

771

case 2:

772

DCHECK(IS_SIMM16(imm));

773

cUnit->codeBuffer.push_back(imm & 0xFF);

774

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

775

break;

776

case 4:

777

cUnit->codeBuffer.push_back(imm & 0xFF);

778

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

779

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

780

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

781

break;

782

default:

783

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

784

<< ") for instruction: " << entry->name;

785

break;

786

}

787

DCHECK_EQ(entry->skeleton.ax_opcode, 0);

788

}

789

790

static void emitMovRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

791

uint8_t reg, int imm) {

792

DCHECK_LT(reg, 8);

793

cUnit->codeBuffer.push_back(0xB8 + reg);

794

cUnit->codeBuffer.push_back(imm & 0xFF);

795

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

796

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

797

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

798

}

799

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

800

static void emitShiftRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

801

uint8_t reg, int imm) {

802

if (entry->skeleton.prefix1 != 0) {

803

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

804

if (entry->skeleton.prefix2 != 0) {

805

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

806

}

807

} else {

808

DCHECK_EQ(0, entry->skeleton.prefix2);

809

}

810

if (imm != 1) {

811

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

812

} else {

813

// Shorter encoding for 1 bit shift

814

cUnit->codeBuffer.push_back(entry->skeleton.ax_opcode);

815

}

816

if (entry->skeleton.opcode == 0x0F) {

817

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

818

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

819

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

820

} else {

821

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

822

}

823

} else {

824

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

825

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

826

}

827

DCHECK_LT(reg, 8);

828

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

829

cUnit->codeBuffer.push_back(modrm);

830

if (imm != 1) {

831

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

832

DCHECK(IS_SIMM8(imm));

833

cUnit->codeBuffer.push_back(imm & 0xFF);

}

}

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

837

static void emitJmp(CompilationUnit* cUnit, const X86EncodingMap* entry, int rel) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

838

if (entry->opcode == kX86Jmp8) {

839

DCHECK(IS_SIMM8(rel));

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

840

cUnit->codeBuffer.push_back(0xEB);

841

cUnit->codeBuffer.push_back(rel & 0xFF);

842

} else {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

843

DCHECK(entry->opcode == kX86Jmp32);

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

844

cUnit->codeBuffer.push_back(0xE9);

845

cUnit->codeBuffer.push_back(rel & 0xFF);

846

cUnit->codeBuffer.push_back((rel >> 8) & 0xFF);

847

cUnit->codeBuffer.push_back((rel >> 16) & 0xFF);

848

cUnit->codeBuffer.push_back((rel >> 24) & 0xFF);

}

}

static void emitJcc(CompilationUnit* cUnit, const X86EncodingMap* entry,

853

int rel, uint8_t cc) {

854

DCHECK_LT(cc, 16);

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

855

if (entry->opcode == kX86Jcc8) {

856

DCHECK(IS_SIMM8(rel));

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

857

cUnit->codeBuffer.push_back(0x70 | cc);

858

cUnit->codeBuffer.push_back(rel & 0xFF);

859

} else {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

860

DCHECK(entry->opcode == kX86Jcc32);

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

861

cUnit->codeBuffer.push_back(0x0F);

862

cUnit->codeBuffer.push_back(0x80 | cc);

863

cUnit->codeBuffer.push_back(rel & 0xFF);

864

cUnit->codeBuffer.push_back((rel >> 8) & 0xFF);

865

cUnit->codeBuffer.push_back((rel >> 16) & 0xFF);

866

cUnit->codeBuffer.push_back((rel >> 24) & 0xFF);

}

}

static void emitCallMem(CompilationUnit* cUnit, const X86EncodingMap* entry,

871

uint8_t base, int disp) {

872

if (entry->skeleton.prefix1 != 0) {

873

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

874

if (entry->skeleton.prefix2 != 0) {

875

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

876

}

877

} else {

878

DCHECK_EQ(0, entry->skeleton.prefix2);

879

}

880

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

881

if (entry->skeleton.opcode == 0x0F) {

882

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

883

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

884

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

885

} else {

886

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

887

}

888

} else {

889

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

890

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

891

}

892

uint8_t modrm = (modrmForDisp(disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;

893

cUnit->codeBuffer.push_back(modrm);

894

if (base == rSP) {

895

// Special SIB for SP base

896

cUnit->codeBuffer.push_back(0 << 6 | (rSP << 3) | rSP);

897

}

898

emitDisp(cUnit, disp);

899

DCHECK_EQ(0, entry->skeleton.ax_opcode);

900

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

901

}

902

903

static void emitCallThread(CompilationUnit* cUnit, const X86EncodingMap* entry, int disp) {

904

DCHECK_NE(entry->skeleton.prefix1, 0);

905

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

906

if (entry->skeleton.prefix2 != 0) {

907

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

908

}

909

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

910

if (entry->skeleton.opcode == 0x0F) {

911

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

912

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

913

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

914

} else {

915

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

916

}

917

} else {

918

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

919

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

920

}

921

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

922

cUnit->codeBuffer.push_back(modrm);

923

cUnit->codeBuffer.push_back(disp & 0xFF);

924

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

925

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

926

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

927

DCHECK_EQ(0, entry->skeleton.ax_opcode);

928

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

929

}

930

Ian Rogers

2012-03-16 13:45:30 -0700

[diff] [blame]

931

void emitUnimplemented(CompilationUnit* cUnit, const X86EncodingMap* entry, LIR* lir) {

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

932

UNIMPLEMENTED(WARNING) << "encoding for: " << entry->name;

Ian Rogers

141b0c7

2012-03-15 18:18:52 -0700

[diff] [blame]

933

for (int i = 0; i < oatGetInsnSize(lir); ++i) {

934

cUnit->codeBuffer.push_back(0xCC); // push breakpoint instruction - int 3

}

}

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

938

/*

939

* Assemble the LIR into binary instruction format. Note that we may

940

* discover that pc-relative displacements may not fit the selected

941

* instruction. In those cases we will try to substitute a new code

942

* sequence or request that the trace be shortened and retried.

943

*/

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

944

AssemblerStatus oatAssembleInstructions(CompilationUnit *cUnit, intptr_t startAddr) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

945

LIR *lir;

946

AssemblerStatus res = kSuccess; // Assume success

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

947

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

948

for (lir = (LIR *) cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {

949

if (lir->opcode < 0) {

950

continue;

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

951

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

952

953

954

if (lir->flags.isNop) {

continue;

}

if (lir->flags.pcRelFixup) {

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

959

switch (lir->opcode) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

960

case kX86Jcc8: {

961

LIR *targetLIR = lir->target;

962

DCHECK(targetLIR != NULL);

963

int delta = 0;

964

intptr_t pc;

965

if (IS_SIMM8(lir->operands[0])) {

966

pc = lir->offset + 2 /* opcode + rel8 */;

967

} else {

968

pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

969

}

970

intptr_t target = targetLIR->offset;

971

delta = target - pc;

972

if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

973

LOG(INFO) << "Retry for JCC growth at " << lir->offset

974

<< " delta: " << delta << " old delta: " << lir->operands[0];

975

lir->opcode = kX86Jcc32;

976

oatSetupResourceMasks(lir);

977

res = kRetryAll;

978

}

979

lir->operands[0] = delta;

980

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

981

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

982

case kX86Jmp8: {

983

LIR *targetLIR = lir->target;

984

DCHECK(targetLIR != NULL);

985

int delta = 0;

986

intptr_t pc;

987

if (IS_SIMM8(lir->operands[0])) {

988

pc = lir->offset + 2 /* opcode + rel8 */;

989

} else {

990

pc = lir->offset + 5 /* opcode + rel32 */;

991

}

992

intptr_t target = targetLIR->offset;

993

delta = target - pc;

994

if (!(cUnit->disableOpt & (1 << kSafeOptimizations)) && lir->operands[0] == 0) {

995

// Useless branch

996

lir->flags.isNop = true;

997

LOG(INFO) << "Retry for useless branch at " << lir->offset;

998

res = kRetryAll;

999

} else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1000

LOG(INFO) << "Retry for JMP growth at " << lir->offset;

1001

lir->opcode = kX86Jmp32;

1002

oatSetupResourceMasks(lir);

1003

res = kRetryAll;

1004

}

1005

lir->operands[0] = delta;

1006

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

}

default:

break;

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

}

/*

* If one of the pc-relative instructions expanded we'll have

1015

* to make another pass. Don't bother to fully assemble the

1016

* instruction.

1017

*/

1018

if (res != kSuccess) {

1019

continue;

1020

}

1021

const X86EncodingMap *entry = &EncodingMap[lir->opcode];

Ian Rogers

141b0c7

2012-03-15 18:18:52 -0700

[diff] [blame]

1022

size_t starting_cbuf_size = cUnit->codeBuffer.size();

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1023

switch(entry->kind) {

1024

case kData: // 4 bytes of data

1025

cUnit->codeBuffer.push_back(lir->operands[0]);

1026

break;

1027

case kNullary: // 1 byte of opcode

1028

DCHECK_EQ(0, entry->skeleton.prefix1);

1029

DCHECK_EQ(0, entry->skeleton.prefix2);

1030

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1031

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1032

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1033

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1034

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1035

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1036

break;

1037

case kReg: // lir operands - 0: reg

1038

emitOpReg(cUnit, entry, lir->operands[0]);

1039

break;

1040

case kMem: // lir operands - 0: base, 1: disp

1041

emitOpMem(cUnit, entry, lir->operands[0], lir->operands[1]);

1042

break;

1043

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

1044

emitMemReg(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1045

break;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1046

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

1047

emitArrayReg(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

1048

lir->operands[3], lir->operands[4]);

1049

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1050

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

1051

emitRegMem(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1052

break;

1053

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

1054

emitRegArray(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

1055

lir->operands[3], lir->operands[4]);

1056

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1057

case kRegThread: // lir operands - 0: reg, 1: disp

1058

emitRegThread(cUnit, entry, lir->operands[0], lir->operands[1]);

1059

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1060

case kRegReg: // lir operands - 0: reg1, 1: reg2

1061

emitRegReg(cUnit, entry, lir->operands[0], lir->operands[1]);

1062

break;

1063

case kRegImm: // lir operands - 0: reg, 1: immediate

1064

emitRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1065

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1066

case kThreadImm: // lir operands - 0: disp, 1: immediate

1067

emitThreadImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1068

break;

1069

case kMovRegImm: // lir operands - 0: reg, 1: immediate

1070

emitMovRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1071

break;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1072

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

1073

emitShiftRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1074

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1075

case kJmp: // lir operands - 0: rel

1076

emitJmp(cUnit, entry, lir->operands[0]);

1077

break;

1078

case kJcc: // lir operands - 0: rel, 1: CC, target assigned

1079

emitJcc(cUnit, entry, lir->operands[0], lir->operands[1]);

1080

break;

1081

case kCall:

1082

switch(entry->opcode) {

1083

case kX86CallM: // lir operands - 0: base, 1: disp

1084

emitCallMem(cUnit, entry, lir->operands[0], lir->operands[1]);

1085

break;

1086

case kX86CallT: // lir operands - 0: disp

1087

emitCallThread(cUnit, entry, lir->operands[0]);

1088

break;

1089

default:

1090

emitUnimplemented(cUnit, entry, lir);

1091

break;

1092

}

1093

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1094

default:

Ian Rogers

2012-03-16 13:45:30 -0700

[diff] [blame]

1095

emitUnimplemented(cUnit, entry, lir);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1096

break;

1097

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1098

if (entry->kind != kJcc && entry->kind != kJmp) {

1099

CHECK_EQ(static_cast<size_t>(oatGetInsnSize(lir)),

1100

cUnit->codeBuffer.size() - starting_cbuf_size)

1101

<< "Instruction size mismatch for entry: " << EncodingMap[lir->opcode].name;

1102

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1103

}

1104

return res;

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1105

}

1106

buzbee