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review.blissroms.org / platform_art / d2b4ca2d02c86b1ce1826fd2b35ce6c9c58c1ff1 / . / compiler / utils / arm / assembler_arm32.h
blob: d346096c22cbe5af3a93a5a457c39ff84a79e56d [file] [log] [blame]
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]1/*
2 * Copyright (C) 2014 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_UTILS_ARM_ASSEMBLER_ARM32_H_
18#define ART_COMPILER_UTILS_ARM_ASSEMBLER_ARM32_H_
19
20#include <vector>
21
22#include "base/logging.h"
23#include "constants_arm.h"
24#include "utils/arm/managed_register_arm.h"
25#include "utils/arm/assembler_arm.h"
26#include "offsets.h"
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]27
28namespace art {
29namespace arm {
30
31class Arm32Assembler FINAL : public ArmAssembler {
32 public:
33 Arm32Assembler() {
34 }
35 virtual ~Arm32Assembler() {}
36
37 bool IsThumb() const OVERRIDE {
38 return false;
39 }
40
41 // Data-processing instructions.
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]42 virtual void and_(Register rd, Register rn, const ShifterOperand& so,
43 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]44
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]45 virtual void eor(Register rd, Register rn, const ShifterOperand& so,
46 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]47
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]48 virtual void sub(Register rd, Register rn, const ShifterOperand& so,
49 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]50
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]51 virtual void rsb(Register rd, Register rn, const ShifterOperand& so,
52 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]53
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]54 virtual void add(Register rd, Register rn, const ShifterOperand& so,
55 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]56
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]57 virtual void adc(Register rd, Register rn, const ShifterOperand& so,
58 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]59
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]60 virtual void sbc(Register rd, Register rn, const ShifterOperand& so,
61 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]62
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]63 virtual void rsc(Register rd, Register rn, const ShifterOperand& so,
64 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]65
66 void tst(Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
67
68 void teq(Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
69
70 void cmp(Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
71
72 void cmn(Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
73
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]74 virtual void orr(Register rd, Register rn, const ShifterOperand& so,
75 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]76
Vladimir Markod2b4ca22015-09-14 15:13:26 +0100[diff] [blame^]77 virtual void orn(Register rd, Register rn, const ShifterOperand& so,
78 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
79
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]80 virtual void mov(Register rd, const ShifterOperand& so,
81 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]82
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]83 virtual void bic(Register rd, Register rn, const ShifterOperand& so,
84 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]85
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]86 virtual void mvn(Register rd, const ShifterOperand& so,
87 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]88
89 // Miscellaneous data-processing instructions.
90 void clz(Register rd, Register rm, Condition cond = AL) OVERRIDE;
91 void movw(Register rd, uint16_t imm16, Condition cond = AL) OVERRIDE;
92 void movt(Register rd, uint16_t imm16, Condition cond = AL) OVERRIDE;
Scott Wakeling9ee23f42015-07-23 10:44:35 +0100[diff] [blame]93 void rbit(Register rd, Register rm, Condition cond = AL) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]94
95 // Multiply instructions.
96 void mul(Register rd, Register rn, Register rm, Condition cond = AL) OVERRIDE;
97 void mla(Register rd, Register rn, Register rm, Register ra,
98 Condition cond = AL) OVERRIDE;
99 void mls(Register rd, Register rn, Register rm, Register ra,
100 Condition cond = AL) OVERRIDE;
Zheng Xuc6667102015-05-15 16:08:45 +0800[diff] [blame]101 void smull(Register rd_lo, Register rd_hi, Register rn, Register rm,
102 Condition cond = AL) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]103 void umull(Register rd_lo, Register rd_hi, Register rn, Register rm,
104 Condition cond = AL) OVERRIDE;
105
106 void sdiv(Register rd, Register rn, Register rm, Condition cond = AL) OVERRIDE;
107 void udiv(Register rd, Register rn, Register rm, Condition cond = AL) OVERRIDE;
108
Roland Levillain981e4542014-11-14 11:47:14 +0000[diff] [blame]109 // Bit field extract instructions.
Roland Levillain51d3fc42014-11-13 14:11:42 +0000[diff] [blame]110 void sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond = AL) OVERRIDE;
Roland Levillain981e4542014-11-14 11:47:14 +0000[diff] [blame]111 void ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond = AL) OVERRIDE;
Roland Levillain51d3fc42014-11-13 14:11:42 +0000[diff] [blame]112
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]113 // Load/store instructions.
114 void ldr(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
115 void str(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
116
117 void ldrb(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
118 void strb(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
119
120 void ldrh(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
121 void strh(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
122
123 void ldrsb(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
124 void ldrsh(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
125
126 void ldrd(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
127 void strd(Register rd, const Address& ad, Condition cond = AL) OVERRIDE;
128
129 void ldm(BlockAddressMode am, Register base,
130 RegList regs, Condition cond = AL) OVERRIDE;
131 void stm(BlockAddressMode am, Register base,
132 RegList regs, Condition cond = AL) OVERRIDE;
133
134 void ldrex(Register rd, Register rn, Condition cond = AL) OVERRIDE;
135 void strex(Register rd, Register rt, Register rn, Condition cond = AL) OVERRIDE;
Calin Juravle52c48962014-12-16 17:02:57 +0000[diff] [blame]136 void ldrexd(Register rt, Register rt2, Register rn, Condition cond = AL) OVERRIDE;
137 void strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond = AL) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]138
139 // Miscellaneous instructions.
140 void clrex(Condition cond = AL) OVERRIDE;
141 void nop(Condition cond = AL) OVERRIDE;
142
143 // Note that gdb sets breakpoints using the undefined instruction 0xe7f001f0.
144 void bkpt(uint16_t imm16) OVERRIDE;
145 void svc(uint32_t imm24) OVERRIDE;
146
147 void cbz(Register rn, Label* target) OVERRIDE;
148 void cbnz(Register rn, Label* target) OVERRIDE;
149
150 // Floating point instructions (VFPv3-D16 and VFPv3-D32 profiles).
151 void vmovsr(SRegister sn, Register rt, Condition cond = AL) OVERRIDE;
152 void vmovrs(Register rt, SRegister sn, Condition cond = AL) OVERRIDE;
153 void vmovsrr(SRegister sm, Register rt, Register rt2, Condition cond = AL) OVERRIDE;
154 void vmovrrs(Register rt, Register rt2, SRegister sm, Condition cond = AL) OVERRIDE;
155 void vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond = AL) OVERRIDE;
156 void vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond = AL) OVERRIDE;
157 void vmovs(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
158 void vmovd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE;
159
160 // Returns false if the immediate cannot be encoded.
161 bool vmovs(SRegister sd, float s_imm, Condition cond = AL) OVERRIDE;
162 bool vmovd(DRegister dd, double d_imm, Condition cond = AL) OVERRIDE;
163
164 void vldrs(SRegister sd, const Address& ad, Condition cond = AL) OVERRIDE;
165 void vstrs(SRegister sd, const Address& ad, Condition cond = AL) OVERRIDE;
166 void vldrd(DRegister dd, const Address& ad, Condition cond = AL) OVERRIDE;
167 void vstrd(DRegister dd, const Address& ad, Condition cond = AL) OVERRIDE;
168
169 void vadds(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE;
170 void vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE;
171 void vsubs(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE;
172 void vsubd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE;
173 void vmuls(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE;
174 void vmuld(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE;
175 void vmlas(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE;
176 void vmlad(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE;
177 void vmlss(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE;
178 void vmlsd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE;
179 void vdivs(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE;
180 void vdivd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE;
181
182 void vabss(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
183 void vabsd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE;
184 void vnegs(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
185 void vnegd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE;
186 void vsqrts(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
187 void vsqrtd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE;
188
189 void vcvtsd(SRegister sd, DRegister dm, Condition cond = AL) OVERRIDE;
190 void vcvtds(DRegister dd, SRegister sm, Condition cond = AL) OVERRIDE;
191 void vcvtis(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
192 void vcvtid(SRegister sd, DRegister dm, Condition cond = AL) OVERRIDE;
193 void vcvtsi(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
194 void vcvtdi(DRegister dd, SRegister sm, Condition cond = AL) OVERRIDE;
195 void vcvtus(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
196 void vcvtud(SRegister sd, DRegister dm, Condition cond = AL) OVERRIDE;
197 void vcvtsu(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
198 void vcvtdu(DRegister dd, SRegister sm, Condition cond = AL) OVERRIDE;
199
200 void vcmps(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
201 void vcmpd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE;
202 void vcmpsz(SRegister sd, Condition cond = AL) OVERRIDE;
203 void vcmpdz(DRegister dd, Condition cond = AL) OVERRIDE;
204 void vmstat(Condition cond = AL) OVERRIDE; // VMRS APSR_nzcv, FPSCR
205
206 void vpushs(SRegister reg, int nregs, Condition cond = AL) OVERRIDE;
207 void vpushd(DRegister reg, int nregs, Condition cond = AL) OVERRIDE;
208 void vpops(SRegister reg, int nregs, Condition cond = AL) OVERRIDE;
209 void vpopd(DRegister reg, int nregs, Condition cond = AL) OVERRIDE;
210
211 // Branch instructions.
Nicolas Geoffrayd56376c2015-05-21 12:32:34 +0000[diff] [blame]212 void b(Label* label, Condition cond = AL) OVERRIDE;
213 void bl(Label* label, Condition cond = AL) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]214 void blx(Register rm, Condition cond = AL) OVERRIDE;
215 void bx(Register rm, Condition cond = AL) OVERRIDE;
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]216 virtual void Lsl(Register rd, Register rm, uint32_t shift_imm,
217 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
218 virtual void Lsr(Register rd, Register rm, uint32_t shift_imm,
219 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
220 virtual void Asr(Register rd, Register rm, uint32_t shift_imm,
221 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
222 virtual void Ror(Register rd, Register rm, uint32_t shift_imm,
223 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
224 virtual void Rrx(Register rd, Register rm,
225 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison45fdb932014-06-25 12:37:10 -0700[diff] [blame]226
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]227 virtual void Lsl(Register rd, Register rm, Register rn,
228 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
229 virtual void Lsr(Register rd, Register rm, Register rn,
230 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
231 virtual void Asr(Register rd, Register rm, Register rn,
232 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
233 virtual void Ror(Register rd, Register rm, Register rn,
234 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]235
236 void Push(Register rd, Condition cond = AL) OVERRIDE;
237 void Pop(Register rd, Condition cond = AL) OVERRIDE;
238
239 void PushList(RegList regs, Condition cond = AL) OVERRIDE;
240 void PopList(RegList regs, Condition cond = AL) OVERRIDE;
241
242 void Mov(Register rd, Register rm, Condition cond = AL) OVERRIDE;
243
244 void CompareAndBranchIfZero(Register r, Label* label) OVERRIDE;
245 void CompareAndBranchIfNonZero(Register r, Label* label) OVERRIDE;
246
Nicolas Geoffray19a19cf2014-10-22 16:07:05 +0100[diff] [blame]247 // Memory barriers.
248 void dmb(DmbOptions flavor) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]249
Vladimir Markocf93a5c2015-06-16 11:33:24 +0000[diff] [blame]250 // Get the final position of a label after local fixup based on the old position
251 // recorded before FinalizeCode().
252 uint32_t GetAdjustedPosition(uint32_t old_position) OVERRIDE;
253
254 Literal* NewLiteral(size_t size, const uint8_t* data) OVERRIDE;
255 void LoadLiteral(Register rt, Literal* literal) OVERRIDE;
256 void LoadLiteral(Register rt, Register rt2, Literal* literal) OVERRIDE;
257 void LoadLiteral(SRegister sd, Literal* literal) OVERRIDE;
258 void LoadLiteral(DRegister dd, Literal* literal) OVERRIDE;
259
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]260 // Add signed constant value to rd. May clobber IP.
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]261 void AddConstant(Register rd, Register rn, int32_t value,
Vladimir Marko449b1092015-09-08 12:16:45 +0100[diff] [blame]262 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]263
264 // Load and Store. May clobber IP.
265 void LoadImmediate(Register rd, int32_t value, Condition cond = AL) OVERRIDE;
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]266 void MarkExceptionHandler(Label* label) OVERRIDE;
267 void LoadFromOffset(LoadOperandType type,
268 Register reg,
269 Register base,
270 int32_t offset,
271 Condition cond = AL) OVERRIDE;
272 void StoreToOffset(StoreOperandType type,
273 Register reg,
274 Register base,
275 int32_t offset,
276 Condition cond = AL) OVERRIDE;
277 void LoadSFromOffset(SRegister reg,
278 Register base,
279 int32_t offset,
280 Condition cond = AL) OVERRIDE;
281 void StoreSToOffset(SRegister reg,
282 Register base,
283 int32_t offset,
284 Condition cond = AL) OVERRIDE;
285 void LoadDFromOffset(DRegister reg,
286 Register base,
287 int32_t offset,
288 Condition cond = AL) OVERRIDE;
289 void StoreDToOffset(DRegister reg,
290 Register base,
291 int32_t offset,
292 Condition cond = AL) OVERRIDE;
293
Nicolas Geoffray3bcc8ea2014-11-28 15:00:02 +0000[diff] [blame]294 bool ShifterOperandCanHold(Register rd,
295 Register rn,
296 Opcode opcode,
297 uint32_t immediate,
298 ShifterOperand* shifter_op) OVERRIDE;
299
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]300
Ian Rogers13735952014-10-08 12:43:28 -0700[diff] [blame]301 static bool IsInstructionForExceptionHandling(uintptr_t pc);
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]302
303 // Emit data (e.g. encoded instruction or immediate) to the
304 // instruction stream.
305 void Emit(int32_t value);
306 void Bind(Label* label) OVERRIDE;
307
308 void MemoryBarrier(ManagedRegister scratch) OVERRIDE;
309
310 private:
311 void EmitType01(Condition cond,
312 int type,
313 Opcode opcode,
Vladimir Marko73cf0fb2015-07-30 15:07:22 +0100[diff] [blame]314 SetCc set_cc,
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]315 Register rn,
316 Register rd,
317 const ShifterOperand& so);
318
319 void EmitType5(Condition cond, int offset, bool link);
320
321 void EmitMemOp(Condition cond,
322 bool load,
323 bool byte,
324 Register rd,
325 const Address& ad);
326
327 void EmitMemOpAddressMode3(Condition cond,
328 int32_t mode,
329 Register rd,
330 const Address& ad);
331
332 void EmitMultiMemOp(Condition cond,
333 BlockAddressMode am,
334 bool load,
335 Register base,
336 RegList regs);
337
338 void EmitShiftImmediate(Condition cond,
339 Shift opcode,
340 Register rd,
341 Register rm,
342 const ShifterOperand& so);
343
344 void EmitShiftRegister(Condition cond,
345 Shift opcode,
346 Register rd,
347 Register rm,
348 const ShifterOperand& so);
349
350 void EmitMulOp(Condition cond,
351 int32_t opcode,
352 Register rd,
353 Register rn,
354 Register rm,
355 Register rs);
356
357 void EmitVFPsss(Condition cond,
358 int32_t opcode,
359 SRegister sd,
360 SRegister sn,
361 SRegister sm);
362
363 void EmitVFPddd(Condition cond,
364 int32_t opcode,
365 DRegister dd,
366 DRegister dn,
367 DRegister dm);
368
369 void EmitVFPsd(Condition cond,
370 int32_t opcode,
371 SRegister sd,
372 DRegister dm);
373
374 void EmitVFPds(Condition cond,
375 int32_t opcode,
376 DRegister dd,
377 SRegister sm);
378
379 void EmitVPushPop(uint32_t reg, int nregs, bool push, bool dbl, Condition cond);
380
381 void EmitBranch(Condition cond, Label* label, bool link);
382 static int32_t EncodeBranchOffset(int offset, int32_t inst);
383 static int DecodeBranchOffset(int32_t inst);
384 int32_t EncodeTstOffset(int offset, int32_t inst);
385 int DecodeTstOffset(int32_t inst);
Nicolas Geoffray3bcc8ea2014-11-28 15:00:02 +0000[diff] [blame]386 bool ShifterOperandCanHoldArm32(uint32_t immediate, ShifterOperand* shifter_op);
Dave Allison65fcc2c2014-04-28 13:45:27 -0700[diff] [blame]387};
388
389} // namespace arm
390} // namespace art
391
392#endif // ART_COMPILER_UTILS_ARM_ASSEMBLER_ARM32_H_