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review.blissroms.org / platform_bionic / ba8d4f460b51161eb82cf1006cb34a3cc1389f47 / . / libc / kernel / uapi / drm / tegra_drm.h
blob: 609957d7a0c38b82d90ab5e2767689025f831545 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_TEGRA_DRM_H_
20#define _UAPI_TEGRA_DRM_H_
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]21#include <drm/drm.h>
22#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]25struct drm_tegra_gem_create {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]26 __u64 size;
27 __u32 flags;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]29 __u32 handle;
30};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]31struct drm_tegra_gem_mmap {
32 __u32 handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]34 __u32 offset;
35};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]36struct drm_tegra_syncpt_read {
37 __u32 id;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]39 __u32 value;
40};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]41struct drm_tegra_syncpt_incr {
42 __u32 id;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]44 __u32 pad;
45};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]46struct drm_tegra_syncpt_wait {
47 __u32 id;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]49 __u32 thresh;
50 __u32 timeout;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]51 __u32 value;
52};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]54#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
55struct drm_tegra_open_channel {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]56 __u32 client;
57 __u32 pad;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]59 __u64 context;
60};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]61struct drm_tegra_close_channel {
62 __u64 context;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]64};
65struct drm_tegra_get_syncpt {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]66 __u64 context;
67 __u32 index;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
69 __u32 id;
70};
71struct drm_tegra_get_syncpt_base {
72 __u64 context;
73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
74 __u32 syncpt;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]75 __u32 id;
76};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]77struct drm_tegra_syncpt {
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]79 __u32 id;
80 __u32 incrs;
81};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]82struct drm_tegra_cmdbuf {
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]84 __u32 handle;
85 __u32 offset;
86 __u32 words;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]87 __u32 pad;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]89};
90struct drm_tegra_reloc {
91 struct {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]92 __u32 handle;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]94 __u32 offset;
95 } cmdbuf;
96 struct {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]97 __u32 handle;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]99 __u32 offset;
100 } target;
101 __u32 shift;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]102 __u32 pad;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]104};
105struct drm_tegra_waitchk {
106 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]107 __u32 offset;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]109 __u32 syncpt;
110 __u32 thresh;
111};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]112struct drm_tegra_submit {
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]114 __u64 context;
115 __u32 num_syncpts;
116 __u32 num_cmdbufs;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]117 __u32 num_relocs;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]119 __u32 num_waitchks;
120 __u32 waitchk_mask;
121 __u32 timeout;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]122 __u64 syncpts;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame^]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]124 __u64 cmdbufs;
125 __u64 relocs;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]126 __u64 waitchks;
127 __u32 fence;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame^]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]129 __u32 reserved[5];
130};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]131#define DRM_TEGRA_GEM_CREATE 0x00
132#define DRM_TEGRA_GEM_MMAP 0x01
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame^]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]134#define DRM_TEGRA_SYNCPT_READ 0x02
135#define DRM_TEGRA_SYNCPT_INCR 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]136#define DRM_TEGRA_SYNCPT_WAIT 0x04
137#define DRM_TEGRA_OPEN_CHANNEL 0x05
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame^]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]139#define DRM_TEGRA_CLOSE_CHANNEL 0x06
140#define DRM_TEGRA_GET_SYNCPT 0x07
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]141#define DRM_TEGRA_SUBMIT 0x08
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]142#define DRM_TEGRA_GET_SYNCPT_BASE 0x09
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame^]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]144#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
145#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
146#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]147#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame^]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]149#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
150#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
151#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]152#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame^]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]154#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]155#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]156#endif