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review.blissroms.org / platform_bionic / c6e5874a4c19f398eb179a23de9b1d2c06bccea0 / . / libc / kernel / uapi / drm / exynos_drm.h
blob: 47294b7f61de38a4e0c5765cd8f60d625640ecc9 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_EXYNOS_DRM_H_
20#define _UAPI_EXYNOS_DRM_H_
21#include <drm/drm.h>
22struct drm_exynos_gem_create {
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]24 uint64_t size;
25 unsigned int flags;
26 unsigned int handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]27};
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]29struct drm_exynos_gem_info {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]30 unsigned int handle;
31 unsigned int flags;
32 uint64_t size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]34};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]35struct drm_exynos_vidi_connection {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]36 unsigned int connection;
37 unsigned int extensions;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]39 uint64_t edid;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]40};
41enum e_drm_exynos_gem_mem_type {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]42 EXYNOS_BO_CONTIG = 0 << 0,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]44 EXYNOS_BO_NONCONTIG = 1 << 0,
45 EXYNOS_BO_NONCACHABLE = 0 << 1,
46 EXYNOS_BO_CACHABLE = 1 << 1,
47 EXYNOS_BO_WC = 1 << 2,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]49 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | EXYNOS_BO_WC
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]50};
51struct drm_exynos_g2d_get_ver {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]52 __u32 major;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]54 __u32 minor;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]55};
56struct drm_exynos_g2d_cmd {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]57 __u32 offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]59 __u32 data;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]60};
61enum drm_exynos_g2d_buf_type {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]62 G2D_BUF_USERPTR = 1 << 31,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
64};
65enum drm_exynos_g2d_event_type {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]66 G2D_EVENT_NOT,
67 G2D_EVENT_NONSTOP,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]69 G2D_EVENT_STOP,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]70};
71struct drm_exynos_g2d_userptr {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]72 unsigned long userptr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]74 unsigned long size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]75};
76struct drm_exynos_g2d_set_cmdlist {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]77 __u64 cmd;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]79 __u64 cmd_buf;
80 __u32 cmd_nr;
81 __u32 cmd_buf_nr;
82 __u64 event_type;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]84 __u64 user_data;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]85};
86struct drm_exynos_g2d_exec {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]87 __u64 async;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
89};
90enum drm_exynos_ops_id {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]91 EXYNOS_DRM_OPS_SRC,
92 EXYNOS_DRM_OPS_DST,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]94 EXYNOS_DRM_OPS_MAX,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]95};
96struct drm_exynos_sz {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]97 __u32 hsize;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]99 __u32 vsize;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]100};
101struct drm_exynos_pos {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]102 __u32 x;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]104 __u32 y;
105 __u32 w;
106 __u32 h;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]107};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]109enum drm_exynos_flip {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]110 EXYNOS_DRM_FLIP_NONE = (0 << 0),
111 EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
112 EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]114 EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL | EXYNOS_DRM_FLIP_HORIZONTAL,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]115};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]116enum drm_exynos_degree {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]117 EXYNOS_DRM_DEGREE_0,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]119 EXYNOS_DRM_DEGREE_90,
120 EXYNOS_DRM_DEGREE_180,
121 EXYNOS_DRM_DEGREE_270,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]122};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]124enum drm_exynos_planer {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]125 EXYNOS_DRM_PLANAR_Y,
126 EXYNOS_DRM_PLANAR_CB,
127 EXYNOS_DRM_PLANAR_CR,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]129 EXYNOS_DRM_PLANAR_MAX,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]130};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]131struct drm_exynos_ipp_prop_list {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]132 __u32 version;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]134 __u32 ipp_id;
135 __u32 count;
136 __u32 writeback;
137 __u32 flip;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]139 __u32 degree;
140 __u32 csc;
141 __u32 crop;
142 __u32 scale;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]144 __u32 refresh_min;
145 __u32 refresh_max;
146 __u32 reserved;
147 struct drm_exynos_sz crop_min;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]149 struct drm_exynos_sz crop_max;
150 struct drm_exynos_sz scale_min;
151 struct drm_exynos_sz scale_max;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]152};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]154struct drm_exynos_ipp_config {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]155 enum drm_exynos_ops_id ops_id;
156 enum drm_exynos_flip flip;
157 enum drm_exynos_degree degree;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]159 __u32 fmt;
160 struct drm_exynos_sz sz;
161 struct drm_exynos_pos pos;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]162};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]164enum drm_exynos_ipp_cmd {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]165 IPP_CMD_NONE,
166 IPP_CMD_M2M,
167 IPP_CMD_WB,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]169 IPP_CMD_OUTPUT,
170 IPP_CMD_MAX,
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]171};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]172struct drm_exynos_ipp_property {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]174 struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
175 enum drm_exynos_ipp_cmd cmd;
176 __u32 ipp_id;
177 __u32 prop_id;
178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
179 __u32 refresh_rate;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]180};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]181enum drm_exynos_ipp_buf_type {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]182 IPP_BUF_ENQUEUE,
183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
184 IPP_BUF_DEQUEUE,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]185};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]186struct drm_exynos_ipp_queue_buf {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]187 enum drm_exynos_ops_id ops_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]189 enum drm_exynos_ipp_buf_type buf_type;
190 __u32 prop_id;
191 __u32 buf_id;
192 __u32 handle[EXYNOS_DRM_PLANAR_MAX];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]194 __u32 reserved;
195 __u64 user_data;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]196};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]197enum drm_exynos_ipp_ctrl {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]199 IPP_CTRL_PLAY,
200 IPP_CTRL_STOP,
201 IPP_CTRL_PAUSE,
202 IPP_CTRL_RESUME,
203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
204 IPP_CTRL_MAX,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]205};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]206struct drm_exynos_ipp_cmd_ctrl {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]207 __u32 prop_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]209 enum drm_exynos_ipp_ctrl ctrl;
210};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]211#define DRM_EXYNOS_GEM_CREATE 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]212#define DRM_EXYNOS_GEM_GET 0x04
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]214#define DRM_EXYNOS_VIDI_CONNECTION 0x07
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]215#define DRM_EXYNOS_G2D_GET_VER 0x20
216#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
217#define DRM_EXYNOS_G2D_EXEC 0x22
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]219#define DRM_EXYNOS_IPP_GET_PROPERTY 0x30
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]220#define DRM_EXYNOS_IPP_SET_PROPERTY 0x31
221#define DRM_EXYNOS_IPP_QUEUE_BUF 0x32
222#define DRM_EXYNOS_IPP_CMD_CTRL 0x33
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]224#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
225#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
226#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
227#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]229#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
230#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
231#define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
232#define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]234#define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
235#define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]236#define DRM_EXYNOS_G2D_EVENT 0x80000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]237#define DRM_EXYNOS_IPP_EVENT 0x80000001
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]239struct drm_exynos_g2d_event {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]240 struct drm_event base;
241 __u64 user_data;
242 __u32 tv_sec;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]244 __u32 tv_usec;
245 __u32 cmdlist_no;
246 __u32 reserved;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]247};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]249struct drm_exynos_ipp_event {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]250 struct drm_event base;
251 __u64 user_data;
252 __u32 tv_sec;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]254 __u32 tv_usec;
255 __u32 prop_id;
256 __u32 reserved;
257 __u32 buf_id[EXYNOS_DRM_OPS_MAX];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]259};
260#endif