Blame - compiler/dex/quick/x86/assemble_x86.cc - platform_art

2013-07-12 13:46:57 -0700

[diff] [blame]

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#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \

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{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

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{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

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EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),

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{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

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{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),

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{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

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{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0),

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EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0),

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{ kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" },

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{ kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" },

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EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),

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{ kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" },

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{ kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" },

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{ kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

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{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

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{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

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// TODO: load/store?

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// Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.

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{ kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },

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EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES),

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EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES),

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{ kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" },

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{ kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" },

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{ kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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{ kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" },

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{ kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),

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EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),

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EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),

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EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),

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#undef EXT_0F_ENCODING_MAP

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{ kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },

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{ kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },

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{ kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },

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{ kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },

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{ kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" },

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{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

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{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

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{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

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{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

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b1eba21

2013-07-17 18:07:19 -0700

[diff] [blame]

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{ kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

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2013-07-12 13:46:57 -0700

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{ kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" },

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{ kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },

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{ kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" },

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};

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static size_t ComputeSize(const X86EncodingMap* entry, int base, int displacement, bool has_sib) {

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size_t size = 0;

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if (entry->skeleton.prefix1 > 0) {

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++size;

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if (entry->skeleton.prefix2 > 0) {

++size;

}

}

++size; // opcode

if (entry->skeleton.opcode == 0x0F) {

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++size;

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if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

if (has_sib || base == rX86_SP) {

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// SP requires a SIB byte.

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++size;

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}

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if (displacement != 0 || base == rBP) {

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// BP requires an explicit displacement, even when it's 0.

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if (entry->opcode != kX86Lea32RA) {

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DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name;

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}

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size += IS_SIMM8(displacement) ? 1 : 4;

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}

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size += entry->skeleton.immediate_bytes;

return size;

}

int X86Mir2Lir::GetInsnSize(LIR* lir) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

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DCHECK(!IsPseudoLirOp(lir->opcode));

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2013-07-12 13:46:57 -0700

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const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode];

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switch (entry->kind) {

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case kData:

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return 4; // 4 bytes of data

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case kNop:

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return lir->operands[0]; // length of nop is sole operand

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case kNullary:

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return 1; // 1 byte of opcode

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

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case kRegOpcode: // lir operands - 0: reg

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return ComputeSize(entry, 0, 0, false) - 1; // substract 1 for modrm

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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case kReg: // lir operands - 0: reg

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return ComputeSize(entry, 0, 0, false);

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case kMem: // lir operands - 0: base, 1: disp

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return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

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case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

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return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

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case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

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return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

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case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

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return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

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case kThreadReg: // lir operands - 0: disp, 1: reg

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return ComputeSize(entry, 0, lir->operands[0], false);

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case kRegReg:

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return ComputeSize(entry, 0, 0, false);

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case kRegRegStore:

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return ComputeSize(entry, 0, 0, false);

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case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

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return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

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case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

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return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

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case kRegThread: // lir operands - 0: reg, 1: disp

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return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

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case kRegImm: { // lir operands - 0: reg, 1: immediate

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size_t size = ComputeSize(entry, 0, 0, false);

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if (entry->skeleton.ax_opcode == 0) {

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return size;

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} else {

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// AX opcodes don't require the modrm byte.

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int reg = lir->operands[0];

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return size - (reg == rAX ? 1 : 0);

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}

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}

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case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

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return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

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case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

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return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

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case kThreadImm: // lir operands - 0: disp, 1: imm

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return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

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case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

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return ComputeSize(entry, 0, 0, false);

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case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

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return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

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case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

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return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

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case kMovRegImm: // lir operands - 0: reg, 1: immediate

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return 1 + entry->skeleton.immediate_bytes;

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case kShiftRegImm: // lir operands - 0: reg, 1: immediate

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// Shift by immediate one has a shorter opcode.

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return ComputeSize(entry, 0, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

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case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

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// Shift by immediate one has a shorter opcode.

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return ComputeSize(entry, lir->operands[0], lir->operands[1], false) -

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(lir->operands[2] == 1 ? 1 : 0);

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case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

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// Shift by immediate one has a shorter opcode.

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return ComputeSize(entry, lir->operands[0], lir->operands[3], true) -

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(lir->operands[4] == 1 ? 1 : 0);

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case kShiftRegCl:

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return ComputeSize(entry, 0, 0, false);

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case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

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return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

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case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

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return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

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case kRegCond: // lir operands - 0: reg, 1: cond

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return ComputeSize(entry, 0, 0, false);

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case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

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return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

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case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

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return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

446

case kJcc:

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if (lir->opcode == kX86Jcc8) {

448

return 2; // opcode + rel8

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} else {

450

DCHECK(lir->opcode == kX86Jcc32);

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return 6; // 2 byte opcode + rel32

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}

453

case kJmp:

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if (lir->opcode == kX86Jmp8) {

455

return 2; // opcode + rel8

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} else if (lir->opcode == kX86Jmp32) {

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return 5; // opcode + rel32

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} else {

459

DCHECK(lir->opcode == kX86JmpR);

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return 2; // opcode + modrm

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}

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case kCall:

463

switch (lir->opcode) {

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case kX86CallR: return 2; // opcode modrm

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case kX86CallM: // lir operands - 0: base, 1: disp

466

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

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case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

468

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

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case kX86CallT: // lir operands - 0: disp

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return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

default:

break;

}

break;

case kPcRel:

if (entry->opcode == kX86PcRelLoadRA) {

477

// lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

478

return ComputeSize(entry, lir->operands[1], 0x12345678, true);

479

} else {

480

DCHECK(entry->opcode == kX86PcRelAdr);

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

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return 5; // opcode with reg + 4 byte immediate

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

482

}

483

case kMacro:

484

DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));

485

return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +

486

ComputeSize(&X86Mir2Lir::EncodingMap[kX86Sub32RI], 0, 0, false) -

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(lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

return 0;

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

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void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry) {

496

if (entry->skeleton.prefix1 != 0) {

497

code_buffer_.push_back(entry->skeleton.prefix1);

498

if (entry->skeleton.prefix2 != 0) {

499

code_buffer_.push_back(entry->skeleton.prefix2);

500

}

501

} else {

502

DCHECK_EQ(0, entry->skeleton.prefix2);

}

}

void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) {

507

code_buffer_.push_back(entry->skeleton.opcode);

508

if (entry->skeleton.opcode == 0x0F) {

509

code_buffer_.push_back(entry->skeleton.extra_opcode1);

510

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

511

code_buffer_.push_back(entry->skeleton.extra_opcode2);

512

} else {

513

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

514

}

515

} else {

516

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

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DCHECK_EQ(0, entry->skeleton.extra_opcode2);

}

}

void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry) {

EmitPrefix(entry);

EmitOpcode(entry);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

526

static uint8_t ModrmForDisp(int base, int disp) {

527

// BP requires an explicit disp, so do not omit it in the 0 case

528

if (disp == 0 && base != rBP) {

529

return 0;

530

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

537

void X86Mir2Lir::EmitDisp(uint8_t base, int disp) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

538

// BP requires an explicit disp, so do not omit it in the 0 case

539

if (disp == 0 && base != rBP) {

540

return;

541

} else if (IS_SIMM8(disp)) {

542

code_buffer_.push_back(disp & 0xFF);

543

} else {

544

code_buffer_.push_back(disp & 0xFF);

545

code_buffer_.push_back((disp >> 8) & 0xFF);

546

code_buffer_.push_back((disp >> 16) & 0xFF);

547

code_buffer_.push_back((disp >> 24) & 0xFF);

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

551

void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp) {

552

DCHECK_LT(reg_or_opcode, 8);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

553

DCHECK_LT(base, 8);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

554

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | base;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

555

code_buffer_.push_back(modrm);

556

if (base == rX86_SP) {

557

// Special SIB for SP base

558

code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);

559

}

560

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

561

}

562

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

563

void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index,

564

int scale, int disp) {

565

DCHECK_LT(reg_or_opcode, 8);

566

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | rX86_SP;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

567

code_buffer_.push_back(modrm);

DCHECK_LT(scale, 4);

DCHECK_LT(index, 8);

DCHECK_LT(base, 8);

uint8_t sib = (scale << 6) | (index << 3) | base;

572

code_buffer_.push_back(sib);

573

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

574

}

575

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

576

void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int imm) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

577

switch (entry->skeleton.immediate_bytes) {

578

case 1:

579

DCHECK(IS_SIMM8(imm));

580

code_buffer_.push_back(imm & 0xFF);

581

break;

582

case 2:

583

DCHECK(IS_SIMM16(imm));

584

code_buffer_.push_back(imm & 0xFF);

585

code_buffer_.push_back((imm >> 8) & 0xFF);

586

break;

587

case 4:

588

code_buffer_.push_back(imm & 0xFF);

589

code_buffer_.push_back((imm >> 8) & 0xFF);

590

code_buffer_.push_back((imm >> 16) & 0xFF);

591

code_buffer_.push_back((imm >> 24) & 0xFF);

592

break;

593

default:

594

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

595

<< ") for instruction: " << entry->name;

break;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

600

void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg) {

601

EmitPrefixAndOpcode(entry);

602

// There's no 3-byte instruction with +rd

603

DCHECK(entry->skeleton.opcode != 0x0F ||

604

(entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A));

605

DCHECK(!X86_FPREG(reg));

606

DCHECK_LT(reg, 8);

607

code_buffer_.back() += reg;

608

DCHECK_EQ(0, entry->skeleton.ax_opcode);

609

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

610

}

611

612

void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) {

613

EmitPrefixAndOpcode(entry);

614

if (X86_FPREG(reg)) {

615

reg = reg & X86_FP_REG_MASK;

616

}

617

if (reg >= 4) {

618

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

619

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

620

}

621

DCHECK_LT(reg, 8);

622

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

623

code_buffer_.push_back(modrm);

624

DCHECK_EQ(0, entry->skeleton.ax_opcode);

625

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

626

}

627

628

void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) {

629

EmitPrefix(entry);

630

code_buffer_.push_back(entry->skeleton.opcode);

631

DCHECK_NE(0x0F, entry->skeleton.opcode);

632

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

633

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

634

DCHECK_NE(rX86_SP, base);

635

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

636

DCHECK_EQ(0, entry->skeleton.ax_opcode);

637

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

638

}

639

640

void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index,

641

int scale, int disp) {

642

EmitPrefixAndOpcode(entry);

643

EmitModrmSibDisp(entry->skeleton.modrm_opcode, base, index, scale, disp);

644

DCHECK_EQ(0, entry->skeleton.ax_opcode);

645

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

646

}

647

648

void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry,

649

uint8_t base, int disp, uint8_t reg) {

650

EmitPrefixAndOpcode(entry);

651

if (X86_FPREG(reg)) {

652

reg = reg & X86_FP_REG_MASK;

653

}

654

if (reg >= 4) {

655

DCHECK(strchr(entry->name, '8') == NULL ||

656

entry->opcode == kX86Movzx8RM || entry->opcode == kX86Movsx8RM)

657

<< entry->name << " " << static_cast<int>(reg)

658

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

659

}

660

EmitModrmDisp(reg, base, disp);

661

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

662

DCHECK_EQ(0, entry->skeleton.ax_opcode);

663

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

664

}

665

666

void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry,

667

uint8_t reg, uint8_t base, int disp) {

668

// Opcode will flip operands.

669

EmitMemReg(entry, base, disp, reg);

670

}

671

672

void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index,

673

int scale, int disp) {

674

EmitPrefixAndOpcode(entry);

675

if (X86_FPREG(reg)) {

676

reg = reg & X86_FP_REG_MASK;

677

}

678

EmitModrmSibDisp(reg, base, index, scale, disp);

679

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

680

DCHECK_EQ(0, entry->skeleton.ax_opcode);

681

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

682

}

683

684

void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp,

685

uint8_t reg) {

686

// Opcode will flip operands.

687

EmitRegArray(entry, reg, base, index, scale, disp);

688

}

689

690

void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) {

691

DCHECK_NE(entry->skeleton.prefix1, 0);

692

EmitPrefixAndOpcode(entry);

693

if (X86_FPREG(reg)) {

694

reg = reg & X86_FP_REG_MASK;

695

}

696

if (reg >= 4) {

697

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

698

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

699

}

700

DCHECK_LT(reg, 8);

701

uint8_t modrm = (0 << 6) | (reg << 3) | rBP;

702

code_buffer_.push_back(modrm);

703

code_buffer_.push_back(disp & 0xFF);

704

code_buffer_.push_back((disp >> 8) & 0xFF);

705

code_buffer_.push_back((disp >> 16) & 0xFF);

706

code_buffer_.push_back((disp >> 24) & 0xFF);

707

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

708

DCHECK_EQ(0, entry->skeleton.ax_opcode);

709

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

710

}

711

712

void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) {

713

EmitPrefixAndOpcode(entry);

714

if (X86_FPREG(reg1)) {

715

reg1 = reg1 & X86_FP_REG_MASK;

716

}

717

if (X86_FPREG(reg2)) {

718

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

723

code_buffer_.push_back(modrm);

724

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

725

DCHECK_EQ(0, entry->skeleton.ax_opcode);

726

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

727

}

728

729

void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry,

730

uint8_t reg1, uint8_t reg2, int32_t imm) {

731

EmitPrefixAndOpcode(entry);

732

if (X86_FPREG(reg1)) {

733

reg1 = reg1 & X86_FP_REG_MASK;

734

}

735

if (X86_FPREG(reg2)) {

736

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

741

code_buffer_.push_back(modrm);

742

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

743

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

747

void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

748

if (entry->skeleton.prefix1 != 0) {

749

code_buffer_.push_back(entry->skeleton.prefix1);

750

if (entry->skeleton.prefix2 != 0) {

751

code_buffer_.push_back(entry->skeleton.prefix2);

752

}

753

} else {

754

DCHECK_EQ(0, entry->skeleton.prefix2);

755

}

756

if (reg == rAX && entry->skeleton.ax_opcode != 0) {

757

code_buffer_.push_back(entry->skeleton.ax_opcode);

758

} else {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

759

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

760

if (X86_FPREG(reg)) {

761

reg = reg & X86_FP_REG_MASK;

762

}

763

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

764

code_buffer_.push_back(modrm);

765

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

766

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

767

}

768

769

void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

770

EmitPrefixAndOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

771

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

772

code_buffer_.push_back(modrm);

773

code_buffer_.push_back(disp & 0xFF);

774

code_buffer_.push_back((disp >> 8) & 0xFF);

775

code_buffer_.push_back((disp >> 16) & 0xFF);

776

code_buffer_.push_back((disp >> 24) & 0xFF);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

777

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

778

DCHECK_EQ(entry->skeleton.ax_opcode, 0);

779

}

780

781

void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

782

DCHECK_LT(reg, 8);

783

code_buffer_.push_back(0xB8 + reg);

784

code_buffer_.push_back(imm & 0xFF);

785

code_buffer_.push_back((imm >> 8) & 0xFF);

786

code_buffer_.push_back((imm >> 16) & 0xFF);

787

code_buffer_.push_back((imm >> 24) & 0xFF);

788

}

789

790

void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

791

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

792

if (imm != 1) {

793

code_buffer_.push_back(entry->skeleton.opcode);

794

} else {

795

// Shorter encoding for 1 bit shift

796

code_buffer_.push_back(entry->skeleton.ax_opcode);

797

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

798

DCHECK_NE(0x0F, entry->skeleton.opcode);

799

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

800

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

801

if (reg >= 4) {

802

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

803

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

804

}

805

DCHECK_LT(reg, 8);

806

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

807

code_buffer_.push_back(modrm);

808

if (imm != 1) {

809

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

810

DCHECK(IS_SIMM8(imm));

811

code_buffer_.push_back(imm & 0xFF);

}

}

void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl) {

816

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

817

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

818

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

819

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

820

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

821

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

822

DCHECK_LT(reg, 8);

823

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

824

code_buffer_.push_back(modrm);

825

DCHECK_EQ(0, entry->skeleton.ax_opcode);

826

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

827

}

828

829

void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) {

830

if (entry->skeleton.prefix1 != 0) {

831

code_buffer_.push_back(entry->skeleton.prefix1);

832

if (entry->skeleton.prefix2 != 0) {

833

code_buffer_.push_back(entry->skeleton.prefix2);

834

}

835

} else {

836

DCHECK_EQ(0, entry->skeleton.prefix2);

837

}

838

DCHECK_EQ(0, entry->skeleton.ax_opcode);

839

DCHECK_EQ(0x0F, entry->skeleton.opcode);

840

code_buffer_.push_back(0x0F);

841

DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);

842

code_buffer_.push_back(0x90 | condition);

843

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

844

DCHECK_LT(reg, 8);

845

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

846

code_buffer_.push_back(modrm);

847

DCHECK_EQ(entry->skeleton.immediate_bytes, 0);

848

}

849

850

void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int rel) {

851

if (entry->opcode == kX86Jmp8) {

852

DCHECK(IS_SIMM8(rel));

853

code_buffer_.push_back(0xEB);

854

code_buffer_.push_back(rel & 0xFF);

855

} else if (entry->opcode == kX86Jmp32) {

856

code_buffer_.push_back(0xE9);

857

code_buffer_.push_back(rel & 0xFF);

858

code_buffer_.push_back((rel >> 8) & 0xFF);

859

code_buffer_.push_back((rel >> 16) & 0xFF);

860

code_buffer_.push_back((rel >> 24) & 0xFF);

861

} else {

862

DCHECK(entry->opcode == kX86JmpR);

863

code_buffer_.push_back(entry->skeleton.opcode);

864

uint8_t reg = static_cast<uint8_t>(rel);

865

DCHECK_LT(reg, 8);

866

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

867

code_buffer_.push_back(modrm);

}

}

void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc) {

872

DCHECK_LT(cc, 16);

873

if (entry->opcode == kX86Jcc8) {

874

DCHECK(IS_SIMM8(rel));

875

code_buffer_.push_back(0x70 | cc);

876

code_buffer_.push_back(rel & 0xFF);

877

} else {

878

DCHECK(entry->opcode == kX86Jcc32);

879

code_buffer_.push_back(0x0F);

880

code_buffer_.push_back(0x80 | cc);

881

code_buffer_.push_back(rel & 0xFF);

882

code_buffer_.push_back((rel >> 8) & 0xFF);

883

code_buffer_.push_back((rel >> 16) & 0xFF);

884

code_buffer_.push_back((rel >> 24) & 0xFF);

}

}

void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

889

EmitPrefixAndOpcode(entry);

890

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

891

DCHECK_EQ(0, entry->skeleton.ax_opcode);

892

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

893

}

894

895

void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int disp) {

896

DCHECK_NE(entry->skeleton.prefix1, 0);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

897

EmitPrefixAndOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

898

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

899

code_buffer_.push_back(modrm);

900

code_buffer_.push_back(disp & 0xFF);

901

code_buffer_.push_back((disp >> 8) & 0xFF);

902

code_buffer_.push_back((disp >> 16) & 0xFF);

903

code_buffer_.push_back((disp >> 24) & 0xFF);

904

DCHECK_EQ(0, entry->skeleton.ax_opcode);

905

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

906

}

907

908

void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, uint8_t reg,

909

int base_or_table, uint8_t index, int scale, int table_or_disp) {

910

int disp;

911

if (entry->opcode == kX86PcRelLoadRA) {

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

912

Mir2Lir::EmbeddedData *tab_rec =

913

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

914

disp = tab_rec->offset;

915

} else {

916

DCHECK(entry->opcode == kX86PcRelAdr);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

917

Mir2Lir::EmbeddedData *tab_rec =

918

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(base_or_table));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

919

disp = tab_rec->offset;

920

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

921

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

922

if (X86_FPREG(reg)) {

923

reg = reg & X86_FP_REG_MASK;

924

}

925

DCHECK_LT(reg, 8);

926

if (entry->opcode == kX86PcRelLoadRA) {

927

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

928

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

929

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

930

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

931

uint8_t modrm = (2 << 6) | (reg << 3) | rX86_SP;

932

code_buffer_.push_back(modrm);

933

DCHECK_LT(scale, 4);

934

DCHECK_LT(index, 8);

935

DCHECK_LT(base_or_table, 8);

936

uint8_t base = static_cast<uint8_t>(base_or_table);

937

uint8_t sib = (scale << 6) | (index << 3) | base;

938

code_buffer_.push_back(sib);

939

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

940

} else {

941

code_buffer_.push_back(entry->skeleton.opcode + reg);

942

}

943

code_buffer_.push_back(disp & 0xFF);

944

code_buffer_.push_back((disp >> 8) & 0xFF);

945

code_buffer_.push_back((disp >> 16) & 0xFF);

946

code_buffer_.push_back((disp >> 24) & 0xFF);

947

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

948

DCHECK_EQ(0, entry->skeleton.ax_opcode);

949

}

950

951

void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset) {

952

DCHECK(entry->opcode == kX86StartOfMethod) << entry->name;

953

code_buffer_.push_back(0xE8); // call +0

954

code_buffer_.push_back(0);

955

code_buffer_.push_back(0);

956

code_buffer_.push_back(0);

957

code_buffer_.push_back(0);

958

959

DCHECK_LT(reg, 8);

960

code_buffer_.push_back(0x58 + reg); // pop reg

961

962

EmitRegImm(&X86Mir2Lir::EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */);

963

}

964

965

void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) {

966

UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " "

967

<< BuildInsnString(entry->fmt, lir, 0);

968

for (int i = 0; i < GetInsnSize(lir); ++i) {

969

code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3

}

}

/*

* Assemble the LIR into binary instruction format. Note that we may

975

* discover that pc-relative displacements may not fit the selected

976

* instruction. In those cases we will try to substitute a new code

977

* sequence or request that the trace be shortened and retried.

978

*/

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

979

AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

980

LIR *lir;

981

AssemblerStatus res = kSuccess; // Assume success

982

983

const bool kVerbosePcFixup = false;

984

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

985

if (IsPseudoLirOp(lir->opcode)) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

continue;

}

if (lir->flags.is_nop) {

continue;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

993

if (lir->flags.fixup != kFixupNone) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

994

switch (lir->opcode) {

995

case kX86Jcc8: {

996

LIR *target_lir = lir->target;

997

DCHECK(target_lir != NULL);

998

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

999

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1000

if (IS_SIMM8(lir->operands[0])) {

1001

pc = lir->offset + 2 /* opcode + rel8 */;

1002

} else {

1003

pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1004

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1005

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1006

delta = target - pc;

1007

if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1008

if (kVerbosePcFixup) {

1009

LOG(INFO) << "Retry for JCC growth at " << lir->offset

1010

<< " delta: " << delta << " old delta: " << lir->operands[0];

1011

}

1012

lir->opcode = kX86Jcc32;

1013

SetupResourceMasks(lir);

1014

res = kRetryAll;

1015

}

1016

if (kVerbosePcFixup) {

1017

LOG(INFO) << "Source:";

1018

DumpLIRInsn(lir, 0);

1019

LOG(INFO) << "Target:";

1020

DumpLIRInsn(target_lir, 0);

1021

LOG(INFO) << "Delta " << delta;

1022

}

1023

lir->operands[0] = delta;

break;

}

case kX86Jcc32: {

LIR *target_lir = lir->target;

1028

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1029

CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1030

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1031

int delta = target - pc;

1032

if (kVerbosePcFixup) {

1033

LOG(INFO) << "Source:";

1034

DumpLIRInsn(lir, 0);

1035

LOG(INFO) << "Target:";

1036

DumpLIRInsn(target_lir, 0);

1037

LOG(INFO) << "Delta " << delta;

1038

}

1039

lir->operands[0] = delta;

break;

}

case kX86Jmp8: {

LIR *target_lir = lir->target;

1044

DCHECK(target_lir != NULL);

1045

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1046

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1047

if (IS_SIMM8(lir->operands[0])) {

1048

pc = lir->offset + 2 /* opcode + rel8 */;

1049

} else {

1050

pc = lir->offset + 5 /* opcode + rel32 */;

1051

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1052

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1053

delta = target - pc;

1054

if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) {

1055

// Useless branch

buzbee

252254b

2013-09-08 16:20:53 -0700

[diff] [blame]

1056

NopLIR(lir);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1057

if (kVerbosePcFixup) {

1058

LOG(INFO) << "Retry for useless branch at " << lir->offset;

1059

}

1060

res = kRetryAll;

1061

} else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1062

if (kVerbosePcFixup) {

1063

LOG(INFO) << "Retry for JMP growth at " << lir->offset;

1064

}

1065

lir->opcode = kX86Jmp32;

1066

SetupResourceMasks(lir);

1067

res = kRetryAll;

1068

}

1069

lir->operands[0] = delta;

break;

}

case kX86Jmp32: {

LIR *target_lir = lir->target;

1074

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1075

CodeOffset pc = lir->offset + 5 /* opcode + rel32 */;

1076

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1077

int delta = target - pc;

1078

lir->operands[0] = delta;

break;

}

default:

break;

}

}

/*

* If one of the pc-relative instructions expanded we'll have

1088

* to make another pass. Don't bother to fully assemble the

1089

* instruction.

1090

*/

1091

if (res != kSuccess) {

1092

continue;

1093

}

1094

CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size());

1095

const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode];

1096

size_t starting_cbuf_size = code_buffer_.size();

1097

switch (entry->kind) {

1098

case kData: // 4 bytes of data

1099

code_buffer_.push_back(lir->operands[0]);

1100

break;

1101

case kNullary: // 1 byte of opcode

1102

DCHECK_EQ(0, entry->skeleton.prefix1);

1103

DCHECK_EQ(0, entry->skeleton.prefix2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

1104

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1105

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1106

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1107

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1108

break;

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

1109

case kRegOpcode: // lir operands - 0: reg

1110

EmitOpRegOpcode(entry, lir->operands[0]);

1111

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1112

case kReg: // lir operands - 0: reg

1113

EmitOpReg(entry, lir->operands[0]);

1114

break;

1115

case kMem: // lir operands - 0: base, 1: disp

1116

EmitOpMem(entry, lir->operands[0], lir->operands[1]);

1117

break;

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame^]

1118

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

1119

EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]);

1120

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1121

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

1122

EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1123

break;

1124

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

1125

EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1126

lir->operands[3], lir->operands[4]);

1127

break;

1128

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

1129

EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1130

break;

1131

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

1132

EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1133

lir->operands[3], lir->operands[4]);

1134

break;

1135

case kRegThread: // lir operands - 0: reg, 1: disp

1136

EmitRegThread(entry, lir->operands[0], lir->operands[1]);

1137

break;

1138

case kRegReg: // lir operands - 0: reg1, 1: reg2

1139

EmitRegReg(entry, lir->operands[0], lir->operands[1]);

1140

break;

1141

case kRegRegStore: // lir operands - 0: reg2, 1: reg1

1142

EmitRegReg(entry, lir->operands[1], lir->operands[0]);

1143

break;

1144

case kRegRegImm:

1145

EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1146

break;

1147

case kRegImm: // lir operands - 0: reg, 1: immediate

1148

EmitRegImm(entry, lir->operands[0], lir->operands[1]);

1149

break;

1150

case kThreadImm: // lir operands - 0: disp, 1: immediate

1151

EmitThreadImm(entry, lir->operands[0], lir->operands[1]);

1152

break;

1153

case kMovRegImm: // lir operands - 0: reg, 1: immediate

1154

EmitMovRegImm(entry, lir->operands[0], lir->operands[1]);

1155

break;

1156

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

1157

EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]);

1158

break;

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

1159

case kShiftRegCl: // lir operands - 0: reg, 1: cl

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1160

EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]);

1161

break;

1162

case kRegCond: // lir operands - 0: reg, 1: condition

1163

EmitRegCond(entry, lir->operands[0], lir->operands[1]);

1164

break;

1165

case kJmp: // lir operands - 0: rel

1166

EmitJmp(entry, lir->operands[0]);

1167

break;

1168

case kJcc: // lir operands - 0: rel, 1: CC, target assigned

1169

EmitJcc(entry, lir->operands[0], lir->operands[1]);

1170

break;

1171

case kCall:

1172

switch (entry->opcode) {

1173

case kX86CallM: // lir operands - 0: base, 1: disp

1174

EmitCallMem(entry, lir->operands[0], lir->operands[1]);

1175

break;

1176

case kX86CallT: // lir operands - 0: disp

1177

EmitCallThread(entry, lir->operands[0]);

1178

break;

1179

default:

1180

EmitUnimplemented(entry, lir);

break;

}

break;

case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

1185

EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1186

lir->operands[3], lir->operands[4]);

1187

break;

1188

case kMacro:

1189

EmitMacro(entry, lir->operands[0], lir->offset);

1190

break;

1191

default:

1192

EmitUnimplemented(entry, lir);

1193

break;

1194

}

1195

CHECK_EQ(static_cast<size_t>(GetInsnSize(lir)),

1196

code_buffer_.size() - starting_cbuf_size)

1197

<< "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name;

}

return res;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1202

// LIR offset assignment.

1203

// TODO: consolidate w/ Arm assembly mechanism.

1204

int X86Mir2Lir::AssignInsnOffsets() {

LIR* lir;

int offset = 0;

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

1209

lir->offset = offset;

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1210

if (LIKELY(!IsPseudoLirOp(lir->opcode))) {

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1211

if (!lir->flags.is_nop) {

1212

offset += lir->flags.size;

1213

}

1214

} else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) {

1215

if (offset & 0x2) {

1216

offset += 2;

1217

lir->operands[0] = 1;

1218

} else {

1219

lir->operands[0] = 0;

1220

}

1221

}

1222

/* Pseudo opcodes don't consume space */

}

return offset;

}

/*

* Walk the compilation unit and assign offsets to instructions

1229

* and literals and compute the total size of the compiled unit.

1230

* TODO: consolidate w/ Arm assembly mechanism.

1231

*/

1232

void X86Mir2Lir::AssignOffsets() {

1233

int offset = AssignInsnOffsets();

1234

1235

/* Const values have to be word aligned */

1236

offset = (offset + 3) & ~3;

1237

1238

/* Set up offsets for literals */

1239

data_offset_ = offset;

1240

1241

offset = AssignLiteralOffset(offset);

1242

1243

offset = AssignSwitchTablesOffset(offset);

1244

1245

offset = AssignFillArrayDataOffset(offset);

1246

1247

total_size_ = offset;

}

/*

* Go over each instruction in the list and calculate the offset from the top

1252

* before sending them off to the assembler. If out-of-range branch distance is

1253

* seen rearrange the instructions a bit to correct it.

1254

* TODO: consolidate w/ Arm assembly mechanism.

1255

*/

1256

void X86Mir2Lir::AssembleLIR() {

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1257

cu_->NewTimingSplit("Assemble");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1258

AssignOffsets();

1259

int assembler_retries = 0;

1260

/*

1261

* Assemble here. Note that we generate code with optimistic assumptions

1262

* and if found now to work, we'll have to redo the sequence and retry.

*/

while (true) {

AssemblerStatus res = AssembleInstructions(0);

1267

if (res == kSuccess) {

break;

} else {

assembler_retries++;

if (assembler_retries > MAX_ASSEMBLER_RETRIES) {

1272

CodegenDump();

1273

LOG(FATAL) << "Assembler error - too many retries";

1274

}

1275

// Redo offsets and try again

1276

AssignOffsets();

1277

code_buffer_.clear();

}

}

// Install literals

InstallLiteralPools();

1283

1284

// Install switch tables

1285

InstallSwitchTables();

1286

1287

// Install fill array data

1288

InstallFillArrayData();

1289

1290

// Create the mapping table and native offset to reference map.

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1291

cu_->NewTimingSplit("PcMappingTable");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1292

CreateMappingTables();

1293

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1294

cu_->NewTimingSplit("GcMap");

buzbee