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review.blissroms.org / platform_art / a61f49539a59b610e557b5513695295639496750 / . / compiler / dex / quick / x86 / assemble_x86.cc
blob: 0e302608d824dbc06716c646b2ec7a5b5cda67c3 [file] [log] [blame]
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "codegen_x86.h"
18#include "dex/quick/mir_to_lir-inl.h"
19#include "x86_lir.h"
20
21namespace art {
22
23#define MAX_ASSEMBLER_RETRIES 50
24
25const X86EncodingMap X86Mir2Lir::EncodingMap[kX86Last] = {
26 { kX8632BitData, kData, IS_UNARY_OP, { 0, 0, 0x00, 0, 0, 0, 0, 4 }, "data", "0x!0d" },
27 { kX86Bkpt, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xCC, 0, 0, 0, 0, 0 }, "int 3", "" },
28 { kX86Nop, kNop, IS_UNARY_OP, { 0, 0, 0x90, 0, 0, 0, 0, 0 }, "nop", "" },
29
30#define ENCODING_MAP(opname, mem_use, reg_def, uses_ccodes, \
31 rm8_r8, rm32_r32, \
32 r8_rm8, r32_rm32, \
33 ax8_i8, ax32_i32, \
34 rm8_i8, rm8_i8_modrm, \
35 rm32_i32, rm32_i32_modrm, \
36 rm32_i8, rm32_i8_modrm) \
37{ kX86 ## opname ## 8MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8MR", "[!0r+!1d],!2r" }, \
38{ kX86 ## opname ## 8AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8AR", "[!0r+!1r<<!2d+!3d],!4r" }, \
39{ kX86 ## opname ## 8TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8TR", "fs:[!0d],!1r" }, \
40{ kX86 ## opname ## 8RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RR", "!0r,!1r" }, \
41{ kX86 ## opname ## 8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RM", "!0r,[!1r+!2d]" }, \
42{ kX86 ## opname ## 8RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \
43{ kX86 ## opname ## 8RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RT", "!0r,fs:[!1d]" }, \
44{ kX86 ## opname ## 8RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, ax8_i8, 1 }, #opname "8RI", "!0r,!1d" }, \
45{ kX86 ## opname ## 8MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \
46{ kX86 ## opname ## 8AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
47{ kX86 ## opname ## 8TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8TI", "fs:[!0d],!1d" }, \
48 \
49{ kX86 ## opname ## 16MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16MR", "[!0r+!1d],!2r" }, \
50{ kX86 ## opname ## 16AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \
51{ kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16TR", "fs:[!0d],!1r" }, \
52{ kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RR", "!0r,!1r" }, \
53{ kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RM", "!0r,[!1r+!2d]" }, \
54{ kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \
55{ kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RT", "!0r,fs:[!1d]" }, \
56{ kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2 }, #opname "16RI", "!0r,!1d" }, \
57{ kX86 ## opname ## 16MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16MI", "[!0r+!1d],!2d" }, \
58{ kX86 ## opname ## 16AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
59{ kX86 ## opname ## 16TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16TI", "fs:[!0d],!1d" }, \
60{ kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16RI8", "!0r,!1d" }, \
61{ kX86 ## opname ## 16MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16MI8", "[!0r+!1d],!2d" }, \
62{ kX86 ## opname ## 16AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \
63{ kX86 ## opname ## 16TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16TI8", "fs:[!0d],!1d" }, \
64 \
65{ kX86 ## opname ## 32MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32MR", "[!0r+!1d],!2r" }, \
66{ kX86 ## opname ## 32AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \
67{ kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32TR", "fs:[!0d],!1r" }, \
68{ kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RR", "!0r,!1r" }, \
69{ kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RM", "!0r,[!1r+!2d]" }, \
70{ kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \
71{ kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RT", "!0r,fs:[!1d]" }, \
72{ kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4 }, #opname "32RI", "!0r,!1d" }, \
73{ kX86 ## opname ## 32MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32MI", "[!0r+!1d],!2d" }, \
74{ kX86 ## opname ## 32AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
75{ kX86 ## opname ## 32TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32TI", "fs:[!0d],!1d" }, \
76{ kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32RI8", "!0r,!1d" }, \
77{ kX86 ## opname ## 32MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32MI8", "[!0r+!1d],!2d" }, \
78{ kX86 ## opname ## 32AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \
79{ kX86 ## opname ## 32TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32TI8", "fs:[!0d],!1d" }
80
81ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0,
82 0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */,
83 0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */,
84 0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */,
85 0x80, 0x0 /* RegMem8/imm8 */,
86 0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */),
87ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0,
88 0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */,
89 0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */,
90 0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */,
91 0x80, 0x1 /* RegMem8/imm8 */,
92 0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */),
93ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,
94 0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */,
95 0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */,
96 0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */,
97 0x80, 0x2 /* RegMem8/imm8 */,
98 0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */),
99ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,
100 0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */,
101 0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */,
102 0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */,
103 0x80, 0x3 /* RegMem8/imm8 */,
104 0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */),
105ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0,
106 0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */,
107 0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */,
108 0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */,
109 0x80, 0x4 /* RegMem8/imm8 */,
110 0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */),
111ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0,
112 0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */,
113 0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */,
114 0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */,
115 0x80, 0x5 /* RegMem8/imm8 */,
116 0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */),
117ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0,
118 0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */,
119 0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */,
120 0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */,
121 0x80, 0x6 /* RegMem8/imm8 */,
122 0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */),
123ENCODING_MAP(Cmp, IS_LOAD, 0, 0,
124 0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */,
125 0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */,
126 0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */,
127 0x80, 0x7 /* RegMem8/imm8 */,
128 0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */),
129#undef ENCODING_MAP
130
131 { kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RRI", "!0r,!1r,!2d" },
132 { kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RMI", "!0r,[!1r+!2d],!3d" },
133 { kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },
134
135 { kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RRI", "!0r,!1r,!2d" },
136 { kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RMI", "!0r,[!1r+!2d],!3d" },
137 { kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },
138 { kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RRI8", "!0r,!1r,!2d" },
139 { kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" },
140 { kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" },
141
142 { kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8MR", "[!0r+!1d],!2r" },
143 { kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" },
144 { kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8TR", "fs:[!0d],!1r" },
145 { kX86Mov8RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RR", "!0r,!1r" },
146 { kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RM", "!0r,[!1r+!2d]" },
147 { kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" },
148 { kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RT", "!0r,fs:[!1d]" },
149 { kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1 }, "Mov8RI", "!0r,!1d" },
150 { kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8MI", "[!0r+!1d],!2d" },
151 { kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" },
152 { kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8TI", "fs:[!0d],!1d" },
153
154 { kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16MR", "[!0r+!1d],!2r" },
155 { kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" },
156 { kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0 }, "Mov16TR", "fs:[!0d],!1r" },
157 { kX86Mov16RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RR", "!0r,!1r" },
158 { kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RM", "!0r,[!1r+!2d]" },
159 { kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" },
160 { kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RT", "!0r,fs:[!1d]" },
161 { kX86Mov16RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2 }, "Mov16RI", "!0r,!1d" },
162 { kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16MI", "[!0r+!1d],!2d" },
163 { kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" },
164 { kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2 }, "Mov16TI", "fs:[!0d],!1d" },
165
166 { kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32MR", "[!0r+!1d],!2r" },
167 { kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" },
168 { kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32TR", "fs:[!0d],!1r" },
169 { kX86Mov32RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RR", "!0r,!1r" },
170 { kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RM", "!0r,[!1r+!2d]" },
171 { kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" },
172 { kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RT", "!0r,fs:[!1d]" },
173 { kX86Mov32RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "Mov32RI", "!0r,!1d" },
174 { kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32MI", "[!0r+!1d],!2d" },
175 { kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" },
176 { kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32TI", "fs:[!0d],!1d" },
177
178 { kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" },
179
180#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \
181{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \
182{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \
183{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
184{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \
185{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \
186{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \
187 \
188{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \
189{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \
190{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
191{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \
192{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \
193{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \
194 \
195{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \
196{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \
197{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
198{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \
199{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \
200{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }
201
202 SHIFT_ENCODING_MAP(Rol, 0x0),
203 SHIFT_ENCODING_MAP(Ror, 0x1),
204 SHIFT_ENCODING_MAP(Rcl, 0x2),
205 SHIFT_ENCODING_MAP(Rcr, 0x3),
206 SHIFT_ENCODING_MAP(Sal, 0x4),
207 SHIFT_ENCODING_MAP(Shr, 0x5),
208 SHIFT_ENCODING_MAP(Sar, 0x7),
209#undef SHIFT_ENCODING_MAP
210
211 { kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0}, "Cmc", "" },
212
213 { kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" },
214 { kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" },
215 { kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" },
216 { kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" },
217 { kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" },
218 { kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" },
219 { kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" },
220 { kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" },
221 { kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" },
222 { kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0}, "Test32RR", "!0r,!1r" },
223
224#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \
225 reg, reg_kind, reg_flags, \
226 mem, mem_kind, mem_flags, \
227 arr, arr_kind, arr_flags, imm, \
228 b_flags, hw_flags, w_flags, \
229 b_format, hw_format, w_format) \
230{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, #b_format "!0r" }, \
231{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, #b_format "[!0r+!1d]" }, \
232{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, #b_format "[!0r+!1r<<!2d+!3d]" }, \
233{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, #hw_format "!0r" }, \
234{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, #hw_format "[!0r+!1d]" }, \
235{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, #hw_format "[!0r+!1r<<!2d+!3d]" }, \
236{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, #w_format "!0r" }, \
237{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, #w_format "[!0r+!1d]" }, \
238{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, #w_format "[!0r+!1r<<!2d+!3d]" }
239
240 UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),
241 UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),
242
243 UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),
244 UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),
245 UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),
246 UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),
247#undef UNARY_ENCODING_MAP
248
249#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \
250{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \
251{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \
252{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }
253
254 EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),
255 { kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },
256 { kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },
257
258 EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),
259 { kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },
260 { kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },
261
262 EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),
263 EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),
264 EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),
265 EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),
266 EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),
267 EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),
268 EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES),
269 EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES),
270 EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES),
271 EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES),
272 EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0),
273 EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0),
274 EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0),
275 EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0),
276 EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0),
277 EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0),
278 EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),
279 EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),
280 EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0),
281 EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0),
282 EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0),
283 EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0),
284
285 { kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" },
286 { kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" },
287
288 EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),
289 { kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" },
290 { kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" },
291 { kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },
292
293 { kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },
294 { kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },
295 { kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },
296
297 // TODO: load/store?
298 // Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.
299 { kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },
300
301 EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES),
302 EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES),
303
304 { kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" },
305 { kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" },
306 { kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },
307 { kX86LockCmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "!0r,!1r" },
308 { kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" },
309 { kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },
310
311 EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),
312 EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),
313 EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),
314 EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),
315#undef EXT_0F_ENCODING_MAP
316
317 { kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },
318 { kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },
319 { kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },
320 { kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },
321 { kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" },
322 { kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },
323 { kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },
324 { kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },
325 { kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },
Brian Carlstromb1eba212013-07-17 18:07:19 -0700[diff] [blame]326 { kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]327
328 { kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" },
329 { kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },
330 { kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" },
331};
332
333static size_t ComputeSize(const X86EncodingMap* entry, int base, int displacement, bool has_sib) {
334 size_t size = 0;
335 if (entry->skeleton.prefix1 > 0) {
336 ++size;
337 if (entry->skeleton.prefix2 > 0) {
338 ++size;
339 }
340 }
341 ++size; // opcode
342 if (entry->skeleton.opcode == 0x0F) {
343 ++size;
344 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {
345 ++size;
346 }
347 }
348 ++size; // modrm
349 if (has_sib || base == rX86_SP) {
350 // SP requires a SIB byte.
351 ++size;
352 }
353 if (displacement != 0 || base == rBP) {
354 // BP requires an explicit displacement, even when it's 0.
355 if (entry->opcode != kX86Lea32RA) {
356 DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name;
357 }
358 size += IS_SIMM8(displacement) ? 1 : 4;
359 }
360 size += entry->skeleton.immediate_bytes;
361 return size;
362}
363
364int X86Mir2Lir::GetInsnSize(LIR* lir) {
buzbee409fe942013-10-11 10:49:56 -0700[diff] [blame]365 DCHECK(!IsPseudoLirOp(lir->opcode));
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]366 const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode];
367 switch (entry->kind) {
368 case kData:
369 return 4; // 4 bytes of data
370 case kNop:
371 return lir->operands[0]; // length of nop is sole operand
372 case kNullary:
373 return 1; // 1 byte of opcode
374 case kReg: // lir operands - 0: reg
375 return ComputeSize(entry, 0, 0, false);
376 case kMem: // lir operands - 0: base, 1: disp
377 return ComputeSize(entry, lir->operands[0], lir->operands[1], false);
378 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp
379 return ComputeSize(entry, lir->operands[0], lir->operands[3], true);
380 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg
381 return ComputeSize(entry, lir->operands[0], lir->operands[1], false);
382 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg
383 return ComputeSize(entry, lir->operands[0], lir->operands[3], true);
384 case kThreadReg: // lir operands - 0: disp, 1: reg
385 return ComputeSize(entry, 0, lir->operands[0], false);
386 case kRegReg:
387 return ComputeSize(entry, 0, 0, false);
388 case kRegRegStore:
389 return ComputeSize(entry, 0, 0, false);
390 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp
391 return ComputeSize(entry, lir->operands[1], lir->operands[2], false);
392 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp
393 return ComputeSize(entry, lir->operands[1], lir->operands[4], true);
394 case kRegThread: // lir operands - 0: reg, 1: disp
395 return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit
396 case kRegImm: { // lir operands - 0: reg, 1: immediate
397 size_t size = ComputeSize(entry, 0, 0, false);
398 if (entry->skeleton.ax_opcode == 0) {
399 return size;
400 } else {
401 // AX opcodes don't require the modrm byte.
402 int reg = lir->operands[0];
403 return size - (reg == rAX ? 1 : 0);
404 }
405 }
406 case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate
407 return ComputeSize(entry, lir->operands[0], lir->operands[1], false);
408 case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate
409 return ComputeSize(entry, lir->operands[0], lir->operands[3], true);
410 case kThreadImm: // lir operands - 0: disp, 1: imm
411 return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit
412 case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm
413 return ComputeSize(entry, 0, 0, false);
414 case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm
415 return ComputeSize(entry, lir->operands[1], lir->operands[2], false);
416 case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm
417 return ComputeSize(entry, lir->operands[1], lir->operands[4], true);
418 case kMovRegImm: // lir operands - 0: reg, 1: immediate
419 return 1 + entry->skeleton.immediate_bytes;
420 case kShiftRegImm: // lir operands - 0: reg, 1: immediate
421 // Shift by immediate one has a shorter opcode.
422 return ComputeSize(entry, 0, 0, false) - (lir->operands[1] == 1 ? 1 : 0);
423 case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate
424 // Shift by immediate one has a shorter opcode.
425 return ComputeSize(entry, lir->operands[0], lir->operands[1], false) -
426 (lir->operands[2] == 1 ? 1 : 0);
427 case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate
428 // Shift by immediate one has a shorter opcode.
429 return ComputeSize(entry, lir->operands[0], lir->operands[3], true) -
430 (lir->operands[4] == 1 ? 1 : 0);
431 case kShiftRegCl:
432 return ComputeSize(entry, 0, 0, false);
433 case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl
434 return ComputeSize(entry, lir->operands[0], lir->operands[1], false);
435 case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg
436 return ComputeSize(entry, lir->operands[0], lir->operands[3], true);
437 case kRegCond: // lir operands - 0: reg, 1: cond
438 return ComputeSize(entry, 0, 0, false);
439 case kMemCond: // lir operands - 0: base, 1: disp, 2: cond
440 return ComputeSize(entry, lir->operands[0], lir->operands[1], false);
441 case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond
442 return ComputeSize(entry, lir->operands[0], lir->operands[3], true);
443 case kJcc:
444 if (lir->opcode == kX86Jcc8) {
445 return 2; // opcode + rel8
446 } else {
447 DCHECK(lir->opcode == kX86Jcc32);
448 return 6; // 2 byte opcode + rel32
449 }
450 case kJmp:
451 if (lir->opcode == kX86Jmp8) {
452 return 2; // opcode + rel8
453 } else if (lir->opcode == kX86Jmp32) {
454 return 5; // opcode + rel32
455 } else {
456 DCHECK(lir->opcode == kX86JmpR);
457 return 2; // opcode + modrm
458 }
459 case kCall:
460 switch (lir->opcode) {
461 case kX86CallR: return 2; // opcode modrm
462 case kX86CallM: // lir operands - 0: base, 1: disp
463 return ComputeSize(entry, lir->operands[0], lir->operands[1], false);
464 case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp
465 return ComputeSize(entry, lir->operands[0], lir->operands[3], true);
466 case kX86CallT: // lir operands - 0: disp
467 return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit
468 default:
469 break;
470 }
471 break;
472 case kPcRel:
473 if (entry->opcode == kX86PcRelLoadRA) {
474 // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table
475 return ComputeSize(entry, lir->operands[1], 0x12345678, true);
476 } else {
477 DCHECK(entry->opcode == kX86PcRelAdr);
Brian Carlstrom7934ac22013-07-26 10:54:15 -0700[diff] [blame]478 return 5; // opcode with reg + 4 byte immediate
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]479 }
480 case kMacro:
481 DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));
482 return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +
483 ComputeSize(&X86Mir2Lir::EncodingMap[kX86Sub32RI], 0, 0, false) -
484 (lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding
485 default:
486 break;
487 }
488 UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;
489 return 0;
490}
491
492static uint8_t ModrmForDisp(int base, int disp) {
493 // BP requires an explicit disp, so do not omit it in the 0 case
494 if (disp == 0 && base != rBP) {
495 return 0;
496 } else if (IS_SIMM8(disp)) {
497 return 1;
498 } else {
499 return 2;
500 }
501}
502
503void X86Mir2Lir::EmitDisp(int base, int disp) {
504 // BP requires an explicit disp, so do not omit it in the 0 case
505 if (disp == 0 && base != rBP) {
506 return;
507 } else if (IS_SIMM8(disp)) {
508 code_buffer_.push_back(disp & 0xFF);
509 } else {
510 code_buffer_.push_back(disp & 0xFF);
511 code_buffer_.push_back((disp >> 8) & 0xFF);
512 code_buffer_.push_back((disp >> 16) & 0xFF);
513 code_buffer_.push_back((disp >> 24) & 0xFF);
514 }
515}
516
517void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) {
518 if (entry->skeleton.prefix1 != 0) {
519 code_buffer_.push_back(entry->skeleton.prefix1);
520 if (entry->skeleton.prefix2 != 0) {
521 code_buffer_.push_back(entry->skeleton.prefix2);
522 }
523 } else {
524 DCHECK_EQ(0, entry->skeleton.prefix2);
525 }
526 code_buffer_.push_back(entry->skeleton.opcode);
527 if (entry->skeleton.opcode == 0x0F) {
528 code_buffer_.push_back(entry->skeleton.extra_opcode1);
529 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {
530 code_buffer_.push_back(entry->skeleton.extra_opcode2);
531 } else {
532 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
533 }
534 } else {
535 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
536 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
537 }
538 if (X86_FPREG(reg)) {
539 reg = reg & X86_FP_REG_MASK;
540 }
541 if (reg >= 4) {
542 DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)
543 << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);
544 }
545 DCHECK_LT(reg, 8);
546 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;
547 code_buffer_.push_back(modrm);
548 DCHECK_EQ(0, entry->skeleton.ax_opcode);
549 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
550}
551
552void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) {
553 if (entry->skeleton.prefix1 != 0) {
554 code_buffer_.push_back(entry->skeleton.prefix1);
555 if (entry->skeleton.prefix2 != 0) {
556 code_buffer_.push_back(entry->skeleton.prefix2);
557 }
558 } else {
559 DCHECK_EQ(0, entry->skeleton.prefix2);
560 }
561 code_buffer_.push_back(entry->skeleton.opcode);
562 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
563 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
564 DCHECK_LT(entry->skeleton.modrm_opcode, 8);
565 DCHECK_LT(base, 8);
566 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;
567 code_buffer_.push_back(modrm);
568 EmitDisp(base, disp);
569 DCHECK_EQ(0, entry->skeleton.ax_opcode);
570 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
571}
572
573void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry,
574 uint8_t base, int disp, uint8_t reg) {
575 if (entry->skeleton.prefix1 != 0) {
576 code_buffer_.push_back(entry->skeleton.prefix1);
577 if (entry->skeleton.prefix2 != 0) {
578 code_buffer_.push_back(entry->skeleton.prefix2);
579 }
580 } else {
581 DCHECK_EQ(0, entry->skeleton.prefix2);
582 }
583 code_buffer_.push_back(entry->skeleton.opcode);
584 if (entry->skeleton.opcode == 0x0F) {
585 code_buffer_.push_back(entry->skeleton.extra_opcode1);
586 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {
587 code_buffer_.push_back(entry->skeleton.extra_opcode2);
588 } else {
589 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
590 }
591 } else {
592 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
593 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
594 }
595 if (X86_FPREG(reg)) {
596 reg = reg & X86_FP_REG_MASK;
597 }
598 if (reg >= 4) {
599 DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)
600 << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);
601 }
602 DCHECK_LT(reg, 8);
603 DCHECK_LT(base, 8);
604 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg << 3) | base;
605 code_buffer_.push_back(modrm);
606 if (base == rX86_SP) {
607 // Special SIB for SP base
608 code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);
609 }
610 EmitDisp(base, disp);
611 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
612 DCHECK_EQ(0, entry->skeleton.ax_opcode);
613 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
614}
615
616void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry,
617 uint8_t reg, uint8_t base, int disp) {
618 // Opcode will flip operands.
619 EmitMemReg(entry, base, disp, reg);
620}
621
622void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index,
623 int scale, int disp) {
624 if (entry->skeleton.prefix1 != 0) {
625 code_buffer_.push_back(entry->skeleton.prefix1);
626 if (entry->skeleton.prefix2 != 0) {
627 code_buffer_.push_back(entry->skeleton.prefix2);
628 }
629 } else {
630 DCHECK_EQ(0, entry->skeleton.prefix2);
631 }
632 code_buffer_.push_back(entry->skeleton.opcode);
633 if (entry->skeleton.opcode == 0x0F) {
634 code_buffer_.push_back(entry->skeleton.extra_opcode1);
635 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {
636 code_buffer_.push_back(entry->skeleton.extra_opcode2);
637 } else {
638 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
639 }
640 } else {
641 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
642 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
643 }
644 if (X86_FPREG(reg)) {
645 reg = reg & X86_FP_REG_MASK;
646 }
647 DCHECK_LT(reg, 8);
648 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg << 3) | rX86_SP;
649 code_buffer_.push_back(modrm);
650 DCHECK_LT(scale, 4);
651 DCHECK_LT(index, 8);
652 DCHECK_LT(base, 8);
653 uint8_t sib = (scale << 6) | (index << 3) | base;
654 code_buffer_.push_back(sib);
655 EmitDisp(base, disp);
656 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
657 DCHECK_EQ(0, entry->skeleton.ax_opcode);
658 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
659}
660
661void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp,
662 uint8_t reg) {
663 // Opcode will flip operands.
664 EmitRegArray(entry, reg, base, index, scale, disp);
665}
666
667void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) {
668 DCHECK_NE(entry->skeleton.prefix1, 0);
669 code_buffer_.push_back(entry->skeleton.prefix1);
670 if (entry->skeleton.prefix2 != 0) {
671 code_buffer_.push_back(entry->skeleton.prefix2);
672 }
673 code_buffer_.push_back(entry->skeleton.opcode);
674 if (entry->skeleton.opcode == 0x0F) {
675 code_buffer_.push_back(entry->skeleton.extra_opcode1);
676 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {
677 code_buffer_.push_back(entry->skeleton.extra_opcode2);
678 } else {
679 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
680 }
681 } else {
682 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
683 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
684 }
685 if (X86_FPREG(reg)) {
686 reg = reg & X86_FP_REG_MASK;
687 }
688 if (reg >= 4) {
689 DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)
690 << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);
691 }
692 DCHECK_LT(reg, 8);
693 uint8_t modrm = (0 << 6) | (reg << 3) | rBP;
694 code_buffer_.push_back(modrm);
695 code_buffer_.push_back(disp & 0xFF);
696 code_buffer_.push_back((disp >> 8) & 0xFF);
697 code_buffer_.push_back((disp >> 16) & 0xFF);
698 code_buffer_.push_back((disp >> 24) & 0xFF);
699 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
700 DCHECK_EQ(0, entry->skeleton.ax_opcode);
701 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
702}
703
704void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) {
705 if (entry->skeleton.prefix1 != 0) {
706 code_buffer_.push_back(entry->skeleton.prefix1);
707 if (entry->skeleton.prefix2 != 0) {
708 code_buffer_.push_back(entry->skeleton.prefix2);
709 }
710 } else {
711 DCHECK_EQ(0, entry->skeleton.prefix2);
712 }
713 code_buffer_.push_back(entry->skeleton.opcode);
714 if (entry->skeleton.opcode == 0x0F) {
715 code_buffer_.push_back(entry->skeleton.extra_opcode1);
716 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {
717 code_buffer_.push_back(entry->skeleton.extra_opcode2);
718 } else {
719 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
720 }
721 } else {
722 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
723 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
724 }
725 if (X86_FPREG(reg1)) {
726 reg1 = reg1 & X86_FP_REG_MASK;
727 }
728 if (X86_FPREG(reg2)) {
729 reg2 = reg2 & X86_FP_REG_MASK;
730 }
731 DCHECK_LT(reg1, 8);
732 DCHECK_LT(reg2, 8);
733 uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;
734 code_buffer_.push_back(modrm);
735 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
736 DCHECK_EQ(0, entry->skeleton.ax_opcode);
737 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
738}
739
740void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry,
741 uint8_t reg1, uint8_t reg2, int32_t imm) {
742 if (entry->skeleton.prefix1 != 0) {
743 code_buffer_.push_back(entry->skeleton.prefix1);
744 if (entry->skeleton.prefix2 != 0) {
745 code_buffer_.push_back(entry->skeleton.prefix2);
746 }
747 } else {
748 DCHECK_EQ(0, entry->skeleton.prefix2);
749 }
750 code_buffer_.push_back(entry->skeleton.opcode);
751 if (entry->skeleton.opcode == 0x0F) {
752 code_buffer_.push_back(entry->skeleton.extra_opcode1);
753 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {
754 code_buffer_.push_back(entry->skeleton.extra_opcode2);
755 } else {
756 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
757 }
758 } else {
759 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
760 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
761 }
762 if (X86_FPREG(reg1)) {
763 reg1 = reg1 & X86_FP_REG_MASK;
764 }
765 if (X86_FPREG(reg2)) {
766 reg2 = reg2 & X86_FP_REG_MASK;
767 }
768 DCHECK_LT(reg1, 8);
769 DCHECK_LT(reg2, 8);
770 uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;
771 code_buffer_.push_back(modrm);
772 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
773 DCHECK_EQ(0, entry->skeleton.ax_opcode);
774 switch (entry->skeleton.immediate_bytes) {
775 case 1:
776 DCHECK(IS_SIMM8(imm));
777 code_buffer_.push_back(imm & 0xFF);
778 break;
779 case 2:
780 DCHECK(IS_SIMM16(imm));
781 code_buffer_.push_back(imm & 0xFF);
782 code_buffer_.push_back((imm >> 8) & 0xFF);
783 break;
784 case 4:
785 code_buffer_.push_back(imm & 0xFF);
786 code_buffer_.push_back((imm >> 8) & 0xFF);
787 code_buffer_.push_back((imm >> 16) & 0xFF);
788 code_buffer_.push_back((imm >> 24) & 0xFF);
789 break;
790 default:
791 LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes
792 << ") for instruction: " << entry->name;
793 break;
794 }
795}
796
797void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {
798 if (entry->skeleton.prefix1 != 0) {
799 code_buffer_.push_back(entry->skeleton.prefix1);
800 if (entry->skeleton.prefix2 != 0) {
801 code_buffer_.push_back(entry->skeleton.prefix2);
802 }
803 } else {
804 DCHECK_EQ(0, entry->skeleton.prefix2);
805 }
806 if (reg == rAX && entry->skeleton.ax_opcode != 0) {
807 code_buffer_.push_back(entry->skeleton.ax_opcode);
808 } else {
809 code_buffer_.push_back(entry->skeleton.opcode);
810 if (entry->skeleton.opcode == 0x0F) {
811 code_buffer_.push_back(entry->skeleton.extra_opcode1);
812 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {
813 code_buffer_.push_back(entry->skeleton.extra_opcode2);
814 } else {
815 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
816 }
817 } else {
818 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
819 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
820 }
821 if (X86_FPREG(reg)) {
822 reg = reg & X86_FP_REG_MASK;
823 }
824 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;
825 code_buffer_.push_back(modrm);
826 }
827 switch (entry->skeleton.immediate_bytes) {
828 case 1:
829 DCHECK(IS_SIMM8(imm));
830 code_buffer_.push_back(imm & 0xFF);
831 break;
832 case 2:
833 DCHECK(IS_SIMM16(imm));
834 code_buffer_.push_back(imm & 0xFF);
835 code_buffer_.push_back((imm >> 8) & 0xFF);
836 break;
837 case 4:
838 code_buffer_.push_back(imm & 0xFF);
839 code_buffer_.push_back((imm >> 8) & 0xFF);
840 code_buffer_.push_back((imm >> 16) & 0xFF);
841 code_buffer_.push_back((imm >> 24) & 0xFF);
842 break;
843 default:
844 LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes
845 << ") for instruction: " << entry->name;
846 break;
847 }
848}
849
850void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) {
851 if (entry->skeleton.prefix1 != 0) {
852 code_buffer_.push_back(entry->skeleton.prefix1);
853 if (entry->skeleton.prefix2 != 0) {
854 code_buffer_.push_back(entry->skeleton.prefix2);
855 }
856 } else {
857 DCHECK_EQ(0, entry->skeleton.prefix2);
858 }
859 code_buffer_.push_back(entry->skeleton.opcode);
860 if (entry->skeleton.opcode == 0x0F) {
861 code_buffer_.push_back(entry->skeleton.extra_opcode1);
862 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {
863 code_buffer_.push_back(entry->skeleton.extra_opcode2);
864 } else {
865 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
866 }
867 } else {
868 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
869 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
870 }
871 uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;
872 code_buffer_.push_back(modrm);
873 code_buffer_.push_back(disp & 0xFF);
874 code_buffer_.push_back((disp >> 8) & 0xFF);
875 code_buffer_.push_back((disp >> 16) & 0xFF);
876 code_buffer_.push_back((disp >> 24) & 0xFF);
877 switch (entry->skeleton.immediate_bytes) {
878 case 1:
879 DCHECK(IS_SIMM8(imm));
880 code_buffer_.push_back(imm & 0xFF);
881 break;
882 case 2:
883 DCHECK(IS_SIMM16(imm));
884 code_buffer_.push_back(imm & 0xFF);
885 code_buffer_.push_back((imm >> 8) & 0xFF);
886 break;
887 case 4:
888 code_buffer_.push_back(imm & 0xFF);
889 code_buffer_.push_back((imm >> 8) & 0xFF);
890 code_buffer_.push_back((imm >> 16) & 0xFF);
891 code_buffer_.push_back((imm >> 24) & 0xFF);
892 break;
893 default:
894 LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes
895 << ") for instruction: " << entry->name;
896 break;
897 }
898 DCHECK_EQ(entry->skeleton.ax_opcode, 0);
899}
900
901void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {
902 DCHECK_LT(reg, 8);
903 code_buffer_.push_back(0xB8 + reg);
904 code_buffer_.push_back(imm & 0xFF);
905 code_buffer_.push_back((imm >> 8) & 0xFF);
906 code_buffer_.push_back((imm >> 16) & 0xFF);
907 code_buffer_.push_back((imm >> 24) & 0xFF);
908}
909
910void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {
911 if (entry->skeleton.prefix1 != 0) {
912 code_buffer_.push_back(entry->skeleton.prefix1);
913 if (entry->skeleton.prefix2 != 0) {
914 code_buffer_.push_back(entry->skeleton.prefix2);
915 }
916 } else {
917 DCHECK_EQ(0, entry->skeleton.prefix2);
918 }
919 if (imm != 1) {
920 code_buffer_.push_back(entry->skeleton.opcode);
921 } else {
922 // Shorter encoding for 1 bit shift
923 code_buffer_.push_back(entry->skeleton.ax_opcode);
924 }
925 if (entry->skeleton.opcode == 0x0F) {
926 code_buffer_.push_back(entry->skeleton.extra_opcode1);
927 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {
928 code_buffer_.push_back(entry->skeleton.extra_opcode2);
929 } else {
930 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
931 }
932 } else {
933 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
934 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
935 }
936 if (reg >= 4) {
937 DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)
938 << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);
939 }
940 DCHECK_LT(reg, 8);
941 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;
942 code_buffer_.push_back(modrm);
943 if (imm != 1) {
944 DCHECK_EQ(entry->skeleton.immediate_bytes, 1);
945 DCHECK(IS_SIMM8(imm));
946 code_buffer_.push_back(imm & 0xFF);
947 }
948}
949
950void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl) {
951 DCHECK_EQ(cl, static_cast<uint8_t>(rCX));
952 if (entry->skeleton.prefix1 != 0) {
953 code_buffer_.push_back(entry->skeleton.prefix1);
954 if (entry->skeleton.prefix2 != 0) {
955 code_buffer_.push_back(entry->skeleton.prefix2);
956 }
957 } else {
958 DCHECK_EQ(0, entry->skeleton.prefix2);
959 }
960 code_buffer_.push_back(entry->skeleton.opcode);
961 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
962 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
963 DCHECK_LT(reg, 8);
964 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;
965 code_buffer_.push_back(modrm);
966 DCHECK_EQ(0, entry->skeleton.ax_opcode);
967 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
968}
969
970void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) {
971 if (entry->skeleton.prefix1 != 0) {
972 code_buffer_.push_back(entry->skeleton.prefix1);
973 if (entry->skeleton.prefix2 != 0) {
974 code_buffer_.push_back(entry->skeleton.prefix2);
975 }
976 } else {
977 DCHECK_EQ(0, entry->skeleton.prefix2);
978 }
979 DCHECK_EQ(0, entry->skeleton.ax_opcode);
980 DCHECK_EQ(0x0F, entry->skeleton.opcode);
981 code_buffer_.push_back(0x0F);
982 DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);
983 code_buffer_.push_back(0x90 | condition);
984 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
985 DCHECK_LT(reg, 8);
986 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;
987 code_buffer_.push_back(modrm);
988 DCHECK_EQ(entry->skeleton.immediate_bytes, 0);
989}
990
991void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int rel) {
992 if (entry->opcode == kX86Jmp8) {
993 DCHECK(IS_SIMM8(rel));
994 code_buffer_.push_back(0xEB);
995 code_buffer_.push_back(rel & 0xFF);
996 } else if (entry->opcode == kX86Jmp32) {
997 code_buffer_.push_back(0xE9);
998 code_buffer_.push_back(rel & 0xFF);
999 code_buffer_.push_back((rel >> 8) & 0xFF);
1000 code_buffer_.push_back((rel >> 16) & 0xFF);
1001 code_buffer_.push_back((rel >> 24) & 0xFF);
1002 } else {
1003 DCHECK(entry->opcode == kX86JmpR);
1004 code_buffer_.push_back(entry->skeleton.opcode);
1005 uint8_t reg = static_cast<uint8_t>(rel);
1006 DCHECK_LT(reg, 8);
1007 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;
1008 code_buffer_.push_back(modrm);
1009 }
1010}
1011
1012void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc) {
1013 DCHECK_LT(cc, 16);
1014 if (entry->opcode == kX86Jcc8) {
1015 DCHECK(IS_SIMM8(rel));
1016 code_buffer_.push_back(0x70 | cc);
1017 code_buffer_.push_back(rel & 0xFF);
1018 } else {
1019 DCHECK(entry->opcode == kX86Jcc32);
1020 code_buffer_.push_back(0x0F);
1021 code_buffer_.push_back(0x80 | cc);
1022 code_buffer_.push_back(rel & 0xFF);
1023 code_buffer_.push_back((rel >> 8) & 0xFF);
1024 code_buffer_.push_back((rel >> 16) & 0xFF);
1025 code_buffer_.push_back((rel >> 24) & 0xFF);
1026 }
1027}
1028
1029void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) {
1030 if (entry->skeleton.prefix1 != 0) {
1031 code_buffer_.push_back(entry->skeleton.prefix1);
1032 if (entry->skeleton.prefix2 != 0) {
1033 code_buffer_.push_back(entry->skeleton.prefix2);
1034 }
1035 } else {
1036 DCHECK_EQ(0, entry->skeleton.prefix2);
1037 }
1038 code_buffer_.push_back(entry->skeleton.opcode);
1039 if (entry->skeleton.opcode == 0x0F) {
1040 code_buffer_.push_back(entry->skeleton.extra_opcode1);
1041 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {
1042 code_buffer_.push_back(entry->skeleton.extra_opcode2);
1043 } else {
1044 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
1045 }
1046 } else {
1047 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
1048 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
1049 }
1050 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;
1051 code_buffer_.push_back(modrm);
1052 if (base == rX86_SP) {
1053 // Special SIB for SP base
1054 code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);
1055 }
1056 EmitDisp(base, disp);
1057 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1058 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1059}
1060
1061void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int disp) {
1062 DCHECK_NE(entry->skeleton.prefix1, 0);
1063 code_buffer_.push_back(entry->skeleton.prefix1);
1064 if (entry->skeleton.prefix2 != 0) {
1065 code_buffer_.push_back(entry->skeleton.prefix2);
1066 }
1067 code_buffer_.push_back(entry->skeleton.opcode);
1068 if (entry->skeleton.opcode == 0x0F) {
1069 code_buffer_.push_back(entry->skeleton.extra_opcode1);
1070 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {
1071 code_buffer_.push_back(entry->skeleton.extra_opcode2);
1072 } else {
1073 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
1074 }
1075 } else {
1076 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
1077 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
1078 }
1079 uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;
1080 code_buffer_.push_back(modrm);
1081 code_buffer_.push_back(disp & 0xFF);
1082 code_buffer_.push_back((disp >> 8) & 0xFF);
1083 code_buffer_.push_back((disp >> 16) & 0xFF);
1084 code_buffer_.push_back((disp >> 24) & 0xFF);
1085 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1086 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1087}
1088
1089void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, uint8_t reg,
1090 int base_or_table, uint8_t index, int scale, int table_or_disp) {
1091 int disp;
1092 if (entry->opcode == kX86PcRelLoadRA) {
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]1093 Mir2Lir::EmbeddedData *tab_rec =
1094 reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp));
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1095 disp = tab_rec->offset;
1096 } else {
1097 DCHECK(entry->opcode == kX86PcRelAdr);
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]1098 Mir2Lir::EmbeddedData *tab_rec =
1099 reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(base_or_table));
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1100 disp = tab_rec->offset;
1101 }
1102 if (entry->skeleton.prefix1 != 0) {
1103 code_buffer_.push_back(entry->skeleton.prefix1);
1104 if (entry->skeleton.prefix2 != 0) {
1105 code_buffer_.push_back(entry->skeleton.prefix2);
1106 }
1107 } else {
1108 DCHECK_EQ(0, entry->skeleton.prefix2);
1109 }
1110 if (X86_FPREG(reg)) {
1111 reg = reg & X86_FP_REG_MASK;
1112 }
1113 DCHECK_LT(reg, 8);
1114 if (entry->opcode == kX86PcRelLoadRA) {
1115 code_buffer_.push_back(entry->skeleton.opcode);
1116 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
1117 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
1118 uint8_t modrm = (2 << 6) | (reg << 3) | rX86_SP;
1119 code_buffer_.push_back(modrm);
1120 DCHECK_LT(scale, 4);
1121 DCHECK_LT(index, 8);
1122 DCHECK_LT(base_or_table, 8);
1123 uint8_t base = static_cast<uint8_t>(base_or_table);
1124 uint8_t sib = (scale << 6) | (index << 3) | base;
1125 code_buffer_.push_back(sib);
1126 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1127 } else {
1128 code_buffer_.push_back(entry->skeleton.opcode + reg);
1129 }
1130 code_buffer_.push_back(disp & 0xFF);
1131 code_buffer_.push_back((disp >> 8) & 0xFF);
1132 code_buffer_.push_back((disp >> 16) & 0xFF);
1133 code_buffer_.push_back((disp >> 24) & 0xFF);
1134 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1135 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1136}
1137
1138void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset) {
1139 DCHECK(entry->opcode == kX86StartOfMethod) << entry->name;
1140 code_buffer_.push_back(0xE8); // call +0
1141 code_buffer_.push_back(0);
1142 code_buffer_.push_back(0);
1143 code_buffer_.push_back(0);
1144 code_buffer_.push_back(0);
1145
1146 DCHECK_LT(reg, 8);
1147 code_buffer_.push_back(0x58 + reg); // pop reg
1148
1149 EmitRegImm(&X86Mir2Lir::EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */);
1150}
1151
1152void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) {
1153 UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " "
1154 << BuildInsnString(entry->fmt, lir, 0);
1155 for (int i = 0; i < GetInsnSize(lir); ++i) {
1156 code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3
1157 }
1158}
1159
1160/*
1161 * Assemble the LIR into binary instruction format. Note that we may
1162 * discover that pc-relative displacements may not fit the selected
1163 * instruction. In those cases we will try to substitute a new code
1164 * sequence or request that the trace be shortened and retried.
1165 */
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]1166AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1167 LIR *lir;
1168 AssemblerStatus res = kSuccess; // Assume success
1169
1170 const bool kVerbosePcFixup = false;
1171 for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {
buzbee409fe942013-10-11 10:49:56 -0700[diff] [blame]1172 if (IsPseudoLirOp(lir->opcode)) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1173 continue;
1174 }
1175
1176 if (lir->flags.is_nop) {
1177 continue;
1178 }
1179
buzbeeb48819d2013-09-14 16:15:25 -0700[diff] [blame]1180 if (lir->flags.fixup != kFixupNone) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1181 switch (lir->opcode) {
1182 case kX86Jcc8: {
1183 LIR *target_lir = lir->target;
1184 DCHECK(target_lir != NULL);
1185 int delta = 0;
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]1186 CodeOffset pc;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1187 if (IS_SIMM8(lir->operands[0])) {
1188 pc = lir->offset + 2 /* opcode + rel8 */;
1189 } else {
1190 pc = lir->offset + 6 /* 2 byte opcode + rel32 */;
1191 }
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]1192 CodeOffset target = target_lir->offset;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1193 delta = target - pc;
1194 if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {
1195 if (kVerbosePcFixup) {
1196 LOG(INFO) << "Retry for JCC growth at " << lir->offset
1197 << " delta: " << delta << " old delta: " << lir->operands[0];
1198 }
1199 lir->opcode = kX86Jcc32;
1200 SetupResourceMasks(lir);
1201 res = kRetryAll;
1202 }
1203 if (kVerbosePcFixup) {
1204 LOG(INFO) << "Source:";
1205 DumpLIRInsn(lir, 0);
1206 LOG(INFO) << "Target:";
1207 DumpLIRInsn(target_lir, 0);
1208 LOG(INFO) << "Delta " << delta;
1209 }
1210 lir->operands[0] = delta;
1211 break;
1212 }
1213 case kX86Jcc32: {
1214 LIR *target_lir = lir->target;
1215 DCHECK(target_lir != NULL);
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]1216 CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */;
1217 CodeOffset target = target_lir->offset;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1218 int delta = target - pc;
1219 if (kVerbosePcFixup) {
1220 LOG(INFO) << "Source:";
1221 DumpLIRInsn(lir, 0);
1222 LOG(INFO) << "Target:";
1223 DumpLIRInsn(target_lir, 0);
1224 LOG(INFO) << "Delta " << delta;
1225 }
1226 lir->operands[0] = delta;
1227 break;
1228 }
1229 case kX86Jmp8: {
1230 LIR *target_lir = lir->target;
1231 DCHECK(target_lir != NULL);
1232 int delta = 0;
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]1233 CodeOffset pc;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1234 if (IS_SIMM8(lir->operands[0])) {
1235 pc = lir->offset + 2 /* opcode + rel8 */;
1236 } else {
1237 pc = lir->offset + 5 /* opcode + rel32 */;
1238 }
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]1239 CodeOffset target = target_lir->offset;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1240 delta = target - pc;
1241 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) {
1242 // Useless branch
buzbee252254b2013-09-08 16:20:53 -0700[diff] [blame]1243 NopLIR(lir);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1244 if (kVerbosePcFixup) {
1245 LOG(INFO) << "Retry for useless branch at " << lir->offset;
1246 }
1247 res = kRetryAll;
1248 } else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {
1249 if (kVerbosePcFixup) {
1250 LOG(INFO) << "Retry for JMP growth at " << lir->offset;
1251 }
1252 lir->opcode = kX86Jmp32;
1253 SetupResourceMasks(lir);
1254 res = kRetryAll;
1255 }
1256 lir->operands[0] = delta;
1257 break;
1258 }
1259 case kX86Jmp32: {
1260 LIR *target_lir = lir->target;
1261 DCHECK(target_lir != NULL);
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]1262 CodeOffset pc = lir->offset + 5 /* opcode + rel32 */;
1263 CodeOffset target = target_lir->offset;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1264 int delta = target - pc;
1265 lir->operands[0] = delta;
1266 break;
1267 }
1268 default:
1269 break;
1270 }
1271 }
1272
1273 /*
1274 * If one of the pc-relative instructions expanded we'll have
1275 * to make another pass. Don't bother to fully assemble the
1276 * instruction.
1277 */
1278 if (res != kSuccess) {
1279 continue;
1280 }
1281 CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size());
1282 const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode];
1283 size_t starting_cbuf_size = code_buffer_.size();
1284 switch (entry->kind) {
1285 case kData: // 4 bytes of data
1286 code_buffer_.push_back(lir->operands[0]);
1287 break;
1288 case kNullary: // 1 byte of opcode
1289 DCHECK_EQ(0, entry->skeleton.prefix1);
1290 DCHECK_EQ(0, entry->skeleton.prefix2);
1291 code_buffer_.push_back(entry->skeleton.opcode);
1292 if (entry->skeleton.extra_opcode1 != 0) {
1293 code_buffer_.push_back(entry->skeleton.extra_opcode1);
1294 if (entry->skeleton.extra_opcode2 != 0) {
1295 code_buffer_.push_back(entry->skeleton.extra_opcode2);
1296 }
1297 } else {
1298 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
1299 }
1300 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1301 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1302 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1303 break;
1304 case kReg: // lir operands - 0: reg
1305 EmitOpReg(entry, lir->operands[0]);
1306 break;
1307 case kMem: // lir operands - 0: base, 1: disp
1308 EmitOpMem(entry, lir->operands[0], lir->operands[1]);
1309 break;
1310 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg
1311 EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1312 break;
1313 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg
1314 EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2],
1315 lir->operands[3], lir->operands[4]);
1316 break;
1317 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp
1318 EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1319 break;
1320 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp
1321 EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2],
1322 lir->operands[3], lir->operands[4]);
1323 break;
1324 case kRegThread: // lir operands - 0: reg, 1: disp
1325 EmitRegThread(entry, lir->operands[0], lir->operands[1]);
1326 break;
1327 case kRegReg: // lir operands - 0: reg1, 1: reg2
1328 EmitRegReg(entry, lir->operands[0], lir->operands[1]);
1329 break;
1330 case kRegRegStore: // lir operands - 0: reg2, 1: reg1
1331 EmitRegReg(entry, lir->operands[1], lir->operands[0]);
1332 break;
1333 case kRegRegImm:
1334 EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1335 break;
1336 case kRegImm: // lir operands - 0: reg, 1: immediate
1337 EmitRegImm(entry, lir->operands[0], lir->operands[1]);
1338 break;
1339 case kThreadImm: // lir operands - 0: disp, 1: immediate
1340 EmitThreadImm(entry, lir->operands[0], lir->operands[1]);
1341 break;
1342 case kMovRegImm: // lir operands - 0: reg, 1: immediate
1343 EmitMovRegImm(entry, lir->operands[0], lir->operands[1]);
1344 break;
1345 case kShiftRegImm: // lir operands - 0: reg, 1: immediate
1346 EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]);
1347 break;
Brian Carlstrom7934ac22013-07-26 10:54:15 -0700[diff] [blame]1348 case kShiftRegCl: // lir operands - 0: reg, 1: cl
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1349 EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]);
1350 break;
1351 case kRegCond: // lir operands - 0: reg, 1: condition
1352 EmitRegCond(entry, lir->operands[0], lir->operands[1]);
1353 break;
1354 case kJmp: // lir operands - 0: rel
1355 EmitJmp(entry, lir->operands[0]);
1356 break;
1357 case kJcc: // lir operands - 0: rel, 1: CC, target assigned
1358 EmitJcc(entry, lir->operands[0], lir->operands[1]);
1359 break;
1360 case kCall:
1361 switch (entry->opcode) {
1362 case kX86CallM: // lir operands - 0: base, 1: disp
1363 EmitCallMem(entry, lir->operands[0], lir->operands[1]);
1364 break;
1365 case kX86CallT: // lir operands - 0: disp
1366 EmitCallThread(entry, lir->operands[0]);
1367 break;
1368 default:
1369 EmitUnimplemented(entry, lir);
1370 break;
1371 }
1372 break;
1373 case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table
1374 EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2],
1375 lir->operands[3], lir->operands[4]);
1376 break;
1377 case kMacro:
1378 EmitMacro(entry, lir->operands[0], lir->offset);
1379 break;
1380 default:
1381 EmitUnimplemented(entry, lir);
1382 break;
1383 }
1384 CHECK_EQ(static_cast<size_t>(GetInsnSize(lir)),
1385 code_buffer_.size() - starting_cbuf_size)
1386 << "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name;
1387 }
1388 return res;
1389}
1390
buzbeeb48819d2013-09-14 16:15:25 -0700[diff] [blame]1391// LIR offset assignment.
1392// TODO: consolidate w/ Arm assembly mechanism.
1393int X86Mir2Lir::AssignInsnOffsets() {
1394 LIR* lir;
1395 int offset = 0;
1396
1397 for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {
1398 lir->offset = offset;
buzbee409fe942013-10-11 10:49:56 -0700[diff] [blame]1399 if (LIKELY(!IsPseudoLirOp(lir->opcode))) {
buzbeeb48819d2013-09-14 16:15:25 -0700[diff] [blame]1400 if (!lir->flags.is_nop) {
1401 offset += lir->flags.size;
1402 }
1403 } else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) {
1404 if (offset & 0x2) {
1405 offset += 2;
1406 lir->operands[0] = 1;
1407 } else {
1408 lir->operands[0] = 0;
1409 }
1410 }
1411 /* Pseudo opcodes don't consume space */
1412 }
1413 return offset;
1414}
1415
1416/*
1417 * Walk the compilation unit and assign offsets to instructions
1418 * and literals and compute the total size of the compiled unit.
1419 * TODO: consolidate w/ Arm assembly mechanism.
1420 */
1421void X86Mir2Lir::AssignOffsets() {
1422 int offset = AssignInsnOffsets();
1423
1424 /* Const values have to be word aligned */
1425 offset = (offset + 3) & ~3;
1426
1427 /* Set up offsets for literals */
1428 data_offset_ = offset;
1429
1430 offset = AssignLiteralOffset(offset);
1431
1432 offset = AssignSwitchTablesOffset(offset);
1433
1434 offset = AssignFillArrayDataOffset(offset);
1435
1436 total_size_ = offset;
1437}
1438
1439/*
1440 * Go over each instruction in the list and calculate the offset from the top
1441 * before sending them off to the assembler. If out-of-range branch distance is
1442 * seen rearrange the instructions a bit to correct it.
1443 * TODO: consolidate w/ Arm assembly mechanism.
1444 */
1445void X86Mir2Lir::AssembleLIR() {
buzbeea61f4952013-08-23 14:27:06 -0700[diff] [blame^]1446 cu_->NewTimingSplit("Assemble");
buzbeeb48819d2013-09-14 16:15:25 -0700[diff] [blame]1447 AssignOffsets();
1448 int assembler_retries = 0;
1449 /*
1450 * Assemble here. Note that we generate code with optimistic assumptions
1451 * and if found now to work, we'll have to redo the sequence and retry.
1452 */
1453
1454 while (true) {
1455 AssemblerStatus res = AssembleInstructions(0);
1456 if (res == kSuccess) {
1457 break;
1458 } else {
1459 assembler_retries++;
1460 if (assembler_retries > MAX_ASSEMBLER_RETRIES) {
1461 CodegenDump();
1462 LOG(FATAL) << "Assembler error - too many retries";
1463 }
1464 // Redo offsets and try again
1465 AssignOffsets();
1466 code_buffer_.clear();
1467 }
1468 }
1469
buzbeea61f4952013-08-23 14:27:06 -0700[diff] [blame^]1470 cu_->NewTimingSplit("LiteralData");
buzbeeb48819d2013-09-14 16:15:25 -0700[diff] [blame]1471 // Install literals
1472 InstallLiteralPools();
1473
1474 // Install switch tables
1475 InstallSwitchTables();
1476
1477 // Install fill array data
1478 InstallFillArrayData();
1479
1480 // Create the mapping table and native offset to reference map.
buzbeea61f4952013-08-23 14:27:06 -0700[diff] [blame^]1481 cu_->NewTimingSplit("PcMappingTable");
buzbeeb48819d2013-09-14 16:15:25 -0700[diff] [blame]1482 CreateMappingTables();
1483
buzbeea61f4952013-08-23 14:27:06 -0700[diff] [blame^]1484 cu_->NewTimingSplit("GcMap");
buzbeeb48819d2013-09-14 16:15:25 -0700[diff] [blame]1485 CreateNativeGcMap();
1486}
1487
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1488} // namespace art