Blame - src/compiler/codegen/x86/Assemble.cc - platform_art

2012-03-06 22:14:17 -0800

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{ kX86 ## opname ## 16MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16MR", "[!0r+!1d],!2r" }, \

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{ kX86 ## opname ## 16AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \

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{ kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16TR", "fs:[!0d],!1r" }, \

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{ kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RR", "!0r,!1r" }, \

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{ kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \

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{ kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RT", "!0r,fs:[!1d]" }, \

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{ kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16TI", "fs:[!0d],!1d" }, \

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{ kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16RI8", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16MI8", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16TI8", "fs:[!0d],!1d" }, \

Ian Rogers

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jeffhao

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{ kX86 ## opname ## 32MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32MR", "[!0r+!1d],!2r" }, \

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{ kX86 ## opname ## 32AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \

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{ kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32TR", "fs:[!0d],!1r" }, \

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{ kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RR", "!0r,!1r" }, \

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{ kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \

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{ kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RT", "!0r,fs:[!1d]" }, \

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{ kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32TI", "fs:[!0d],!1d" }, \

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{ kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32RI8", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32MI8", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32TI8", "fs:[!0d],!1d" }

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ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */,

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0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */,

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0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */,

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0x80, 0x0 /* RegMem8/imm8 */,

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0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */),

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ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */,

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0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */,

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0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */,

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0x80, 0x1 /* RegMem8/imm8 */,

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0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */),

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ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,

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0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */,

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0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */,

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0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */,

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0x80, 0x2 /* RegMem8/imm8 */,

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0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */),

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ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,

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0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */,

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0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */,

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0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */,

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0x80, 0x3 /* RegMem8/imm8 */,

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0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */),

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ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */,

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0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */,

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0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */,

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0x80, 0x4 /* RegMem8/imm8 */,

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0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */),

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ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */,

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0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */,

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0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */,

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0x80, 0x5 /* RegMem8/imm8 */,

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0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */),

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ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */,

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0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */,

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0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */,

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0x80, 0x6 /* RegMem8/imm8 */,

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0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */),

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ENCODING_MAP(Cmp, IS_LOAD, 0, 0,

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0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */,

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0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */,

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0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */,

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0x80, 0x7 /* RegMem8/imm8 */,

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0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */),

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#undef ENCODING_MAP

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{ kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RRI", "!0r,!1r,!2d" },

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{ kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RMI", "!0r,[!1r+!2d],!3d" },

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{ kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },

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{ kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RRI", "!0r,!1r,!2d" },

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{ kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RMI", "!0r,[!1r+!2d],!3d" },

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{ kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },

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{ kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RRI8", "!0r,!1r,!2d" },

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{ kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" },

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{ kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" },

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jeffhao

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{ kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8MR", "[!0r+!1d],!2r" },

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{ kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8TR", "fs:[!0d],!1r" },

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{ kX86Mov8RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RR", "!0r,!1r" },

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{ kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RM", "!0r,[!1r+!2d]" },

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{ kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RT", "!0r,fs:[!1d]" },

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{ kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1 }, "Mov8RI", "!0r,!1d" },

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{ kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8MI", "[!0r+!1d],!2d" },

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{ kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8TI", "fs:[!0d],!1d" },

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{ kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16MR", "[!0r+!1d],!2r" },

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{ kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0 }, "Mov16TR", "fs:[!0d],!1r" },

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{ kX86Mov16RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RR", "!0r,!1r" },

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{ kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RM", "!0r,[!1r+!2d]" },

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{ kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RT", "!0r,fs:[!1d]" },

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{ kX86Mov16RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2 }, "Mov16RI", "!0r,!1d" },

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{ kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16MI", "[!0r+!1d],!2d" },

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{ kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2 }, "Mov16TI", "fs:[!0d],!1d" },

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{ kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32MR", "[!0r+!1d],!2r" },

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{ kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32TR", "fs:[!0d],!1r" },

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{ kX86Mov32RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RR", "!0r,!1r" },

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{ kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RM", "!0r,[!1r+!2d]" },

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{ kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RT", "!0r,fs:[!1d]" },

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{ kX86Mov32RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "Mov32RI", "!0r,!1d" },

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{ kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32MI", "[!0r+!1d],!2d" },

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{ kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32TI", "fs:[!0d],!1d" },

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{ kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \

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{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \

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{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \

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{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \

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{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }

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203

SHIFT_ENCODING_MAP(Rol, 0x0),

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SHIFT_ENCODING_MAP(Ror, 0x1),

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SHIFT_ENCODING_MAP(Rcl, 0x2),

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SHIFT_ENCODING_MAP(Rcr, 0x3),

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SHIFT_ENCODING_MAP(Sal, 0x4),

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SHIFT_ENCODING_MAP(Shr, 0x5),

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SHIFT_ENCODING_MAP(Sar, 0x7),

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#undef SHIFT_ENCODING_MAP

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{ kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" },

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{ kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" },

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{ kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" },

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{ kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" },

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{ kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" },

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{ kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" },

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{ kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \

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reg, reg_kind, reg_flags, \

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mem, mem_kind, mem_flags, \

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arr, arr_kind, arr_flags, imm, \

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b_flags, hw_flags, w_flags, \

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b_format, hw_format, w_format) \

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{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, #b_format "!0r" }, \

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{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, #b_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, #b_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, #hw_format "!0r" }, \

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{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, #hw_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, #hw_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, #w_format "!0r" }, \

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{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, #w_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, #w_format "[!0r+!1r<<!2d+!3d]" }

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UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

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UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

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#undef UNARY_ENCODING_MAP

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#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \

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{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

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{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

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EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),

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{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

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{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),

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{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

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{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0),

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EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0),

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{ kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" },

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{ kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" },

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EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),

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{ kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" },

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{ kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" },

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{ kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

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{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

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{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

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// TODO: load/store?

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// Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.

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{ kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },

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EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES),

300

EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES),

jeffhao

8302576

2012-08-02 11:08:56 -0700

[diff] [blame^]

301

302

{ kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" },

303

{ kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" },

304

{ kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

305

{ kX86LockCmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "!0r,!1r" },

306

{ kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" },

307

{ kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

308

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

309

EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),

310

EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),

311

EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),

312

EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

313

#undef EXT_0F_ENCODING_MAP

314

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

315

{ kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },

316

{ kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },

317

{ kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },

318

{ kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },

319

{ kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" },

320

{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

321

{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

322

{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

323

{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

324

{ kX86Ret, kNullary,NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

325

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

326

{ kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" },

327

{ kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },

328

{ kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" },

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

329

};

330

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

331

static size_t computeSize(X86EncodingMap* entry, int displacement, bool has_sib) {

332

size_t size = 0;

333

if (entry->skeleton.prefix1 > 0) {

334

++size;

335

if (entry->skeleton.prefix2 > 0) {

336

++size;

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

337

}

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

338

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

339

++size; // opcode

340

if (entry->skeleton.opcode == 0x0F) {

341

++size;

342

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

if (has_sib) {

++size;

}

if (displacement != 0) {

351

if (entry->opcode != kX86Lea32RA) {

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

352

DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0) << entry->name;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

353

}

354

size += IS_SIMM8(displacement) ? 1 : 4;

355

}

356

size += entry->skeleton.immediate_bytes;

return size;

}

int oatGetInsnSize(LIR* lir) {

361

X86EncodingMap* entry = &EncodingMap[lir->opcode];

362

switch (entry->kind) {

363

case kData:

364

return 4; // 4 bytes of data

365

case kNop:

366

return lir->operands[0]; // length of nop is sole operand

367

case kNullary:

368

return 1; // 1 byte of opcode

369

case kReg: // lir operands - 0: reg

370

return computeSize(entry, 0, false);

371

case kMem: { // lir operands - 0: base, 1: disp

372

int base = lir->operands[0];

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

373

int disp = lir->operands[1];

374

// SP requires a special extra SIB byte. BP requires explicit disp,

375

// so add a byte for disp 0 which would normally be omitted.

376

return computeSize(entry, disp, false) + ((base == rSP) || (base == rBP && disp == 0) ? 1 : 0);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

377

}

378

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

379

return computeSize(entry, lir->operands[3], true);

380

case kMemReg: { // lir operands - 0: base, 1: disp, 2: reg

381

int base = lir->operands[0];

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

382

int disp = lir->operands[1];

383

// SP requires a special extra SIB byte. BP requires explicit disp,

384

// so add a byte for disp 0 which would normally be omitted.

385

return computeSize(entry, disp, false) + ((base == rSP) || (base == rBP && disp == 0) ? 1 : 0);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

386

}

387

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

388

return computeSize(entry, lir->operands[3], true);

389

case kThreadReg: // lir operands - 0: disp, 1: reg

390

return computeSize(entry, lir->operands[0], false);

391

case kRegReg:

392

return computeSize(entry, 0, false);

jeffhao

2012-07-11 16:08:43 -0700

[diff] [blame]

393

case kRegRegStore:

394

return computeSize(entry, 0, false);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

395

case kRegMem: { // lir operands - 0: reg, 1: base, 2: disp

396

int base = lir->operands[1];

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

397

int disp = lir->operands[2];

398

// SP requires a special extra SIB byte. BP requires explicit disp,

399

// so add a byte for disp 0 which would normally be omitted.

400

return computeSize(entry, disp, false) + ((base == rSP) || (base == rBP && disp == 0) ? 1 : 0);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

401

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

402

case kRegArray: { // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

403

int base = lir->operands[1];

404

int disp = lir->operands[4];

405

// BP requires explicit disp, so add a byte for disp 0 which would normally be omitted.

406

return computeSize(entry, disp, true) + ((base == rBP && disp == 0) ? 1 : 0);

407

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

408

case kRegThread: // lir operands - 0: reg, 1: disp

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

409

return computeSize(entry, 0x12345678, false); // displacement size is always 32bit

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

410

case kRegImm: { // lir operands - 0: reg, 1: immediate

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

411

size_t size = computeSize(entry, 0, false);

412

if (entry->skeleton.ax_opcode == 0) {

413

return size;

414

} else {

415

// AX opcodes don't require the modrm byte.

416

int reg = lir->operands[0];

417

return size - (reg == rAX ? 1 : 0);

418

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

419

}

420

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

421

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

422

return computeSize(entry, lir->operands[1], false);

423

case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

424

return computeSize(entry, lir->operands[3], true);

425

case kThreadImm: // lir operands - 0: disp, 1: imm

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

426

return computeSize(entry, 0x12345678, false); // displacement size is always 32bit

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

427

case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

428

return computeSize(entry, 0, false);

429

case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

430

CHECK_NE(lir->operands[1], static_cast<int>(rSP)); // TODO: add extra SIB byte

431

return computeSize(entry, lir->operands[2], false);

432

case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

433

return computeSize(entry, lir->operands[4], true);

434

case kMovRegImm: // lir operands - 0: reg, 1: immediate

435

return 1 + entry->skeleton.immediate_bytes;

436

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

437

// Shift by immediate one has a shorter opcode.

438

return computeSize(entry, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

439

case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

440

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

441

// Shift by immediate one has a shorter opcode.

442

return computeSize(entry, lir->operands[1], false) - (lir->operands[2] == 1 ? 1 : 0);

443

case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

444

// Shift by immediate one has a shorter opcode.

445

return computeSize(entry, lir->operands[3], true) - (lir->operands[4] == 1 ? 1 : 0);

446

case kShiftRegCl:

447

return computeSize(entry, 0, false);

448

case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

449

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

450

return computeSize(entry, lir->operands[1], false);

451

case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

452

return computeSize(entry, lir->operands[3], true);

453

case kRegCond: // lir operands - 0: reg, 1: cond

454

return computeSize(entry, 0, false);

455

case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

456

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

457

return computeSize(entry, lir->operands[1], false);

458

case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

459

return computeSize(entry, lir->operands[3], true);

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

460

case kJcc:

461

if (lir->opcode == kX86Jcc8) {

462

return 2; // opcode + rel8

463

} else {

464

DCHECK(lir->opcode == kX86Jcc32);

465

return 6; // 2 byte opcode + rel32

466

}

467

case kJmp:

468

if (lir->opcode == kX86Jmp8) {

469

return 2; // opcode + rel8

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

470

} else if (lir->opcode == kX86Jmp32) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

471

return 5; // opcode + rel32

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

472

} else {

473

DCHECK(lir->opcode == kX86JmpR);

474

return 2; // opcode + modrm

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

475

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

476

case kCall:

Elliott Hughes

b25c3f6

2012-03-26 16:35:06 -0700

[diff] [blame]

477

switch (lir->opcode) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

478

case kX86CallR: return 2; // opcode modrm

479

case kX86CallM: // lir operands - 0: base, 1: disp

480

return computeSize(entry, lir->operands[1], false);

481

case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

482

return computeSize(entry, lir->operands[3], true);

Ian Rogers

6cbb2bd

2012-03-16 13:45:30 -0700

[diff] [blame]

483

case kX86CallT: // lir operands - 0: disp

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

484

return computeSize(entry, 0x12345678, false); // displacement size is always 32bit

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

default:

break;

}

break;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

489

case kPcRel:

490

if (entry->opcode == kX86PcRelLoadRA) {

491

// lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

492

return computeSize(entry, 0x12345678, true);

493

} else {

494

DCHECK(entry->opcode == kX86PcRelAdr);

495

return 5; // opcode with reg + 4 byte immediate

496

}

497

case kMacro:

498

DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));

499

return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +

500

computeSize(&EncodingMap[kX86Sub32RI], 0, false) -

501

(lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

506

return 0;

507

}

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

508

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

509

static uint8_t modrmForDisp(int base, int disp) {

510

// BP requires an explicit disp, so do not omit it in the 0 case

511

if (disp == 0 && base != rBP) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

512

return 0;

513

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

520

static void emitDisp(CompilationUnit* cUnit, int base, int disp) {

521

// BP requires an explicit disp, so do not omit it in the 0 case

522

if (disp == 0 && base != rBP) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

523

return;

524

} else if (IS_SIMM8(disp)) {

525

cUnit->codeBuffer.push_back(disp & 0xFF);

526

} else {

527

cUnit->codeBuffer.push_back(disp & 0xFF);

528

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

529

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

530

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

}

}

static void emitOpReg(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg) {

535

if (entry->skeleton.prefix1 != 0) {

536

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

537

if (entry->skeleton.prefix2 != 0) {

538

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

539

}

540

} else {

541

DCHECK_EQ(0, entry->skeleton.prefix2);

542

}

543

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

544

if (entry->skeleton.opcode == 0x0F) {

545

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

546

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

547

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

548

} else {

549

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

550

}

551

} else {

552

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

553

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

554

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

555

if (FPREG(reg)) {

556

reg = reg & FP_REG_MASK;

557

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

558

if (reg >= 4) {

559

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg

560

<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);

561

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

562

DCHECK_LT(reg, 8);

563

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

564

cUnit->codeBuffer.push_back(modrm);

565

DCHECK_EQ(0, entry->skeleton.ax_opcode);

566

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

567

}

568

569

static void emitOpMem(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t base, int disp) {

570

if (entry->skeleton.prefix1 != 0) {

571

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

572

if (entry->skeleton.prefix2 != 0) {

573

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

574

}

575

} else {

576

DCHECK_EQ(0, entry->skeleton.prefix2);

577

}

578

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

579

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

580

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

581

DCHECK_LT(entry->skeleton.modrm_opcode, 8);

582

DCHECK_LT(base, 8);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

583

uint8_t modrm = (modrmForDisp(base, disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

584

cUnit->codeBuffer.push_back(modrm);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

585

emitDisp(cUnit, base, disp);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

586

DCHECK_EQ(0, entry->skeleton.ax_opcode);

587

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

588

}

589

590

static void emitMemReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

591

uint8_t base, int disp, uint8_t reg) {

592

if (entry->skeleton.prefix1 != 0) {

593

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

594

if (entry->skeleton.prefix2 != 0) {

595

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

596

}

597

} else {

598

DCHECK_EQ(0, entry->skeleton.prefix2);

599

}

600

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

601

if (entry->skeleton.opcode == 0x0F) {

602

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

603

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

604

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

605

} else {

606

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

607

}

608

} else {

609

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

610

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

611

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

612

if (FPREG(reg)) {

613

reg = reg & FP_REG_MASK;

614

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

615

if (reg >= 4) {

616

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg

617

<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);

618

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

619

DCHECK_LT(reg, 8);

620

DCHECK_LT(base, 8);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

621

uint8_t modrm = (modrmForDisp(base, disp) << 6) | (reg << 3) | base;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

622

cUnit->codeBuffer.push_back(modrm);

623

if (base == rSP) {

624

// Special SIB for SP base

625

cUnit->codeBuffer.push_back(0 << 6 | (rSP << 3) | rSP);

626

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

627

emitDisp(cUnit, base, disp);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

628

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

629

DCHECK_EQ(0, entry->skeleton.ax_opcode);

630

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

631

}

632

633

static void emitRegMem(CompilationUnit* cUnit, const X86EncodingMap* entry,

634

uint8_t reg, uint8_t base, int disp) {

635

// Opcode will flip operands.

636

emitMemReg(cUnit, entry, base, disp, reg);

637

}

638

639

static void emitRegArray(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg,

640

uint8_t base, uint8_t index, int scale, int disp) {

641

if (entry->skeleton.prefix1 != 0) {

642

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

643

if (entry->skeleton.prefix2 != 0) {

644

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

645

}

646

} else {

647

DCHECK_EQ(0, entry->skeleton.prefix2);

648

}

649

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

650

if (entry->skeleton.opcode == 0x0F) {

651

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

652

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

653

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

654

} else {

655

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

656

}

657

} else {

658

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

659

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

660

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

661

if (FPREG(reg)) {

662

reg = reg & FP_REG_MASK;

663

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

664

DCHECK_LT(reg, 8);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

665

uint8_t modrm = (modrmForDisp(base, disp) << 6) | (reg << 3) | rSP;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

666

cUnit->codeBuffer.push_back(modrm);

DCHECK_LT(scale, 4);

DCHECK_LT(index, 8);

DCHECK_LT(base, 8);

uint8_t sib = (scale << 6) | (index << 3) | base;

671

cUnit->codeBuffer.push_back(sib);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

672

emitDisp(cUnit, base, disp);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

673

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

674

DCHECK_EQ(0, entry->skeleton.ax_opcode);

675

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

676

}

677

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

678

static void emitArrayReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

679

uint8_t base, uint8_t index, int scale, int disp, uint8_t reg) {

680

// Opcode will flip operands.

681

emitRegArray(cUnit, entry, reg, base, index, scale, disp);

682

}

683

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

684

static void emitRegThread(CompilationUnit* cUnit, const X86EncodingMap* entry,

685

uint8_t reg, int disp) {

686

DCHECK_NE(entry->skeleton.prefix1, 0);

687

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

688

if (entry->skeleton.prefix2 != 0) {

689

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

690

}

691

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

692

if (entry->skeleton.opcode == 0x0F) {

693

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

694

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

695

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

696

} else {

697

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

698

}

699

} else {

700

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

701

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

702

}

703

if (FPREG(reg)) {

704

reg = reg & FP_REG_MASK;

705

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

706

if (reg >= 4) {

707

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg

708

<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);

709

}

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

710

DCHECK_LT(reg, 8);

711

uint8_t modrm = (0 << 6) | (reg << 3) | rBP;

712

cUnit->codeBuffer.push_back(modrm);

713

cUnit->codeBuffer.push_back(disp & 0xFF);

714

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

715

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

716

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

717

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

718

DCHECK_EQ(0, entry->skeleton.ax_opcode);

719

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

720

}

721

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

722

static void emitRegReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

723

uint8_t reg1, uint8_t reg2) {

724

if (entry->skeleton.prefix1 != 0) {

725

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

726

if (entry->skeleton.prefix2 != 0) {

727

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

728

}

729

} else {

730

DCHECK_EQ(0, entry->skeleton.prefix2);

731

}

732

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

733

if (entry->skeleton.opcode == 0x0F) {

734

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

735

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

736

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

737

} else {

738

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

739

}

740

} else {

741

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

742

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

743

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

744

if (FPREG(reg1)) {

745

reg1 = reg1 & FP_REG_MASK;

746

}

747

if (FPREG(reg2)) {

748

reg2 = reg2 & FP_REG_MASK;

749

}

750

DCHECK_LT(reg1, 8);

751

DCHECK_LT(reg2, 8);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

752

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

753

cUnit->codeBuffer.push_back(modrm);

754

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

755

DCHECK_EQ(0, entry->skeleton.ax_opcode);

756

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

757

}

758

Elliott Hughes

225ae52

2012-04-16 20:21:45 -0700

[diff] [blame]

759

static void emitRegRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

760

uint8_t reg1, uint8_t reg2, int32_t imm) {

761

if (entry->skeleton.prefix1 != 0) {

762

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

763

if (entry->skeleton.prefix2 != 0) {

764

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

765

}

766

} else {

767

DCHECK_EQ(0, entry->skeleton.prefix2);

768

}

769

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

770

if (entry->skeleton.opcode == 0x0F) {

771

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

772

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

773

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

774

} else {

775

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

776

}

777

} else {

778

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

779

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

780

}

781

if (FPREG(reg1)) {

782

reg1 = reg1 & FP_REG_MASK;

783

}

784

if (FPREG(reg2)) {

785

reg2 = reg2 & FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

790

cUnit->codeBuffer.push_back(modrm);

791

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

792

DCHECK_EQ(0, entry->skeleton.ax_opcode);

793

switch (entry->skeleton.immediate_bytes) {

794

case 1:

795

DCHECK(IS_SIMM8(imm));

796

cUnit->codeBuffer.push_back(imm & 0xFF);

797

break;

798

case 2:

799

DCHECK(IS_SIMM16(imm));

800

cUnit->codeBuffer.push_back(imm & 0xFF);

801

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

802

break;

803

case 4:

804

cUnit->codeBuffer.push_back(imm & 0xFF);

805

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

806

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

807

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

808

break;

809

default:

810

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

811

<< ") for instruction: " << entry->name;

break;

}

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

816

static void emitRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

817

uint8_t reg, int imm) {

818

if (entry->skeleton.prefix1 != 0) {

819

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

820

if (entry->skeleton.prefix2 != 0) {

821

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

822

}

823

} else {

824

DCHECK_EQ(0, entry->skeleton.prefix2);

825

}

826

if (reg == rAX && entry->skeleton.ax_opcode != 0) {

827

cUnit->codeBuffer.push_back(entry->skeleton.ax_opcode);

828

} else {

829

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

830

if (entry->skeleton.opcode == 0x0F) {

831

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

832

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

833

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

834

} else {

835

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

836

}

837

} else {

838

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

839

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

840

}

jeffhao

2012-07-11 16:08:43 -0700

[diff] [blame]

841

if (FPREG(reg)) {

842

reg = reg & FP_REG_MASK;

843

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

844

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

845

cUnit->codeBuffer.push_back(modrm);

846

}

847

switch (entry->skeleton.immediate_bytes) {

848

case 1:

849

DCHECK(IS_SIMM8(imm));

850

cUnit->codeBuffer.push_back(imm & 0xFF);

851

break;

852

case 2:

853

DCHECK(IS_SIMM16(imm));

854

cUnit->codeBuffer.push_back(imm & 0xFF);

855

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

856

break;

857

case 4:

858

cUnit->codeBuffer.push_back(imm & 0xFF);

859

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

860

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

861

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

862

break;

863

default:

864

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

865

<< ") for instruction: " << entry->name;

break;

}

}

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

870

static void emitThreadImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

871

int disp, int imm) {

872

if (entry->skeleton.prefix1 != 0) {

873

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

874

if (entry->skeleton.prefix2 != 0) {

875

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

876

}

877

} else {

878

DCHECK_EQ(0, entry->skeleton.prefix2);

879

}

880

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

881

if (entry->skeleton.opcode == 0x0F) {

882

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

883

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

884

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

885

} else {

886

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

887

}

888

} else {

889

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

890

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

891

}

892

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

893

cUnit->codeBuffer.push_back(modrm);

894

cUnit->codeBuffer.push_back(disp & 0xFF);

895

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

896

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

897

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

898

switch (entry->skeleton.immediate_bytes) {

899

case 1:

900

DCHECK(IS_SIMM8(imm));

901

cUnit->codeBuffer.push_back(imm & 0xFF);

902

break;

903

case 2:

904

DCHECK(IS_SIMM16(imm));

905

cUnit->codeBuffer.push_back(imm & 0xFF);

906

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

907

break;

908

case 4:

909

cUnit->codeBuffer.push_back(imm & 0xFF);

910

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

911

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

912

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

913

break;

914

default:

915

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

916

<< ") for instruction: " << entry->name;

917

break;

918

}

919

DCHECK_EQ(entry->skeleton.ax_opcode, 0);

920

}

921

922

static void emitMovRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

923

uint8_t reg, int imm) {

924

DCHECK_LT(reg, 8);

925

cUnit->codeBuffer.push_back(0xB8 + reg);

926

cUnit->codeBuffer.push_back(imm & 0xFF);

927

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

928

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

929

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

930

}

931

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

932

static void emitShiftRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

933

uint8_t reg, int imm) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

934

if (entry->skeleton.prefix1 != 0) {

935

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

936

if (entry->skeleton.prefix2 != 0) {

937

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

938

}

939

} else {

940

DCHECK_EQ(0, entry->skeleton.prefix2);

941

}

942

if (imm != 1) {

943

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

944

} else {

945

// Shorter encoding for 1 bit shift

946

cUnit->codeBuffer.push_back(entry->skeleton.ax_opcode);

947

}

948

if (entry->skeleton.opcode == 0x0F) {

949

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

950

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

951

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

952

} else {

953

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

954

}

955

} else {

956

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

957

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

958

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

959

if (reg >= 4) {

960

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg

961

<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);

962

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

963

DCHECK_LT(reg, 8);

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

964

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

965

cUnit->codeBuffer.push_back(modrm);

966

if (imm != 1) {

967

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

968

DCHECK(IS_SIMM8(imm));

969

cUnit->codeBuffer.push_back(imm & 0xFF);

}

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

973

static void emitShiftRegCl(CompilationUnit* cUnit, const X86EncodingMap* entry,

974

uint8_t reg, uint8_t cl) {

975

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

976

if (entry->skeleton.prefix1 != 0) {

977

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

978

if (entry->skeleton.prefix2 != 0) {

979

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

980

}

981

} else {

982

DCHECK_EQ(0, entry->skeleton.prefix2);

983

}

984

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

985

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

986

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

987

DCHECK_LT(reg, 8);

988

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

989

cUnit->codeBuffer.push_back(modrm);

990

DCHECK_EQ(0, entry->skeleton.ax_opcode);

991

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

992

}

993

994

static void emitRegCond(CompilationUnit* cUnit, const X86EncodingMap* entry,

995

uint8_t reg, uint8_t condition) {

996

if (entry->skeleton.prefix1 != 0) {

997

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

998

if (entry->skeleton.prefix2 != 0) {

999

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1000

}

1001

} else {

1002

DCHECK_EQ(0, entry->skeleton.prefix2);

1003

}

1004

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1005

DCHECK_EQ(0x0F, entry->skeleton.opcode);

1006

cUnit->codeBuffer.push_back(0x0F);

1007

DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);

1008

cUnit->codeBuffer.push_back(0x90 | condition);

1009

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1010

DCHECK_LT(reg, 8);

1011

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

1012

cUnit->codeBuffer.push_back(modrm);

1013

DCHECK_EQ(entry->skeleton.immediate_bytes, 0);

1014

}

1015

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1016

static void emitJmp(CompilationUnit* cUnit, const X86EncodingMap* entry, int rel) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1017

if (entry->opcode == kX86Jmp8) {

1018

DCHECK(IS_SIMM8(rel));

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1019

cUnit->codeBuffer.push_back(0xEB);

1020

cUnit->codeBuffer.push_back(rel & 0xFF);

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1021

} else if (entry->opcode == kX86Jmp32) {

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1022

cUnit->codeBuffer.push_back(0xE9);

1023

cUnit->codeBuffer.push_back(rel & 0xFF);

1024

cUnit->codeBuffer.push_back((rel >> 8) & 0xFF);

1025

cUnit->codeBuffer.push_back((rel >> 16) & 0xFF);

1026

cUnit->codeBuffer.push_back((rel >> 24) & 0xFF);

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1027

} else {

1028

DCHECK(entry->opcode == kX86JmpR);

1029

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1030

uint8_t reg = static_cast<uint8_t>(rel);

1031

DCHECK_LT(reg, 8);

1032

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

1033

cUnit->codeBuffer.push_back(modrm);

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

}

}

static void emitJcc(CompilationUnit* cUnit, const X86EncodingMap* entry,

1038

int rel, uint8_t cc) {

1039

DCHECK_LT(cc, 16);

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1040

if (entry->opcode == kX86Jcc8) {

1041

DCHECK(IS_SIMM8(rel));

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1042

cUnit->codeBuffer.push_back(0x70 | cc);

1043

cUnit->codeBuffer.push_back(rel & 0xFF);

1044

} else {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1045

DCHECK(entry->opcode == kX86Jcc32);

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1046

cUnit->codeBuffer.push_back(0x0F);

1047

cUnit->codeBuffer.push_back(0x80 | cc);

1048

cUnit->codeBuffer.push_back(rel & 0xFF);

1049

cUnit->codeBuffer.push_back((rel >> 8) & 0xFF);

1050

cUnit->codeBuffer.push_back((rel >> 16) & 0xFF);

1051

cUnit->codeBuffer.push_back((rel >> 24) & 0xFF);

}

}

static void emitCallMem(CompilationUnit* cUnit, const X86EncodingMap* entry,

1056

uint8_t base, int disp) {

1057

if (entry->skeleton.prefix1 != 0) {

1058

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

1059

if (entry->skeleton.prefix2 != 0) {

1060

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1061

}

1062

} else {

1063

DCHECK_EQ(0, entry->skeleton.prefix2);

1064

}

1065

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1066

if (entry->skeleton.opcode == 0x0F) {

1067

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

1068

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

1069

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

1070

} else {

1071

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1072

}

1073

} else {

1074

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1075

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1076

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

1077

uint8_t modrm = (modrmForDisp(base, disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1078

cUnit->codeBuffer.push_back(modrm);

1079

if (base == rSP) {

1080

// Special SIB for SP base

1081

cUnit->codeBuffer.push_back(0 << 6 | (rSP << 3) | rSP);

1082

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

1083

emitDisp(cUnit, base, disp);

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1084

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1085

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1086

}

1087

1088

static void emitCallThread(CompilationUnit* cUnit, const X86EncodingMap* entry, int disp) {

1089

DCHECK_NE(entry->skeleton.prefix1, 0);

1090

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

1091

if (entry->skeleton.prefix2 != 0) {

1092

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1093

}

1094

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1095

if (entry->skeleton.opcode == 0x0F) {

1096

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

1097

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

1098

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

1099

} else {

1100

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1101

}

1102

} else {

1103

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1104

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1105

}

1106

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

1107

cUnit->codeBuffer.push_back(modrm);

1108

cUnit->codeBuffer.push_back(disp & 0xFF);

1109

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

1110

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

1111

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

1112

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1113

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1114

}

1115

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1116

static void emitPcRel(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg,

1117

int base_or_table, uint8_t index, int scale, int table_or_disp) {

1118

int disp;

1119

if (entry->opcode == kX86PcRelLoadRA) {

1120

SwitchTable *tabRec = (SwitchTable*)table_or_disp;

1121

disp = tabRec->offset;

1122

} else {

1123

DCHECK(entry->opcode == kX86PcRelAdr);

1124

FillArrayData *tabRec = (FillArrayData *)base_or_table;

1125

disp = tabRec->offset;

1126

}

1127

if (entry->skeleton.prefix1 != 0) {

1128

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

1129

if (entry->skeleton.prefix2 != 0) {

1130

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1131

}

1132

} else {

1133

DCHECK_EQ(0, entry->skeleton.prefix2);

1134

}

1135

if (FPREG(reg)) {

1136

reg = reg & FP_REG_MASK;

1137

}

1138

DCHECK_LT(reg, 8);

1139

if (entry->opcode == kX86PcRelLoadRA) {

1140

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1141

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1142

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1143

uint8_t modrm = (2 << 6) | (reg << 3) | rSP;

1144

cUnit->codeBuffer.push_back(modrm);

1145

DCHECK_LT(scale, 4);

1146

DCHECK_LT(index, 8);

1147

DCHECK_LT(base_or_table, 8);

1148

uint8_t base = static_cast<uint8_t>(base_or_table);

1149

uint8_t sib = (scale << 6) | (index << 3) | base;

1150

cUnit->codeBuffer.push_back(sib);

1151

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1152

} else {

1153

cUnit->codeBuffer.push_back(entry->skeleton.opcode + reg);

1154

}

1155

cUnit->codeBuffer.push_back(disp & 0xFF);

1156

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

1157

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

1158

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

1159

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1160

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1161

}

1162

1163

static void emitMacro(CompilationUnit* cUnit, const X86EncodingMap* entry,

1164

uint8_t reg, int offset) {

1165

DCHECK(entry->opcode == kX86StartOfMethod) << entry->name;

1166

cUnit->codeBuffer.push_back(0xE8); // call +0

1167

cUnit->codeBuffer.push_back(0);

1168

cUnit->codeBuffer.push_back(0);

1169

cUnit->codeBuffer.push_back(0);

1170

cUnit->codeBuffer.push_back(0);

1171

1172

DCHECK_LT(reg, 8);

1173

cUnit->codeBuffer.push_back(0x58 + reg); // pop reg

1174

1175

emitRegImm(cUnit, &EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */);

1176

}

1177

Ian Rogers

6cbb2bd

2012-03-16 13:45:30 -0700

[diff] [blame]

1178

void emitUnimplemented(CompilationUnit* cUnit, const X86EncodingMap* entry, LIR* lir) {

Elliott Hughes

225ae52

2012-04-16 20:21:45 -0700

[diff] [blame]

1179

UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " " << buildInsnString(entry->fmt, lir, 0);

Ian Rogers

141b0c7

2012-03-15 18:18:52 -0700

[diff] [blame]

1180

for (int i = 0; i < oatGetInsnSize(lir); ++i) {

1181

cUnit->codeBuffer.push_back(0xCC); // push breakpoint instruction - int 3

}

}

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1185

/*

1186

* Assemble the LIR into binary instruction format. Note that we may

1187

* discover that pc-relative displacements may not fit the selected

1188

* instruction. In those cases we will try to substitute a new code

1189

* sequence or request that the trace be shortened and retried.

1190

*/

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1191

AssemblerStatus oatAssembleInstructions(CompilationUnit *cUnit, intptr_t startAddr) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1192

LIR *lir;

1193

AssemblerStatus res = kSuccess; // Assume success

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1194

Ian Rogers

141d622

2012-04-05 12:23:06 -0700

[diff] [blame]

1195

const bool kVerbosePcFixup = false;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1196

for (lir = (LIR *) cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {

1197

if (lir->opcode < 0) {

1198

continue;

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1199

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1200

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1201

if (lir->flags.isNop) {

continue;

}

if (lir->flags.pcRelFixup) {

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1206

switch (lir->opcode) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1207

case kX86Jcc8: {

1208

LIR *targetLIR = lir->target;

1209

DCHECK(targetLIR != NULL);

1210

int delta = 0;

1211

intptr_t pc;

1212

if (IS_SIMM8(lir->operands[0])) {

1213

pc = lir->offset + 2 /* opcode + rel8 */;

1214

} else {

1215

pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1216

}

1217

intptr_t target = targetLIR->offset;

1218

delta = target - pc;

1219

if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1220

if (kVerbosePcFixup) {

1221

LOG(INFO) << "Retry for JCC growth at " << lir->offset

1222

<< " delta: " << delta << " old delta: " << lir->operands[0];

1223

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1224

lir->opcode = kX86Jcc32;

1225

oatSetupResourceMasks(lir);

1226

res = kRetryAll;

1227

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1228

if (kVerbosePcFixup) {

1229

LOG(INFO) << "Source:";

1230

oatDumpLIRInsn(cUnit, lir, 0);

1231

LOG(INFO) << "Target:";

1232

oatDumpLIRInsn(cUnit, targetLIR, 0);

1233

LOG(INFO) << "Delta " << delta;

1234

}

1235

lir->operands[0] = delta;

break;

}

case kX86Jcc32: {

LIR *targetLIR = lir->target;

1240

DCHECK(targetLIR != NULL);

1241

intptr_t pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1242

intptr_t target = targetLIR->offset;

1243

int delta = target - pc;

1244

if (kVerbosePcFixup) {

1245

LOG(INFO) << "Source:";

1246

oatDumpLIRInsn(cUnit, lir, 0);

1247

LOG(INFO) << "Target:";

1248

oatDumpLIRInsn(cUnit, targetLIR, 0);

1249

LOG(INFO) << "Delta " << delta;

1250

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1251

lir->operands[0] = delta;

1252

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1253

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1254

case kX86Jmp8: {

1255

LIR *targetLIR = lir->target;

1256

DCHECK(targetLIR != NULL);

1257

int delta = 0;

1258

intptr_t pc;

1259

if (IS_SIMM8(lir->operands[0])) {

1260

pc = lir->offset + 2 /* opcode + rel8 */;

1261

} else {

1262

pc = lir->offset + 5 /* opcode + rel32 */;

1263

}

1264

intptr_t target = targetLIR->offset;

1265

delta = target - pc;

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

1266

if (!(cUnit->disableOpt & (1 << kSafeOptimizations)) && delta == 0) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1267

// Useless branch

1268

lir->flags.isNop = true;

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1269

if (kVerbosePcFixup) {

1270

LOG(INFO) << "Retry for useless branch at " << lir->offset;

1271

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1272

res = kRetryAll;

1273

} else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1274

if (kVerbosePcFixup) {

1275

LOG(INFO) << "Retry for JMP growth at " << lir->offset;

1276

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1277

lir->opcode = kX86Jmp32;

1278

oatSetupResourceMasks(lir);

1279

res = kRetryAll;

1280

}

1281

lir->operands[0] = delta;

1282

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1283

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1284

case kX86Jmp32: {

1285

LIR *targetLIR = lir->target;

1286

DCHECK(targetLIR != NULL);

1287

intptr_t pc = lir->offset + 5 /* opcode + rel32 */;

1288

intptr_t target = targetLIR->offset;

1289

int delta = target - pc;

1290

lir->operands[0] = delta;

1291

break;

1292

}

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1293

default:

1294

break;

1295

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

}

/*

* If one of the pc-relative instructions expanded we'll have

1300

* to make another pass. Don't bother to fully assemble the

1301

* instruction.

1302

*/

1303

if (res != kSuccess) {

1304

continue;

1305

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1306

CHECK_EQ(static_cast<size_t>(lir->offset), cUnit->codeBuffer.size());

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1307

const X86EncodingMap *entry = &EncodingMap[lir->opcode];

Ian Rogers

141b0c7

2012-03-15 18:18:52 -0700

[diff] [blame]

1308

size_t starting_cbuf_size = cUnit->codeBuffer.size();

Elliott Hughes

b25c3f6

2012-03-26 16:35:06 -0700

[diff] [blame]

1309

switch (entry->kind) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1310

case kData: // 4 bytes of data

1311

cUnit->codeBuffer.push_back(lir->operands[0]);

1312

break;

1313

case kNullary: // 1 byte of opcode

1314

DCHECK_EQ(0, entry->skeleton.prefix1);

1315

DCHECK_EQ(0, entry->skeleton.prefix2);

1316

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1317

if (entry->skeleton.extra_opcode1 != 0) {

1318

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

1319

if (entry->skeleton.extra_opcode2 != 0) {

1320

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

1321

}

1322

} else {

1323

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1324

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1325

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1326

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1327

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1328

break;

1329

case kReg: // lir operands - 0: reg

1330

emitOpReg(cUnit, entry, lir->operands[0]);

1331

break;

1332

case kMem: // lir operands - 0: base, 1: disp

1333

emitOpMem(cUnit, entry, lir->operands[0], lir->operands[1]);

1334

break;

1335

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

1336

emitMemReg(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1337

break;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1338

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

1339

emitArrayReg(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

1340

lir->operands[3], lir->operands[4]);

1341

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1342

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

1343

emitRegMem(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1344

break;

1345

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

1346

emitRegArray(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

1347

lir->operands[3], lir->operands[4]);

1348

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1349

case kRegThread: // lir operands - 0: reg, 1: disp

1350

emitRegThread(cUnit, entry, lir->operands[0], lir->operands[1]);

1351

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1352

case kRegReg: // lir operands - 0: reg1, 1: reg2

1353

emitRegReg(cUnit, entry, lir->operands[0], lir->operands[1]);

1354

break;

jeffhao

2012-07-11 16:08:43 -0700

[diff] [blame]

1355

case kRegRegStore: // lir operands - 0: reg2, 1: reg1

1356

emitRegReg(cUnit, entry, lir->operands[1], lir->operands[0]);

1357

break;

Elliott Hughes

225ae52

2012-04-16 20:21:45 -0700

[diff] [blame]

1358

case kRegRegImm:

1359

emitRegRegImm(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1360

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1361

case kRegImm: // lir operands - 0: reg, 1: immediate

1362

emitRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1363

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1364

case kThreadImm: // lir operands - 0: disp, 1: immediate

1365

emitThreadImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1366

break;

1367

case kMovRegImm: // lir operands - 0: reg, 1: immediate

1368

emitMovRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1369

break;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1370

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

1371

emitShiftRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1372

break;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1373

case kShiftRegCl: // lir operands - 0: reg, 1: cl

1374

emitShiftRegCl(cUnit, entry, lir->operands[0], lir->operands[1]);

1375

break;

1376

case kRegCond: // lir operands - 0: reg, 1: condition

1377

emitRegCond(cUnit, entry, lir->operands[0], lir->operands[1]);

1378

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1379

case kJmp: // lir operands - 0: rel

1380

emitJmp(cUnit, entry, lir->operands[0]);

1381

break;

1382

case kJcc: // lir operands - 0: rel, 1: CC, target assigned

1383

emitJcc(cUnit, entry, lir->operands[0], lir->operands[1]);

1384

break;

1385

case kCall:

Elliott Hughes

b25c3f6

2012-03-26 16:35:06 -0700

[diff] [blame]

1386

switch (entry->opcode) {

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1387

case kX86CallM: // lir operands - 0: base, 1: disp

1388

emitCallMem(cUnit, entry, lir->operands[0], lir->operands[1]);

1389

break;

1390

case kX86CallT: // lir operands - 0: disp

1391

emitCallThread(cUnit, entry, lir->operands[0]);

1392

break;

1393

default:

1394

emitUnimplemented(cUnit, entry, lir);

1395

break;

1396

}

1397

break;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1398

case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

1399

emitPcRel(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

1400

lir->operands[3], lir->operands[4]);

1401

break;

1402

case kMacro:

1403

emitMacro(cUnit, entry, lir->operands[0], lir->offset);

1404

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1405

default:

Ian Rogers

6cbb2bd

2012-03-16 13:45:30 -0700

[diff] [blame]

1406

emitUnimplemented(cUnit, entry, lir);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1407

break;

1408

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1409

CHECK_EQ(static_cast<size_t>(oatGetInsnSize(lir)),

1410

cUnit->codeBuffer.size() - starting_cbuf_size)

1411

<< "Instruction size mismatch for entry: " << EncodingMap[lir->opcode].name;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1412

}

1413

return res;

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1414

}

1415

buzbee