Blame - src/compiler/codegen/x86/Assemble.cc - platform_art

2012-03-06 22:14:17 -0800

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{ kX86 ## opname ## 16MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16MR", "[!0r+!1d],!2r" }, \

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{ kX86 ## opname ## 16AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \

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{ kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16TR", "fs:[!0d],!1r" }, \

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{ kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RR", "!0r,!1r" }, \

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{ kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \

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{ kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RT", "!0r,fs:[!1d]" }, \

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{ kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16TI", "fs:[!0d],!1d" }, \

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{ kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16RI8", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16MI8", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16TI8", "fs:[!0d],!1d" }, \

Ian Rogers

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jeffhao

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{ kX86 ## opname ## 32MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32MR", "[!0r+!1d],!2r" }, \

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{ kX86 ## opname ## 32AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \

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{ kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32TR", "fs:[!0d],!1r" }, \

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{ kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RR", "!0r,!1r" }, \

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{ kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \

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{ kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RT", "!0r,fs:[!1d]" }, \

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{ kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32TI", "fs:[!0d],!1d" }, \

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{ kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32RI8", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32MI8", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32TI8", "fs:[!0d],!1d" }

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ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */,

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0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */,

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0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */,

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0x80, 0x0 /* RegMem8/imm8 */,

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0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */),

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ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */,

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0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */,

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0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */,

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0x80, 0x1 /* RegMem8/imm8 */,

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0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */),

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ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,

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0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */,

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0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */,

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0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */,

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0x80, 0x2 /* RegMem8/imm8 */,

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0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */),

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ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,

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0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */,

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0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */,

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0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */,

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0x80, 0x3 /* RegMem8/imm8 */,

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0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */),

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ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */,

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0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */,

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0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */,

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0x80, 0x4 /* RegMem8/imm8 */,

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0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */),

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ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */,

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0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */,

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0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */,

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0x80, 0x5 /* RegMem8/imm8 */,

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0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */),

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ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */,

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0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */,

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0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */,

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0x80, 0x6 /* RegMem8/imm8 */,

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0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */),

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ENCODING_MAP(Cmp, IS_LOAD, 0, 0,

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0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */,

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0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */,

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0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */,

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0x80, 0x7 /* RegMem8/imm8 */,

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0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */),

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#undef ENCODING_MAP

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{ kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RRI", "!0r,!1r,!2d" },

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{ kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RMI", "!0r,[!1r+!2d],!3d" },

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{ kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },

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{ kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RRI", "!0r,!1r,!2d" },

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{ kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RMI", "!0r,[!1r+!2d],!3d" },

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{ kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },

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{ kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RRI8", "!0r,!1r,!2d" },

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{ kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" },

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{ kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" },

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jeffhao

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{ kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8MR", "[!0r+!1d],!2r" },

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{ kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8TR", "fs:[!0d],!1r" },

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{ kX86Mov8RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RR", "!0r,!1r" },

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{ kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RM", "!0r,[!1r+!2d]" },

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{ kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RT", "!0r,fs:[!1d]" },

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{ kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1 }, "Mov8RI", "!0r,!1d" },

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{ kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8MI", "[!0r+!1d],!2d" },

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{ kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8TI", "fs:[!0d],!1d" },

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{ kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16MR", "[!0r+!1d],!2r" },

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{ kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0 }, "Mov16TR", "fs:[!0d],!1r" },

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{ kX86Mov16RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RR", "!0r,!1r" },

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{ kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RM", "!0r,[!1r+!2d]" },

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{ kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RT", "!0r,fs:[!1d]" },

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{ kX86Mov16RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2 }, "Mov16RI", "!0r,!1d" },

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{ kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16MI", "[!0r+!1d],!2d" },

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{ kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2 }, "Mov16TI", "fs:[!0d],!1d" },

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{ kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32MR", "[!0r+!1d],!2r" },

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{ kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32TR", "fs:[!0d],!1r" },

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{ kX86Mov32RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RR", "!0r,!1r" },

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{ kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RM", "!0r,[!1r+!2d]" },

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{ kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RT", "!0r,fs:[!1d]" },

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{ kX86Mov32RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "Mov32RI", "!0r,!1d" },

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{ kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32MI", "[!0r+!1d],!2d" },

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{ kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32TI", "fs:[!0d],!1d" },

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{ kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \

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{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \

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{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \

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{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \

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{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }

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203

SHIFT_ENCODING_MAP(Rol, 0x0),

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SHIFT_ENCODING_MAP(Ror, 0x1),

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SHIFT_ENCODING_MAP(Rcl, 0x2),

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SHIFT_ENCODING_MAP(Rcr, 0x3),

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SHIFT_ENCODING_MAP(Sal, 0x4),

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SHIFT_ENCODING_MAP(Shr, 0x5),

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SHIFT_ENCODING_MAP(Sar, 0x7),

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#undef SHIFT_ENCODING_MAP

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{ kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" },

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{ kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" },

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{ kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" },

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{ kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" },

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{ kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" },

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{ kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" },

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{ kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \

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reg, reg_kind, reg_flags, \

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mem, mem_kind, mem_flags, \

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arr, arr_kind, arr_flags, imm, \

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b_flags, hw_flags, w_flags, \

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b_format, hw_format, w_format) \

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{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, #b_format "!0r" }, \

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{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, #b_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, #b_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, #hw_format "!0r" }, \

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{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, #hw_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, #hw_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, #w_format "!0r" }, \

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{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, #w_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, #w_format "[!0r+!1r<<!2d+!3d]" }

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UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

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UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

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#undef UNARY_ENCODING_MAP

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#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \

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{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

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{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

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EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),

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{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

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{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),

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{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

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{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0),

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EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0),

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{ kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" },

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{ kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" },

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EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),

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{ kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" },

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{ kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" },

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{ kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

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{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

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{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

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// TODO: load/store?

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// Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.

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{ kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },

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EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES),

300

EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES),

301

EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),

302

EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),

303

EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),

304

EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

305

#undef EXT_0F_ENCODING_MAP

306

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

307

{ kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },

308

{ kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },

309

{ kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },

310

{ kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },

311

{ kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" },

312

{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

313

{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

314

{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

315

{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

316

{ kX86Ret, kNullary,NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

317

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

318

{ kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" },

319

{ kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },

320

{ kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" },

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

321

};

322

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

323

static size_t computeSize(X86EncodingMap* entry, int displacement, bool has_sib) {

324

size_t size = 0;

325

if (entry->skeleton.prefix1 > 0) {

326

++size;

327

if (entry->skeleton.prefix2 > 0) {

328

++size;

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

329

}

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

330

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

331

++size; // opcode

332

if (entry->skeleton.opcode == 0x0F) {

333

++size;

334

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

if (has_sib) {

++size;

}

if (displacement != 0) {

343

if (entry->opcode != kX86Lea32RA) {

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

344

DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0) << entry->name;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

345

}

346

size += IS_SIMM8(displacement) ? 1 : 4;

347

}

348

size += entry->skeleton.immediate_bytes;

return size;

}

int oatGetInsnSize(LIR* lir) {

353

X86EncodingMap* entry = &EncodingMap[lir->opcode];

354

switch (entry->kind) {

355

case kData:

356

return 4; // 4 bytes of data

357

case kNop:

358

return lir->operands[0]; // length of nop is sole operand

359

case kNullary:

360

return 1; // 1 byte of opcode

361

case kReg: // lir operands - 0: reg

362

return computeSize(entry, 0, false);

363

case kMem: { // lir operands - 0: base, 1: disp

364

int base = lir->operands[0];

365

// SP requires a special extra SIB byte

366

return computeSize(entry, lir->operands[1], false) + (base == rSP ? 1 : 0);

367

}

368

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

369

return computeSize(entry, lir->operands[3], true);

370

case kMemReg: { // lir operands - 0: base, 1: disp, 2: reg

371

int base = lir->operands[0];

372

// SP requires a special extra SIB byte

373

return computeSize(entry, lir->operands[1], false) + (base == rSP ? 1 : 0);

374

}

375

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

376

return computeSize(entry, lir->operands[3], true);

377

case kThreadReg: // lir operands - 0: disp, 1: reg

378

return computeSize(entry, lir->operands[0], false);

379

case kRegReg:

380

return computeSize(entry, 0, false);

jeffhao

2012-07-11 16:08:43 -0700

[diff] [blame]

381

case kRegRegStore:

382

return computeSize(entry, 0, false);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

383

case kRegMem: { // lir operands - 0: reg, 1: base, 2: disp

384

int base = lir->operands[1];

385

return computeSize(entry, lir->operands[2], false) + (base == rSP ? 1 : 0);

386

}

387

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

388

return computeSize(entry, lir->operands[4], true);

389

case kRegThread: // lir operands - 0: reg, 1: disp

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

390

return computeSize(entry, 0x12345678, false); // displacement size is always 32bit

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

391

case kRegImm: { // lir operands - 0: reg, 1: immediate

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

392

size_t size = computeSize(entry, 0, false);

393

if (entry->skeleton.ax_opcode == 0) {

394

return size;

395

} else {

396

// AX opcodes don't require the modrm byte.

397

int reg = lir->operands[0];

398

return size - (reg == rAX ? 1 : 0);

399

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

400

}

401

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

402

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

403

return computeSize(entry, lir->operands[1], false);

404

case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

405

return computeSize(entry, lir->operands[3], true);

406

case kThreadImm: // lir operands - 0: disp, 1: imm

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

407

return computeSize(entry, 0x12345678, false); // displacement size is always 32bit

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

408

case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

409

return computeSize(entry, 0, false);

410

case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

411

CHECK_NE(lir->operands[1], static_cast<int>(rSP)); // TODO: add extra SIB byte

412

return computeSize(entry, lir->operands[2], false);

413

case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

414

return computeSize(entry, lir->operands[4], true);

415

case kMovRegImm: // lir operands - 0: reg, 1: immediate

416

return 1 + entry->skeleton.immediate_bytes;

417

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

418

// Shift by immediate one has a shorter opcode.

419

return computeSize(entry, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

420

case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

421

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

422

// Shift by immediate one has a shorter opcode.

423

return computeSize(entry, lir->operands[1], false) - (lir->operands[2] == 1 ? 1 : 0);

424

case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

425

// Shift by immediate one has a shorter opcode.

426

return computeSize(entry, lir->operands[3], true) - (lir->operands[4] == 1 ? 1 : 0);

427

case kShiftRegCl:

428

return computeSize(entry, 0, false);

429

case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

430

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

431

return computeSize(entry, lir->operands[1], false);

432

case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

433

return computeSize(entry, lir->operands[3], true);

434

case kRegCond: // lir operands - 0: reg, 1: cond

435

return computeSize(entry, 0, false);

436

case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

437

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

438

return computeSize(entry, lir->operands[1], false);

439

case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

440

return computeSize(entry, lir->operands[3], true);

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

441

case kJcc:

442

if (lir->opcode == kX86Jcc8) {

443

return 2; // opcode + rel8

444

} else {

445

DCHECK(lir->opcode == kX86Jcc32);

446

return 6; // 2 byte opcode + rel32

447

}

448

case kJmp:

449

if (lir->opcode == kX86Jmp8) {

450

return 2; // opcode + rel8

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

451

} else if (lir->opcode == kX86Jmp32) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

452

return 5; // opcode + rel32

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

453

} else {

454

DCHECK(lir->opcode == kX86JmpR);

455

return 2; // opcode + modrm

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

456

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

457

case kCall:

Elliott Hughes

b25c3f6

2012-03-26 16:35:06 -0700

[diff] [blame]

458

switch (lir->opcode) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

459

case kX86CallR: return 2; // opcode modrm

460

case kX86CallM: // lir operands - 0: base, 1: disp

461

return computeSize(entry, lir->operands[1], false);

462

case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

463

return computeSize(entry, lir->operands[3], true);

Ian Rogers

6cbb2bd

2012-03-16 13:45:30 -0700

[diff] [blame]

464

case kX86CallT: // lir operands - 0: disp

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

465

return computeSize(entry, 0x12345678, false); // displacement size is always 32bit

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

default:

break;

}

break;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

470

case kPcRel:

471

if (entry->opcode == kX86PcRelLoadRA) {

472

// lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

473

return computeSize(entry, 0x12345678, true);

474

} else {

475

DCHECK(entry->opcode == kX86PcRelAdr);

476

return 5; // opcode with reg + 4 byte immediate

477

}

478

case kMacro:

479

DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));

480

return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +

481

computeSize(&EncodingMap[kX86Sub32RI], 0, false) -

482

(lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

487

return 0;

488

}

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

489

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

490

static uint8_t modrmForDisp(int disp) {

491

if (disp == 0) {

492

return 0;

493

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

static void emitDisp(CompilationUnit* cUnit, int disp) {

501

if (disp == 0) {

502

return;

503

} else if (IS_SIMM8(disp)) {

504

cUnit->codeBuffer.push_back(disp & 0xFF);

505

} else {

506

cUnit->codeBuffer.push_back(disp & 0xFF);

507

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

508

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

509

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

}

}

static void emitOpReg(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg) {

514

if (entry->skeleton.prefix1 != 0) {

515

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

516

if (entry->skeleton.prefix2 != 0) {

517

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

518

}

519

} else {

520

DCHECK_EQ(0, entry->skeleton.prefix2);

521

}

522

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

523

if (entry->skeleton.opcode == 0x0F) {

524

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

525

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

526

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

527

} else {

528

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

529

}

530

} else {

531

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

532

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

533

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

534

if (FPREG(reg)) {

535

reg = reg & FP_REG_MASK;

536

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

537

DCHECK_LT(reg, 8);

538

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

539

cUnit->codeBuffer.push_back(modrm);

540

DCHECK_EQ(0, entry->skeleton.ax_opcode);

541

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

542

}

543

544

static void emitOpMem(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t base, int disp) {

545

if (entry->skeleton.prefix1 != 0) {

546

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

547

if (entry->skeleton.prefix2 != 0) {

548

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

549

}

550

} else {

551

DCHECK_EQ(0, entry->skeleton.prefix2);

552

}

553

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

554

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

555

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

556

DCHECK_LT(entry->skeleton.modrm_opcode, 8);

557

DCHECK_LT(base, 8);

558

uint8_t modrm = (modrmForDisp(disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;

559

cUnit->codeBuffer.push_back(modrm);

560

emitDisp(cUnit, disp);

561

DCHECK_EQ(0, entry->skeleton.ax_opcode);

562

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

563

}

564

565

static void emitMemReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

566

uint8_t base, int disp, uint8_t reg) {

567

if (entry->skeleton.prefix1 != 0) {

568

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

569

if (entry->skeleton.prefix2 != 0) {

570

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

571

}

572

} else {

573

DCHECK_EQ(0, entry->skeleton.prefix2);

574

}

575

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

576

if (entry->skeleton.opcode == 0x0F) {

577

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

578

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

579

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

580

} else {

581

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

582

}

583

} else {

584

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

585

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

586

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

587

if (FPREG(reg)) {

588

reg = reg & FP_REG_MASK;

589

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

590

DCHECK_LT(reg, 8);

591

DCHECK_LT(base, 8);

592

uint8_t modrm = (modrmForDisp(disp) << 6) | (reg << 3) | base;

593

cUnit->codeBuffer.push_back(modrm);

594

if (base == rSP) {

595

// Special SIB for SP base

596

cUnit->codeBuffer.push_back(0 << 6 | (rSP << 3) | rSP);

597

}

598

emitDisp(cUnit, disp);

599

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

600

DCHECK_EQ(0, entry->skeleton.ax_opcode);

601

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

602

}

603

604

static void emitRegMem(CompilationUnit* cUnit, const X86EncodingMap* entry,

605

uint8_t reg, uint8_t base, int disp) {

606

// Opcode will flip operands.

607

emitMemReg(cUnit, entry, base, disp, reg);

608

}

609

610

static void emitRegArray(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg,

611

uint8_t base, uint8_t index, int scale, int disp) {

612

if (entry->skeleton.prefix1 != 0) {

613

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

614

if (entry->skeleton.prefix2 != 0) {

615

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

616

}

617

} else {

618

DCHECK_EQ(0, entry->skeleton.prefix2);

619

}

620

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

621

if (entry->skeleton.opcode == 0x0F) {

622

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

623

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

624

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

625

} else {

626

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

627

}

628

} else {

629

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

630

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

631

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

632

if (FPREG(reg)) {

633

reg = reg & FP_REG_MASK;

634

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

635

DCHECK_LT(reg, 8);

636

uint8_t modrm = (modrmForDisp(disp) << 6) | (reg << 3) | rSP;

637

cUnit->codeBuffer.push_back(modrm);

DCHECK_LT(scale, 4);

DCHECK_LT(index, 8);

DCHECK_LT(base, 8);

uint8_t sib = (scale << 6) | (index << 3) | base;

642

cUnit->codeBuffer.push_back(sib);

643

emitDisp(cUnit, disp);

644

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

645

DCHECK_EQ(0, entry->skeleton.ax_opcode);

646

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

647

}

648

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

649

static void emitArrayReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

650

uint8_t base, uint8_t index, int scale, int disp, uint8_t reg) {

651

// Opcode will flip operands.

652

emitRegArray(cUnit, entry, reg, base, index, scale, disp);

653

}

654

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

655

static void emitRegThread(CompilationUnit* cUnit, const X86EncodingMap* entry,

656

uint8_t reg, int disp) {

657

DCHECK_NE(entry->skeleton.prefix1, 0);

658

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

659

if (entry->skeleton.prefix2 != 0) {

660

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

661

}

662

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

663

if (entry->skeleton.opcode == 0x0F) {

664

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

665

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

666

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

667

} else {

668

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

669

}

670

} else {

671

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

672

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

673

}

674

if (FPREG(reg)) {

675

reg = reg & FP_REG_MASK;

676

}

677

DCHECK_LT(reg, 8);

678

uint8_t modrm = (0 << 6) | (reg << 3) | rBP;

679

cUnit->codeBuffer.push_back(modrm);

680

cUnit->codeBuffer.push_back(disp & 0xFF);

681

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

682

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

683

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

684

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

685

DCHECK_EQ(0, entry->skeleton.ax_opcode);

686

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

687

}

688

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

689

static void emitRegReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

690

uint8_t reg1, uint8_t reg2) {

691

if (entry->skeleton.prefix1 != 0) {

692

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

693

if (entry->skeleton.prefix2 != 0) {

694

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

695

}

696

} else {

697

DCHECK_EQ(0, entry->skeleton.prefix2);

698

}

699

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

700

if (entry->skeleton.opcode == 0x0F) {

701

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

702

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

703

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

704

} else {

705

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

706

}

707

} else {

708

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

709

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

710

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

711

if (FPREG(reg1)) {

712

reg1 = reg1 & FP_REG_MASK;

713

}

714

if (FPREG(reg2)) {

715

reg2 = reg2 & FP_REG_MASK;

716

}

717

DCHECK_LT(reg1, 8);

718

DCHECK_LT(reg2, 8);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

719

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

720

cUnit->codeBuffer.push_back(modrm);

721

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

722

DCHECK_EQ(0, entry->skeleton.ax_opcode);

723

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

724

}

725

Elliott Hughes

225ae52

2012-04-16 20:21:45 -0700

[diff] [blame]

726

static void emitRegRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

727

uint8_t reg1, uint8_t reg2, int32_t imm) {

728

if (entry->skeleton.prefix1 != 0) {

729

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

730

if (entry->skeleton.prefix2 != 0) {

731

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

732

}

733

} else {

734

DCHECK_EQ(0, entry->skeleton.prefix2);

735

}

736

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

737

if (entry->skeleton.opcode == 0x0F) {

738

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

739

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

740

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

741

} else {

742

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

743

}

744

} else {

745

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

746

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

747

}

748

if (FPREG(reg1)) {

749

reg1 = reg1 & FP_REG_MASK;

750

}

751

if (FPREG(reg2)) {

752

reg2 = reg2 & FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

757

cUnit->codeBuffer.push_back(modrm);

758

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

759

DCHECK_EQ(0, entry->skeleton.ax_opcode);

760

switch (entry->skeleton.immediate_bytes) {

761

case 1:

762

DCHECK(IS_SIMM8(imm));

763

cUnit->codeBuffer.push_back(imm & 0xFF);

764

break;

765

case 2:

766

DCHECK(IS_SIMM16(imm));

767

cUnit->codeBuffer.push_back(imm & 0xFF);

768

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

769

break;

770

case 4:

771

cUnit->codeBuffer.push_back(imm & 0xFF);

772

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

773

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

774

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

775

break;

776

default:

777

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

778

<< ") for instruction: " << entry->name;

break;

}

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

783

static void emitRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

784

uint8_t reg, int imm) {

785

if (entry->skeleton.prefix1 != 0) {

786

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

787

if (entry->skeleton.prefix2 != 0) {

788

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

789

}

790

} else {

791

DCHECK_EQ(0, entry->skeleton.prefix2);

792

}

793

if (reg == rAX && entry->skeleton.ax_opcode != 0) {

794

cUnit->codeBuffer.push_back(entry->skeleton.ax_opcode);

795

} else {

796

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

797

if (entry->skeleton.opcode == 0x0F) {

798

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

799

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

800

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

801

} else {

802

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

803

}

804

} else {

805

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

806

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

807

}

jeffhao

2012-07-11 16:08:43 -0700

[diff] [blame]

808

if (FPREG(reg)) {

809

reg = reg & FP_REG_MASK;

810

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

811

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

812

cUnit->codeBuffer.push_back(modrm);

813

}

814

switch (entry->skeleton.immediate_bytes) {

815

case 1:

816

DCHECK(IS_SIMM8(imm));

817

cUnit->codeBuffer.push_back(imm & 0xFF);

818

break;

819

case 2:

820

DCHECK(IS_SIMM16(imm));

821

cUnit->codeBuffer.push_back(imm & 0xFF);

822

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

823

break;

824

case 4:

825

cUnit->codeBuffer.push_back(imm & 0xFF);

826

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

827

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

828

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

829

break;

830

default:

831

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

832

<< ") for instruction: " << entry->name;

break;

}

}

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

837

static void emitThreadImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

838

int disp, int imm) {

839

if (entry->skeleton.prefix1 != 0) {

840

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

841

if (entry->skeleton.prefix2 != 0) {

842

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

843

}

844

} else {

845

DCHECK_EQ(0, entry->skeleton.prefix2);

846

}

847

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

848

if (entry->skeleton.opcode == 0x0F) {

849

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

850

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

851

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

852

} else {

853

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

854

}

855

} else {

856

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

857

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

858

}

859

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

860

cUnit->codeBuffer.push_back(modrm);

861

cUnit->codeBuffer.push_back(disp & 0xFF);

862

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

863

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

864

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

865

switch (entry->skeleton.immediate_bytes) {

866

case 1:

867

DCHECK(IS_SIMM8(imm));

868

cUnit->codeBuffer.push_back(imm & 0xFF);

869

break;

870

case 2:

871

DCHECK(IS_SIMM16(imm));

872

cUnit->codeBuffer.push_back(imm & 0xFF);

873

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

874

break;

875

case 4:

876

cUnit->codeBuffer.push_back(imm & 0xFF);

877

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

878

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

879

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

880

break;

881

default:

882

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

883

<< ") for instruction: " << entry->name;

884

break;

885

}

886

DCHECK_EQ(entry->skeleton.ax_opcode, 0);

887

}

888

889

static void emitMovRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

890

uint8_t reg, int imm) {

891

DCHECK_LT(reg, 8);

892

cUnit->codeBuffer.push_back(0xB8 + reg);

893

cUnit->codeBuffer.push_back(imm & 0xFF);

894

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

895

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

896

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

897

}

898

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

899

static void emitShiftRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

900

uint8_t reg, int imm) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

901

if (entry->skeleton.prefix1 != 0) {

902

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

903

if (entry->skeleton.prefix2 != 0) {

904

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

905

}

906

} else {

907

DCHECK_EQ(0, entry->skeleton.prefix2);

908

}

909

if (imm != 1) {

910

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

911

} else {

912

// Shorter encoding for 1 bit shift

913

cUnit->codeBuffer.push_back(entry->skeleton.ax_opcode);

914

}

915

if (entry->skeleton.opcode == 0x0F) {

916

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

917

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

918

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

919

} else {

920

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

921

}

922

} else {

923

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

924

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

925

}

926

DCHECK_LT(reg, 8);

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

927

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

928

cUnit->codeBuffer.push_back(modrm);

929

if (imm != 1) {

930

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

931

DCHECK(IS_SIMM8(imm));

932

cUnit->codeBuffer.push_back(imm & 0xFF);

}

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

936

static void emitShiftRegCl(CompilationUnit* cUnit, const X86EncodingMap* entry,

937

uint8_t reg, uint8_t cl) {

938

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

939

if (entry->skeleton.prefix1 != 0) {

940

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

941

if (entry->skeleton.prefix2 != 0) {

942

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

943

}

944

} else {

945

DCHECK_EQ(0, entry->skeleton.prefix2);

946

}

947

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

948

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

949

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

950

DCHECK_LT(reg, 8);

951

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

952

cUnit->codeBuffer.push_back(modrm);

953

DCHECK_EQ(0, entry->skeleton.ax_opcode);

954

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

955

}

956

957

static void emitRegCond(CompilationUnit* cUnit, const X86EncodingMap* entry,

958

uint8_t reg, uint8_t condition) {

959

if (entry->skeleton.prefix1 != 0) {

960

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

961

if (entry->skeleton.prefix2 != 0) {

962

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

963

}

964

} else {

965

DCHECK_EQ(0, entry->skeleton.prefix2);

966

}

967

DCHECK_EQ(0, entry->skeleton.ax_opcode);

968

DCHECK_EQ(0x0F, entry->skeleton.opcode);

969

cUnit->codeBuffer.push_back(0x0F);

970

DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);

971

cUnit->codeBuffer.push_back(0x90 | condition);

972

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

973

DCHECK_LT(reg, 8);

974

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

975

cUnit->codeBuffer.push_back(modrm);

976

DCHECK_EQ(entry->skeleton.immediate_bytes, 0);

977

}

978

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

979

static void emitJmp(CompilationUnit* cUnit, const X86EncodingMap* entry, int rel) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

980

if (entry->opcode == kX86Jmp8) {

981

DCHECK(IS_SIMM8(rel));

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

982

cUnit->codeBuffer.push_back(0xEB);

983

cUnit->codeBuffer.push_back(rel & 0xFF);

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

984

} else if (entry->opcode == kX86Jmp32) {

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

985

cUnit->codeBuffer.push_back(0xE9);

986

cUnit->codeBuffer.push_back(rel & 0xFF);

987

cUnit->codeBuffer.push_back((rel >> 8) & 0xFF);

988

cUnit->codeBuffer.push_back((rel >> 16) & 0xFF);

989

cUnit->codeBuffer.push_back((rel >> 24) & 0xFF);

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

990

} else {

991

DCHECK(entry->opcode == kX86JmpR);

992

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

993

uint8_t reg = static_cast<uint8_t>(rel);

994

DCHECK_LT(reg, 8);

995

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

996

cUnit->codeBuffer.push_back(modrm);

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

}

}

static void emitJcc(CompilationUnit* cUnit, const X86EncodingMap* entry,

1001

int rel, uint8_t cc) {

1002

DCHECK_LT(cc, 16);

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1003

if (entry->opcode == kX86Jcc8) {

1004

DCHECK(IS_SIMM8(rel));

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1005

cUnit->codeBuffer.push_back(0x70 | cc);

1006

cUnit->codeBuffer.push_back(rel & 0xFF);

1007

} else {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1008

DCHECK(entry->opcode == kX86Jcc32);

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1009

cUnit->codeBuffer.push_back(0x0F);

1010

cUnit->codeBuffer.push_back(0x80 | cc);

1011

cUnit->codeBuffer.push_back(rel & 0xFF);

1012

cUnit->codeBuffer.push_back((rel >> 8) & 0xFF);

1013

cUnit->codeBuffer.push_back((rel >> 16) & 0xFF);

1014

cUnit->codeBuffer.push_back((rel >> 24) & 0xFF);

}

}

static void emitCallMem(CompilationUnit* cUnit, const X86EncodingMap* entry,

1019

uint8_t base, int disp) {

1020

if (entry->skeleton.prefix1 != 0) {

1021

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

1022

if (entry->skeleton.prefix2 != 0) {

1023

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1024

}

1025

} else {

1026

DCHECK_EQ(0, entry->skeleton.prefix2);

1027

}

1028

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1029

if (entry->skeleton.opcode == 0x0F) {

1030

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

1031

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

1032

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

1033

} else {

1034

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1035

}

1036

} else {

1037

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1038

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1039

}

1040

uint8_t modrm = (modrmForDisp(disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;

1041

cUnit->codeBuffer.push_back(modrm);

1042

if (base == rSP) {

1043

// Special SIB for SP base

1044

cUnit->codeBuffer.push_back(0 << 6 | (rSP << 3) | rSP);

1045

}

1046

emitDisp(cUnit, disp);

1047

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1048

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1049

}

1050

1051

static void emitCallThread(CompilationUnit* cUnit, const X86EncodingMap* entry, int disp) {

1052

DCHECK_NE(entry->skeleton.prefix1, 0);

1053

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

1054

if (entry->skeleton.prefix2 != 0) {

1055

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1056

}

1057

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1058

if (entry->skeleton.opcode == 0x0F) {

1059

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

1060

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

1061

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

1062

} else {

1063

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1064

}

1065

} else {

1066

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1067

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1068

}

1069

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

1070

cUnit->codeBuffer.push_back(modrm);

1071

cUnit->codeBuffer.push_back(disp & 0xFF);

1072

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

1073

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

1074

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

1075

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1076

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1077

}

1078

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1079

static void emitPcRel(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg,

1080

int base_or_table, uint8_t index, int scale, int table_or_disp) {

1081

int disp;

1082

if (entry->opcode == kX86PcRelLoadRA) {

1083

SwitchTable *tabRec = (SwitchTable*)table_or_disp;

1084

disp = tabRec->offset;

1085

} else {

1086

DCHECK(entry->opcode == kX86PcRelAdr);

1087

FillArrayData *tabRec = (FillArrayData *)base_or_table;

1088

disp = tabRec->offset;

1089

}

1090

if (entry->skeleton.prefix1 != 0) {

1091

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

1092

if (entry->skeleton.prefix2 != 0) {

1093

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1094

}

1095

} else {

1096

DCHECK_EQ(0, entry->skeleton.prefix2);

1097

}

1098

if (FPREG(reg)) {

1099

reg = reg & FP_REG_MASK;

1100

}

1101

DCHECK_LT(reg, 8);

1102

if (entry->opcode == kX86PcRelLoadRA) {

1103

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1104

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1105

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1106

uint8_t modrm = (2 << 6) | (reg << 3) | rSP;

1107

cUnit->codeBuffer.push_back(modrm);

1108

DCHECK_LT(scale, 4);

1109

DCHECK_LT(index, 8);

1110

DCHECK_LT(base_or_table, 8);

1111

uint8_t base = static_cast<uint8_t>(base_or_table);

1112

uint8_t sib = (scale << 6) | (index << 3) | base;

1113

cUnit->codeBuffer.push_back(sib);

1114

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1115

} else {

1116

cUnit->codeBuffer.push_back(entry->skeleton.opcode + reg);

1117

}

1118

cUnit->codeBuffer.push_back(disp & 0xFF);

1119

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

1120

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

1121

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

1122

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1123

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1124

}

1125

1126

static void emitMacro(CompilationUnit* cUnit, const X86EncodingMap* entry,

1127

uint8_t reg, int offset) {

1128

DCHECK(entry->opcode == kX86StartOfMethod) << entry->name;

1129

cUnit->codeBuffer.push_back(0xE8); // call +0

1130

cUnit->codeBuffer.push_back(0);

1131

cUnit->codeBuffer.push_back(0);

1132

cUnit->codeBuffer.push_back(0);

1133

cUnit->codeBuffer.push_back(0);

1134

1135

DCHECK_LT(reg, 8);

1136

cUnit->codeBuffer.push_back(0x58 + reg); // pop reg

1137

1138

emitRegImm(cUnit, &EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */);

1139

}

1140

Ian Rogers

6cbb2bd

2012-03-16 13:45:30 -0700

[diff] [blame]

1141

void emitUnimplemented(CompilationUnit* cUnit, const X86EncodingMap* entry, LIR* lir) {

Elliott Hughes

225ae52

2012-04-16 20:21:45 -0700

[diff] [blame]

1142

UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " " << buildInsnString(entry->fmt, lir, 0);

Ian Rogers

141b0c7

2012-03-15 18:18:52 -0700

[diff] [blame]

1143

for (int i = 0; i < oatGetInsnSize(lir); ++i) {

1144

cUnit->codeBuffer.push_back(0xCC); // push breakpoint instruction - int 3

}

}

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1148

/*

1149

* Assemble the LIR into binary instruction format. Note that we may

1150

* discover that pc-relative displacements may not fit the selected

1151

* instruction. In those cases we will try to substitute a new code

1152

* sequence or request that the trace be shortened and retried.

1153

*/

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1154

AssemblerStatus oatAssembleInstructions(CompilationUnit *cUnit, intptr_t startAddr) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1155

LIR *lir;

1156

AssemblerStatus res = kSuccess; // Assume success

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1157

Ian Rogers

141d622

2012-04-05 12:23:06 -0700

[diff] [blame]

1158

const bool kVerbosePcFixup = false;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1159

for (lir = (LIR *) cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {

1160

if (lir->opcode < 0) {

1161

continue;

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1162

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1163

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1164

if (lir->flags.isNop) {

continue;

}

if (lir->flags.pcRelFixup) {

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1169

switch (lir->opcode) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1170

case kX86Jcc8: {

1171

LIR *targetLIR = lir->target;

1172

DCHECK(targetLIR != NULL);

1173

int delta = 0;

1174

intptr_t pc;

1175

if (IS_SIMM8(lir->operands[0])) {

1176

pc = lir->offset + 2 /* opcode + rel8 */;

1177

} else {

1178

pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1179

}

1180

intptr_t target = targetLIR->offset;

1181

delta = target - pc;

1182

if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1183

if (kVerbosePcFixup) {

1184

LOG(INFO) << "Retry for JCC growth at " << lir->offset

1185

<< " delta: " << delta << " old delta: " << lir->operands[0];

1186

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1187

lir->opcode = kX86Jcc32;

1188

oatSetupResourceMasks(lir);

1189

res = kRetryAll;

1190

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1191

if (kVerbosePcFixup) {

1192

LOG(INFO) << "Source:";

1193

oatDumpLIRInsn(cUnit, lir, 0);

1194

LOG(INFO) << "Target:";

1195

oatDumpLIRInsn(cUnit, targetLIR, 0);

1196

LOG(INFO) << "Delta " << delta;

1197

}

1198

lir->operands[0] = delta;

break;

}

case kX86Jcc32: {

LIR *targetLIR = lir->target;

1203

DCHECK(targetLIR != NULL);

1204

intptr_t pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1205

intptr_t target = targetLIR->offset;

1206

int delta = target - pc;

1207

if (kVerbosePcFixup) {

1208

LOG(INFO) << "Source:";

1209

oatDumpLIRInsn(cUnit, lir, 0);

1210

LOG(INFO) << "Target:";

1211

oatDumpLIRInsn(cUnit, targetLIR, 0);

1212

LOG(INFO) << "Delta " << delta;

1213

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1214

lir->operands[0] = delta;

1215

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1216

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1217

case kX86Jmp8: {

1218

LIR *targetLIR = lir->target;

1219

DCHECK(targetLIR != NULL);

1220

int delta = 0;

1221

intptr_t pc;

1222

if (IS_SIMM8(lir->operands[0])) {

1223

pc = lir->offset + 2 /* opcode + rel8 */;

1224

} else {

1225

pc = lir->offset + 5 /* opcode + rel32 */;

1226

}

1227

intptr_t target = targetLIR->offset;

1228

delta = target - pc;

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

1229

if (!(cUnit->disableOpt & (1 << kSafeOptimizations)) && delta == 0) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1230

// Useless branch

1231

lir->flags.isNop = true;

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1232

if (kVerbosePcFixup) {

1233

LOG(INFO) << "Retry for useless branch at " << lir->offset;

1234

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1235

res = kRetryAll;

1236

} else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1237

if (kVerbosePcFixup) {

1238

LOG(INFO) << "Retry for JMP growth at " << lir->offset;

1239

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1240

lir->opcode = kX86Jmp32;

1241

oatSetupResourceMasks(lir);

1242

res = kRetryAll;

1243

}

1244

lir->operands[0] = delta;

1245

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1246

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1247

case kX86Jmp32: {

1248

LIR *targetLIR = lir->target;

1249

DCHECK(targetLIR != NULL);

1250

intptr_t pc = lir->offset + 5 /* opcode + rel32 */;

1251

intptr_t target = targetLIR->offset;

1252

int delta = target - pc;

1253

lir->operands[0] = delta;

1254

break;

1255

}

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1256

default:

1257

break;

1258

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

}

/*

* If one of the pc-relative instructions expanded we'll have

1263

* to make another pass. Don't bother to fully assemble the

1264

* instruction.

1265

*/

1266

if (res != kSuccess) {

1267

continue;

1268

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1269

CHECK_EQ(static_cast<size_t>(lir->offset), cUnit->codeBuffer.size());

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1270

const X86EncodingMap *entry = &EncodingMap[lir->opcode];

Ian Rogers

141b0c7

2012-03-15 18:18:52 -0700

[diff] [blame]

1271

size_t starting_cbuf_size = cUnit->codeBuffer.size();

Elliott Hughes

b25c3f6

2012-03-26 16:35:06 -0700

[diff] [blame]

1272

switch (entry->kind) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1273

case kData: // 4 bytes of data

1274

cUnit->codeBuffer.push_back(lir->operands[0]);

1275

break;

1276

case kNullary: // 1 byte of opcode

1277

DCHECK_EQ(0, entry->skeleton.prefix1);

1278

DCHECK_EQ(0, entry->skeleton.prefix2);

1279

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1280

if (entry->skeleton.extra_opcode1 != 0) {

1281

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

1282

if (entry->skeleton.extra_opcode2 != 0) {

1283

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

1284

}

1285

} else {

1286

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1287

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1288

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1289

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1290

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1291

break;

1292

case kReg: // lir operands - 0: reg

1293

emitOpReg(cUnit, entry, lir->operands[0]);

1294

break;

1295

case kMem: // lir operands - 0: base, 1: disp

1296

emitOpMem(cUnit, entry, lir->operands[0], lir->operands[1]);

1297

break;

1298

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

1299

emitMemReg(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1300

break;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1301

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

1302

emitArrayReg(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

1303

lir->operands[3], lir->operands[4]);

1304

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1305

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

1306

emitRegMem(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1307

break;

1308

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

1309

emitRegArray(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

1310

lir->operands[3], lir->operands[4]);

1311

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1312

case kRegThread: // lir operands - 0: reg, 1: disp

1313

emitRegThread(cUnit, entry, lir->operands[0], lir->operands[1]);

1314

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1315

case kRegReg: // lir operands - 0: reg1, 1: reg2

1316

emitRegReg(cUnit, entry, lir->operands[0], lir->operands[1]);

1317

break;

jeffhao

2012-07-11 16:08:43 -0700

[diff] [blame]

1318

case kRegRegStore: // lir operands - 0: reg2, 1: reg1

1319

emitRegReg(cUnit, entry, lir->operands[1], lir->operands[0]);

1320

break;

Elliott Hughes

225ae52

2012-04-16 20:21:45 -0700

[diff] [blame]

1321

case kRegRegImm:

1322

emitRegRegImm(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1323

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1324

case kRegImm: // lir operands - 0: reg, 1: immediate

1325

emitRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1326

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1327

case kThreadImm: // lir operands - 0: disp, 1: immediate

1328

emitThreadImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1329

break;

1330

case kMovRegImm: // lir operands - 0: reg, 1: immediate

1331

emitMovRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1332

break;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1333

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

1334

emitShiftRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1335

break;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1336

case kShiftRegCl: // lir operands - 0: reg, 1: cl

1337

emitShiftRegCl(cUnit, entry, lir->operands[0], lir->operands[1]);

1338

break;

1339

case kRegCond: // lir operands - 0: reg, 1: condition

1340

emitRegCond(cUnit, entry, lir->operands[0], lir->operands[1]);

1341

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1342

case kJmp: // lir operands - 0: rel

1343

emitJmp(cUnit, entry, lir->operands[0]);

1344

break;

1345

case kJcc: // lir operands - 0: rel, 1: CC, target assigned

1346

emitJcc(cUnit, entry, lir->operands[0], lir->operands[1]);

1347

break;

1348

case kCall:

Elliott Hughes

b25c3f6

2012-03-26 16:35:06 -0700

[diff] [blame]

1349

switch (entry->opcode) {

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1350

case kX86CallM: // lir operands - 0: base, 1: disp

1351

emitCallMem(cUnit, entry, lir->operands[0], lir->operands[1]);

1352

break;

1353

case kX86CallT: // lir operands - 0: disp

1354

emitCallThread(cUnit, entry, lir->operands[0]);

1355

break;

1356

default:

1357

emitUnimplemented(cUnit, entry, lir);

1358

break;

1359

}

1360

break;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1361

case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

1362

emitPcRel(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

1363

lir->operands[3], lir->operands[4]);

1364

break;

1365

case kMacro:

1366

emitMacro(cUnit, entry, lir->operands[0], lir->offset);

1367

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1368

default:

Ian Rogers

6cbb2bd

2012-03-16 13:45:30 -0700

[diff] [blame]

1369

emitUnimplemented(cUnit, entry, lir);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1370

break;

1371

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1372

CHECK_EQ(static_cast<size_t>(oatGetInsnSize(lir)),

1373

cUnit->codeBuffer.size() - starting_cbuf_size)

1374

<< "Instruction size mismatch for entry: " << EncodingMap[lir->opcode].name;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1375

}

1376

return res;

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1377

}

1378

buzbee