Blame - compiler/dex/quick/x86/assemble_x86.cc - platform_art

2013-07-12 13:46:57 -0700

[diff] [blame]

253

#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \

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{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

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{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

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EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),

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{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

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{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),

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{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

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{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0),

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EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0),

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{ kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" },

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{ kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" },

Mark Mendell

bff1ef0

2013-12-13 13:47:34 -0800

[diff] [blame]

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{ kX86SqrtsdRR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0xF2, 0, 0x0F, 0x51, 0, 0, 0, 0 }, "SqrtsdRR", "!0r,!1r" },

Vladimir Marko

12f9628

2013-12-16 14:44:03 +0000

[diff] [blame^]

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{ kX86FstpdM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0 }, "FstpdM", "[!0r,!1d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),

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{ kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" },

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{ kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" },

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{ kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

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{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

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{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

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// TODO: load/store?

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// Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.

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{ kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },

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EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES),

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EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES),

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{ kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" },

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{ kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" },

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{ kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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{ kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" },

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{ kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Vladimir Marko

70b797d

2013-12-03 15:25:24 +0000

[diff] [blame]

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{ kX86LockCmpxchg8bM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1d]" },

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{ kX86LockCmpxchg8bA, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),

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EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),

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EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),

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EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),

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#undef EXT_0F_ENCODING_MAP

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{ kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },

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{ kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },

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{ kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },

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{ kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },

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{ kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" },

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{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

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{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

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{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

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{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

Brian Carlstrom

b1eba21

2013-07-17 18:07:19 -0700

[diff] [blame]

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{ kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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{ kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" },

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{ kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },

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{ kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" },

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};

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static size_t ComputeSize(const X86EncodingMap* entry, int base, int displacement, bool has_sib) {

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size_t size = 0;

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if (entry->skeleton.prefix1 > 0) {

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++size;

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if (entry->skeleton.prefix2 > 0) {

++size;

}

}

++size; // opcode

if (entry->skeleton.opcode == 0x0F) {

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++size;

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if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

if (has_sib || base == rX86_SP) {

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// SP requires a SIB byte.

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++size;

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}

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if (displacement != 0 || base == rBP) {

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// BP requires an explicit displacement, even when it's 0.

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if (entry->opcode != kX86Lea32RA) {

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DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name;

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}

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size += IS_SIMM8(displacement) ? 1 : 4;

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}

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size += entry->skeleton.immediate_bytes;

return size;

}

int X86Mir2Lir::GetInsnSize(LIR* lir) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

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DCHECK(!IsPseudoLirOp(lir->opcode));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode];

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switch (entry->kind) {

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case kData:

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return 4; // 4 bytes of data

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case kNop:

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return lir->operands[0]; // length of nop is sole operand

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case kNullary:

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return 1; // 1 byte of opcode

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

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case kRegOpcode: // lir operands - 0: reg

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return ComputeSize(entry, 0, 0, false) - 1; // substract 1 for modrm

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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case kReg: // lir operands - 0: reg

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return ComputeSize(entry, 0, 0, false);

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case kMem: // lir operands - 0: base, 1: disp

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return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

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case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

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return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

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case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

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return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

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case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

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return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

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case kThreadReg: // lir operands - 0: disp, 1: reg

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return ComputeSize(entry, 0, lir->operands[0], false);

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case kRegReg:

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return ComputeSize(entry, 0, 0, false);

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case kRegRegStore:

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return ComputeSize(entry, 0, 0, false);

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case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

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return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

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case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

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return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

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case kRegThread: // lir operands - 0: reg, 1: disp

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return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

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case kRegImm: { // lir operands - 0: reg, 1: immediate

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size_t size = ComputeSize(entry, 0, 0, false);

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if (entry->skeleton.ax_opcode == 0) {

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return size;

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} else {

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// AX opcodes don't require the modrm byte.

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int reg = lir->operands[0];

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return size - (reg == rAX ? 1 : 0);

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}

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}

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case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

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return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

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case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

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return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

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case kThreadImm: // lir operands - 0: disp, 1: imm

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return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

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case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

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return ComputeSize(entry, 0, 0, false);

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case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

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return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

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case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

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return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

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case kMovRegImm: // lir operands - 0: reg, 1: immediate

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return 1 + entry->skeleton.immediate_bytes;

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case kShiftRegImm: // lir operands - 0: reg, 1: immediate

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// Shift by immediate one has a shorter opcode.

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return ComputeSize(entry, 0, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

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case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

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// Shift by immediate one has a shorter opcode.

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return ComputeSize(entry, lir->operands[0], lir->operands[1], false) -

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(lir->operands[2] == 1 ? 1 : 0);

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case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

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// Shift by immediate one has a shorter opcode.

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return ComputeSize(entry, lir->operands[0], lir->operands[3], true) -

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(lir->operands[4] == 1 ? 1 : 0);

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case kShiftRegCl:

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return ComputeSize(entry, 0, 0, false);

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case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

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return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

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case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

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return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

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case kRegCond: // lir operands - 0: reg, 1: cond

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return ComputeSize(entry, 0, 0, false);

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case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

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return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

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case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

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return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

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case kJcc:

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if (lir->opcode == kX86Jcc8) {

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return 2; // opcode + rel8

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} else {

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DCHECK(lir->opcode == kX86Jcc32);

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return 6; // 2 byte opcode + rel32

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}

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case kJmp:

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if (lir->opcode == kX86Jmp8) {

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return 2; // opcode + rel8

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} else if (lir->opcode == kX86Jmp32) {

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return 5; // opcode + rel32

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} else {

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DCHECK(lir->opcode == kX86JmpR);

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return 2; // opcode + modrm

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}

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case kCall:

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switch (lir->opcode) {

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case kX86CallR: return 2; // opcode modrm

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case kX86CallM: // lir operands - 0: base, 1: disp

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return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

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case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

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return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

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case kX86CallT: // lir operands - 0: disp

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return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

default:

break;

}

break;

case kPcRel:

if (entry->opcode == kX86PcRelLoadRA) {

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// lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

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return ComputeSize(entry, lir->operands[1], 0x12345678, true);

485

} else {

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DCHECK(entry->opcode == kX86PcRelAdr);

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

487

return 5; // opcode with reg + 4 byte immediate

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

488

}

489

case kMacro:

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DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));

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return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +

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ComputeSize(&X86Mir2Lir::EncodingMap[kX86Sub32RI], 0, 0, false) -

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(lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

return 0;

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

501

void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry) {

502

if (entry->skeleton.prefix1 != 0) {

503

code_buffer_.push_back(entry->skeleton.prefix1);

504

if (entry->skeleton.prefix2 != 0) {

505

code_buffer_.push_back(entry->skeleton.prefix2);

506

}

507

} else {

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DCHECK_EQ(0, entry->skeleton.prefix2);

}

}

void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) {

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code_buffer_.push_back(entry->skeleton.opcode);

514

if (entry->skeleton.opcode == 0x0F) {

515

code_buffer_.push_back(entry->skeleton.extra_opcode1);

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if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

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code_buffer_.push_back(entry->skeleton.extra_opcode2);

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} else {

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DCHECK_EQ(0, entry->skeleton.extra_opcode2);

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}

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} else {

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DCHECK_EQ(0, entry->skeleton.extra_opcode1);

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DCHECK_EQ(0, entry->skeleton.extra_opcode2);

}

}

void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry) {

EmitPrefix(entry);

EmitOpcode(entry);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

532

static uint8_t ModrmForDisp(int base, int disp) {

533

// BP requires an explicit disp, so do not omit it in the 0 case

534

if (disp == 0 && base != rBP) {

535

return 0;

536

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

543

void X86Mir2Lir::EmitDisp(uint8_t base, int disp) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

544

// BP requires an explicit disp, so do not omit it in the 0 case

545

if (disp == 0 && base != rBP) {

546

return;

547

} else if (IS_SIMM8(disp)) {

548

code_buffer_.push_back(disp & 0xFF);

549

} else {

550

code_buffer_.push_back(disp & 0xFF);

551

code_buffer_.push_back((disp >> 8) & 0xFF);

552

code_buffer_.push_back((disp >> 16) & 0xFF);

553

code_buffer_.push_back((disp >> 24) & 0xFF);

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

557

void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp) {

558

DCHECK_LT(reg_or_opcode, 8);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

559

DCHECK_LT(base, 8);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

560

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | base;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

561

code_buffer_.push_back(modrm);

562

if (base == rX86_SP) {

563

// Special SIB for SP base

564

code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);

565

}

566

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

567

}

568

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

569

void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index,

570

int scale, int disp) {

571

DCHECK_LT(reg_or_opcode, 8);

572

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | rX86_SP;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

573

code_buffer_.push_back(modrm);

DCHECK_LT(scale, 4);

DCHECK_LT(index, 8);

DCHECK_LT(base, 8);

uint8_t sib = (scale << 6) | (index << 3) | base;

578

code_buffer_.push_back(sib);

579

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

580

}

581

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

582

void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int imm) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

583

switch (entry->skeleton.immediate_bytes) {

584

case 1:

585

DCHECK(IS_SIMM8(imm));

586

code_buffer_.push_back(imm & 0xFF);

587

break;

588

case 2:

589

DCHECK(IS_SIMM16(imm));

590

code_buffer_.push_back(imm & 0xFF);

591

code_buffer_.push_back((imm >> 8) & 0xFF);

592

break;

593

case 4:

594

code_buffer_.push_back(imm & 0xFF);

595

code_buffer_.push_back((imm >> 8) & 0xFF);

596

code_buffer_.push_back((imm >> 16) & 0xFF);

597

code_buffer_.push_back((imm >> 24) & 0xFF);

598

break;

599

default:

600

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

601

<< ") for instruction: " << entry->name;

break;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

606

void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg) {

607

EmitPrefixAndOpcode(entry);

608

// There's no 3-byte instruction with +rd

609

DCHECK(entry->skeleton.opcode != 0x0F ||

610

(entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A));

611

DCHECK(!X86_FPREG(reg));

612

DCHECK_LT(reg, 8);

613

code_buffer_.back() += reg;

614

DCHECK_EQ(0, entry->skeleton.ax_opcode);

615

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

616

}

617

618

void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) {

619

EmitPrefixAndOpcode(entry);

620

if (X86_FPREG(reg)) {

621

reg = reg & X86_FP_REG_MASK;

622

}

623

if (reg >= 4) {

624

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

625

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

626

}

627

DCHECK_LT(reg, 8);

628

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

629

code_buffer_.push_back(modrm);

630

DCHECK_EQ(0, entry->skeleton.ax_opcode);

631

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

632

}

633

634

void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) {

635

EmitPrefix(entry);

636

code_buffer_.push_back(entry->skeleton.opcode);

637

DCHECK_NE(0x0F, entry->skeleton.opcode);

638

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

639

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

640

DCHECK_NE(rX86_SP, base);

641

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

642

DCHECK_EQ(0, entry->skeleton.ax_opcode);

643

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

644

}

645

646

void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index,

647

int scale, int disp) {

648

EmitPrefixAndOpcode(entry);

649

EmitModrmSibDisp(entry->skeleton.modrm_opcode, base, index, scale, disp);

650

DCHECK_EQ(0, entry->skeleton.ax_opcode);

651

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

652

}

653

654

void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry,

655

uint8_t base, int disp, uint8_t reg) {

656

EmitPrefixAndOpcode(entry);

657

if (X86_FPREG(reg)) {

658

reg = reg & X86_FP_REG_MASK;

659

}

660

if (reg >= 4) {

661

DCHECK(strchr(entry->name, '8') == NULL ||

662

entry->opcode == kX86Movzx8RM || entry->opcode == kX86Movsx8RM)

663

<< entry->name << " " << static_cast<int>(reg)

664

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

665

}

666

EmitModrmDisp(reg, base, disp);

667

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

668

DCHECK_EQ(0, entry->skeleton.ax_opcode);

669

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

670

}

671

672

void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry,

673

uint8_t reg, uint8_t base, int disp) {

674

// Opcode will flip operands.

675

EmitMemReg(entry, base, disp, reg);

676

}

677

678

void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index,

679

int scale, int disp) {

680

EmitPrefixAndOpcode(entry);

681

if (X86_FPREG(reg)) {

682

reg = reg & X86_FP_REG_MASK;

683

}

684

EmitModrmSibDisp(reg, base, index, scale, disp);

685

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

686

DCHECK_EQ(0, entry->skeleton.ax_opcode);

687

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

688

}

689

690

void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp,

691

uint8_t reg) {

692

// Opcode will flip operands.

693

EmitRegArray(entry, reg, base, index, scale, disp);

694

}

695

696

void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) {

697

DCHECK_NE(entry->skeleton.prefix1, 0);

698

EmitPrefixAndOpcode(entry);

699

if (X86_FPREG(reg)) {

700

reg = reg & X86_FP_REG_MASK;

701

}

702

if (reg >= 4) {

703

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

704

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

705

}

706

DCHECK_LT(reg, 8);

707

uint8_t modrm = (0 << 6) | (reg << 3) | rBP;

708

code_buffer_.push_back(modrm);

709

code_buffer_.push_back(disp & 0xFF);

710

code_buffer_.push_back((disp >> 8) & 0xFF);

711

code_buffer_.push_back((disp >> 16) & 0xFF);

712

code_buffer_.push_back((disp >> 24) & 0xFF);

713

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

714

DCHECK_EQ(0, entry->skeleton.ax_opcode);

715

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

716

}

717

718

void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) {

719

EmitPrefixAndOpcode(entry);

720

if (X86_FPREG(reg1)) {

721

reg1 = reg1 & X86_FP_REG_MASK;

722

}

723

if (X86_FPREG(reg2)) {

724

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

729

code_buffer_.push_back(modrm);

730

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

731

DCHECK_EQ(0, entry->skeleton.ax_opcode);

732

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

733

}

734

735

void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry,

736

uint8_t reg1, uint8_t reg2, int32_t imm) {

737

EmitPrefixAndOpcode(entry);

738

if (X86_FPREG(reg1)) {

739

reg1 = reg1 & X86_FP_REG_MASK;

740

}

741

if (X86_FPREG(reg2)) {

742

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

747

code_buffer_.push_back(modrm);

748

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

749

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

753

void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

754

if (entry->skeleton.prefix1 != 0) {

755

code_buffer_.push_back(entry->skeleton.prefix1);

756

if (entry->skeleton.prefix2 != 0) {

757

code_buffer_.push_back(entry->skeleton.prefix2);

758

}

759

} else {

760

DCHECK_EQ(0, entry->skeleton.prefix2);

761

}

762

if (reg == rAX && entry->skeleton.ax_opcode != 0) {

763

code_buffer_.push_back(entry->skeleton.ax_opcode);

764

} else {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

765

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

766

if (X86_FPREG(reg)) {

767

reg = reg & X86_FP_REG_MASK;

768

}

769

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

770

code_buffer_.push_back(modrm);

771

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

772

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

773

}

774

775

void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

776

EmitPrefixAndOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

777

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

778

code_buffer_.push_back(modrm);

779

code_buffer_.push_back(disp & 0xFF);

780

code_buffer_.push_back((disp >> 8) & 0xFF);

781

code_buffer_.push_back((disp >> 16) & 0xFF);

782

code_buffer_.push_back((disp >> 24) & 0xFF);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

783

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

784

DCHECK_EQ(entry->skeleton.ax_opcode, 0);

785

}

786

787

void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

788

DCHECK_LT(reg, 8);

789

code_buffer_.push_back(0xB8 + reg);

790

code_buffer_.push_back(imm & 0xFF);

791

code_buffer_.push_back((imm >> 8) & 0xFF);

792

code_buffer_.push_back((imm >> 16) & 0xFF);

793

code_buffer_.push_back((imm >> 24) & 0xFF);

794

}

795

796

void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

797

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

798

if (imm != 1) {

799

code_buffer_.push_back(entry->skeleton.opcode);

800

} else {

801

// Shorter encoding for 1 bit shift

802

code_buffer_.push_back(entry->skeleton.ax_opcode);

803

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

804

DCHECK_NE(0x0F, entry->skeleton.opcode);

805

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

806

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

807

if (reg >= 4) {

808

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

809

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

810

}

811

DCHECK_LT(reg, 8);

812

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

813

code_buffer_.push_back(modrm);

814

if (imm != 1) {

815

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

816

DCHECK(IS_SIMM8(imm));

817

code_buffer_.push_back(imm & 0xFF);

}

}

void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl) {

822

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

823

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

824

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

825

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

826

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

827

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

828

DCHECK_LT(reg, 8);

829

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

830

code_buffer_.push_back(modrm);

831

DCHECK_EQ(0, entry->skeleton.ax_opcode);

832

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

833

}

834

835

void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) {

836

if (entry->skeleton.prefix1 != 0) {

837

code_buffer_.push_back(entry->skeleton.prefix1);

838

if (entry->skeleton.prefix2 != 0) {

839

code_buffer_.push_back(entry->skeleton.prefix2);

840

}

841

} else {

842

DCHECK_EQ(0, entry->skeleton.prefix2);

843

}

844

DCHECK_EQ(0, entry->skeleton.ax_opcode);

845

DCHECK_EQ(0x0F, entry->skeleton.opcode);

846

code_buffer_.push_back(0x0F);

847

DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);

848

code_buffer_.push_back(0x90 | condition);

849

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

850

DCHECK_LT(reg, 8);

851

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

852

code_buffer_.push_back(modrm);

853

DCHECK_EQ(entry->skeleton.immediate_bytes, 0);

854

}

855

856

void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int rel) {

857

if (entry->opcode == kX86Jmp8) {

858

DCHECK(IS_SIMM8(rel));

859

code_buffer_.push_back(0xEB);

860

code_buffer_.push_back(rel & 0xFF);

861

} else if (entry->opcode == kX86Jmp32) {

862

code_buffer_.push_back(0xE9);

863

code_buffer_.push_back(rel & 0xFF);

864

code_buffer_.push_back((rel >> 8) & 0xFF);

865

code_buffer_.push_back((rel >> 16) & 0xFF);

866

code_buffer_.push_back((rel >> 24) & 0xFF);

867

} else {

868

DCHECK(entry->opcode == kX86JmpR);

869

code_buffer_.push_back(entry->skeleton.opcode);

870

uint8_t reg = static_cast<uint8_t>(rel);

871

DCHECK_LT(reg, 8);

872

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

873

code_buffer_.push_back(modrm);

}

}

void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc) {

878

DCHECK_LT(cc, 16);

879

if (entry->opcode == kX86Jcc8) {

880

DCHECK(IS_SIMM8(rel));

881

code_buffer_.push_back(0x70 | cc);

882

code_buffer_.push_back(rel & 0xFF);

883

} else {

884

DCHECK(entry->opcode == kX86Jcc32);

885

code_buffer_.push_back(0x0F);

886

code_buffer_.push_back(0x80 | cc);

887

code_buffer_.push_back(rel & 0xFF);

888

code_buffer_.push_back((rel >> 8) & 0xFF);

889

code_buffer_.push_back((rel >> 16) & 0xFF);

890

code_buffer_.push_back((rel >> 24) & 0xFF);

}

}

void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

895

EmitPrefixAndOpcode(entry);

896

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

897

DCHECK_EQ(0, entry->skeleton.ax_opcode);

898

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

899

}

900

901

void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int disp) {

902

DCHECK_NE(entry->skeleton.prefix1, 0);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

903

EmitPrefixAndOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

904

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

905

code_buffer_.push_back(modrm);

906

code_buffer_.push_back(disp & 0xFF);

907

code_buffer_.push_back((disp >> 8) & 0xFF);

908

code_buffer_.push_back((disp >> 16) & 0xFF);

909

code_buffer_.push_back((disp >> 24) & 0xFF);

910

DCHECK_EQ(0, entry->skeleton.ax_opcode);

911

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

912

}

913

914

void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, uint8_t reg,

915

int base_or_table, uint8_t index, int scale, int table_or_disp) {

916

int disp;

917

if (entry->opcode == kX86PcRelLoadRA) {

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

918

Mir2Lir::EmbeddedData *tab_rec =

919

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

920

disp = tab_rec->offset;

921

} else {

922

DCHECK(entry->opcode == kX86PcRelAdr);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

923

Mir2Lir::EmbeddedData *tab_rec =

924

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(base_or_table));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

925

disp = tab_rec->offset;

926

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

927

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

928

if (X86_FPREG(reg)) {

929

reg = reg & X86_FP_REG_MASK;

930

}

931

DCHECK_LT(reg, 8);

932

if (entry->opcode == kX86PcRelLoadRA) {

933

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

934

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

935

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

936

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

937

uint8_t modrm = (2 << 6) | (reg << 3) | rX86_SP;

938

code_buffer_.push_back(modrm);

939

DCHECK_LT(scale, 4);

940

DCHECK_LT(index, 8);

941

DCHECK_LT(base_or_table, 8);

942

uint8_t base = static_cast<uint8_t>(base_or_table);

943

uint8_t sib = (scale << 6) | (index << 3) | base;

944

code_buffer_.push_back(sib);

945

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

946

} else {

947

code_buffer_.push_back(entry->skeleton.opcode + reg);

948

}

949

code_buffer_.push_back(disp & 0xFF);

950

code_buffer_.push_back((disp >> 8) & 0xFF);

951

code_buffer_.push_back((disp >> 16) & 0xFF);

952

code_buffer_.push_back((disp >> 24) & 0xFF);

953

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

954

DCHECK_EQ(0, entry->skeleton.ax_opcode);

955

}

956

957

void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset) {

958

DCHECK(entry->opcode == kX86StartOfMethod) << entry->name;

959

code_buffer_.push_back(0xE8); // call +0

960

code_buffer_.push_back(0);

961

code_buffer_.push_back(0);

962

code_buffer_.push_back(0);

963

code_buffer_.push_back(0);

964

965

DCHECK_LT(reg, 8);

966

code_buffer_.push_back(0x58 + reg); // pop reg

967

968

EmitRegImm(&X86Mir2Lir::EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */);

969

}

970

971

void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) {

972

UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " "

973

<< BuildInsnString(entry->fmt, lir, 0);

974

for (int i = 0; i < GetInsnSize(lir); ++i) {

975

code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3

}

}

/*

* Assemble the LIR into binary instruction format. Note that we may

981

* discover that pc-relative displacements may not fit the selected

982

* instruction. In those cases we will try to substitute a new code

983

* sequence or request that the trace be shortened and retried.

984

*/

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

985

AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

986

LIR *lir;

987

AssemblerStatus res = kSuccess; // Assume success

988

989

const bool kVerbosePcFixup = false;

990

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

991

if (IsPseudoLirOp(lir->opcode)) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

continue;

}

if (lir->flags.is_nop) {

continue;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

999

if (lir->flags.fixup != kFixupNone) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1000

switch (lir->opcode) {

1001

case kX86Jcc8: {

1002

LIR *target_lir = lir->target;

1003

DCHECK(target_lir != NULL);

1004

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1005

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1006

if (IS_SIMM8(lir->operands[0])) {

1007

pc = lir->offset + 2 /* opcode + rel8 */;

1008

} else {

1009

pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1010

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1011

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1012

delta = target - pc;

1013

if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1014

if (kVerbosePcFixup) {

1015

LOG(INFO) << "Retry for JCC growth at " << lir->offset

1016

<< " delta: " << delta << " old delta: " << lir->operands[0];

1017

}

1018

lir->opcode = kX86Jcc32;

1019

SetupResourceMasks(lir);

1020

res = kRetryAll;

1021

}

1022

if (kVerbosePcFixup) {

1023

LOG(INFO) << "Source:";

1024

DumpLIRInsn(lir, 0);

1025

LOG(INFO) << "Target:";

1026

DumpLIRInsn(target_lir, 0);

1027

LOG(INFO) << "Delta " << delta;

1028

}

1029

lir->operands[0] = delta;

break;

}

case kX86Jcc32: {

LIR *target_lir = lir->target;

1034

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1035

CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1036

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1037

int delta = target - pc;

1038

if (kVerbosePcFixup) {

1039

LOG(INFO) << "Source:";

1040

DumpLIRInsn(lir, 0);

1041

LOG(INFO) << "Target:";

1042

DumpLIRInsn(target_lir, 0);

1043

LOG(INFO) << "Delta " << delta;

1044

}

1045

lir->operands[0] = delta;

break;

}

case kX86Jmp8: {

LIR *target_lir = lir->target;

1050

DCHECK(target_lir != NULL);

1051

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1052

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1053

if (IS_SIMM8(lir->operands[0])) {

1054

pc = lir->offset + 2 /* opcode + rel8 */;

1055

} else {

1056

pc = lir->offset + 5 /* opcode + rel32 */;

1057

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1058

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1059

delta = target - pc;

1060

if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) {

1061

// Useless branch

buzbee

252254b

2013-09-08 16:20:53 -0700

[diff] [blame]

1062

NopLIR(lir);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1063

if (kVerbosePcFixup) {

1064

LOG(INFO) << "Retry for useless branch at " << lir->offset;

1065

}

1066

res = kRetryAll;

1067

} else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1068

if (kVerbosePcFixup) {

1069

LOG(INFO) << "Retry for JMP growth at " << lir->offset;

1070

}

1071

lir->opcode = kX86Jmp32;

1072

SetupResourceMasks(lir);

1073

res = kRetryAll;

1074

}

1075

lir->operands[0] = delta;

break;

}

case kX86Jmp32: {

LIR *target_lir = lir->target;

1080

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1081

CodeOffset pc = lir->offset + 5 /* opcode + rel32 */;

1082

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1083

int delta = target - pc;

1084

lir->operands[0] = delta;

break;

}

default:

break;

}

}

/*

* If one of the pc-relative instructions expanded we'll have

1094

* to make another pass. Don't bother to fully assemble the

1095

* instruction.

1096

*/

1097

if (res != kSuccess) {

1098

continue;

1099

}

1100

CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size());

1101

const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode];

1102

size_t starting_cbuf_size = code_buffer_.size();

1103

switch (entry->kind) {

1104

case kData: // 4 bytes of data

1105

code_buffer_.push_back(lir->operands[0]);

1106

break;

1107

case kNullary: // 1 byte of opcode

1108

DCHECK_EQ(0, entry->skeleton.prefix1);

1109

DCHECK_EQ(0, entry->skeleton.prefix2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1110

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1111

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1112

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1113

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1114

break;

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

1115

case kRegOpcode: // lir operands - 0: reg

1116

EmitOpRegOpcode(entry, lir->operands[0]);

1117

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1118

case kReg: // lir operands - 0: reg

1119

EmitOpReg(entry, lir->operands[0]);

1120

break;

1121

case kMem: // lir operands - 0: base, 1: disp

1122

EmitOpMem(entry, lir->operands[0], lir->operands[1]);

1123

break;

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1124

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

1125

EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]);

1126

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1127

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

1128

EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1129

break;

1130

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

1131

EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1132

lir->operands[3], lir->operands[4]);

1133

break;

1134

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

1135

EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1136

break;

1137

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

1138

EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1139

lir->operands[3], lir->operands[4]);

1140

break;

1141

case kRegThread: // lir operands - 0: reg, 1: disp

1142

EmitRegThread(entry, lir->operands[0], lir->operands[1]);

1143

break;

1144

case kRegReg: // lir operands - 0: reg1, 1: reg2

1145

EmitRegReg(entry, lir->operands[0], lir->operands[1]);

1146

break;

1147

case kRegRegStore: // lir operands - 0: reg2, 1: reg1

1148

EmitRegReg(entry, lir->operands[1], lir->operands[0]);

1149

break;

1150

case kRegRegImm:

1151

EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1152

break;

1153

case kRegImm: // lir operands - 0: reg, 1: immediate

1154

EmitRegImm(entry, lir->operands[0], lir->operands[1]);

1155

break;

1156

case kThreadImm: // lir operands - 0: disp, 1: immediate

1157

EmitThreadImm(entry, lir->operands[0], lir->operands[1]);

1158

break;

1159

case kMovRegImm: // lir operands - 0: reg, 1: immediate

1160

EmitMovRegImm(entry, lir->operands[0], lir->operands[1]);

1161

break;

1162

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

1163

EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]);

1164

break;

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

1165

case kShiftRegCl: // lir operands - 0: reg, 1: cl

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1166

EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]);

1167

break;

1168

case kRegCond: // lir operands - 0: reg, 1: condition

1169

EmitRegCond(entry, lir->operands[0], lir->operands[1]);

1170

break;

1171

case kJmp: // lir operands - 0: rel

1172

EmitJmp(entry, lir->operands[0]);

1173

break;

1174

case kJcc: // lir operands - 0: rel, 1: CC, target assigned

1175

EmitJcc(entry, lir->operands[0], lir->operands[1]);

1176

break;

1177

case kCall:

1178

switch (entry->opcode) {

1179

case kX86CallM: // lir operands - 0: base, 1: disp

1180

EmitCallMem(entry, lir->operands[0], lir->operands[1]);

1181

break;

1182

case kX86CallT: // lir operands - 0: disp

1183

EmitCallThread(entry, lir->operands[0]);

1184

break;

1185

default:

1186

EmitUnimplemented(entry, lir);

break;

}

break;

case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

1191

EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1192

lir->operands[3], lir->operands[4]);

1193

break;

1194

case kMacro:

1195

EmitMacro(entry, lir->operands[0], lir->offset);

1196

break;

1197

default:

1198

EmitUnimplemented(entry, lir);

1199

break;

1200

}

1201

CHECK_EQ(static_cast<size_t>(GetInsnSize(lir)),

1202

code_buffer_.size() - starting_cbuf_size)

1203

<< "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name;

}

return res;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1208

// LIR offset assignment.

1209

// TODO: consolidate w/ Arm assembly mechanism.

1210

int X86Mir2Lir::AssignInsnOffsets() {

LIR* lir;

int offset = 0;

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

1215

lir->offset = offset;

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1216

if (LIKELY(!IsPseudoLirOp(lir->opcode))) {

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1217

if (!lir->flags.is_nop) {

1218

offset += lir->flags.size;

1219

}

1220

} else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) {

1221

if (offset & 0x2) {

1222

offset += 2;

1223

lir->operands[0] = 1;

1224

} else {

1225

lir->operands[0] = 0;

1226

}

1227

}

1228

/* Pseudo opcodes don't consume space */

}

return offset;

}

/*

* Walk the compilation unit and assign offsets to instructions

1235

* and literals and compute the total size of the compiled unit.

1236

* TODO: consolidate w/ Arm assembly mechanism.

1237

*/

1238

void X86Mir2Lir::AssignOffsets() {

1239

int offset = AssignInsnOffsets();

1240

1241

/* Const values have to be word aligned */

1242

offset = (offset + 3) & ~3;

1243

1244

/* Set up offsets for literals */

1245

data_offset_ = offset;

1246

1247

offset = AssignLiteralOffset(offset);

1248

1249

offset = AssignSwitchTablesOffset(offset);

1250

1251

offset = AssignFillArrayDataOffset(offset);

1252

1253

total_size_ = offset;

}

/*

* Go over each instruction in the list and calculate the offset from the top

1258

* before sending them off to the assembler. If out-of-range branch distance is

1259

* seen rearrange the instructions a bit to correct it.

1260

* TODO: consolidate w/ Arm assembly mechanism.

1261

*/

1262

void X86Mir2Lir::AssembleLIR() {

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1263

cu_->NewTimingSplit("Assemble");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1264

AssignOffsets();

1265

int assembler_retries = 0;

1266

/*

1267

* Assemble here. Note that we generate code with optimistic assumptions

1268

* and if found now to work, we'll have to redo the sequence and retry.

*/

while (true) {

AssemblerStatus res = AssembleInstructions(0);

1273

if (res == kSuccess) {

break;

} else {

assembler_retries++;

if (assembler_retries > MAX_ASSEMBLER_RETRIES) {

1278

CodegenDump();

1279

LOG(FATAL) << "Assembler error - too many retries";

1280

}

1281

// Redo offsets and try again

1282

AssignOffsets();

1283

code_buffer_.clear();

}

}

// Install literals

InstallLiteralPools();

1289

1290

// Install switch tables

1291

InstallSwitchTables();

1292

1293

// Install fill array data

1294

InstallFillArrayData();

1295

1296

// Create the mapping table and native offset to reference map.

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1297

cu_->NewTimingSplit("PcMappingTable");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1298

CreateMappingTables();

1299

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1300

cu_->NewTimingSplit("GcMap");

buzbee