blob: a98a99ec4eedf79a23b4fb2510c10ef1221d42ff [file] [log] [blame]
Brian Carlstrom7940e442013-07-12 13:46:57 -07001/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
Brian Carlstromfc0e3212013-07-17 14:40:12 -070017#ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_
18#define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_
Brian Carlstrom7940e442013-07-12 13:46:57 -070019
Andreas Gampe0b9203e2015-01-22 20:39:27 -080020#include "base/logging.h"
21#include "dex/compiler_ir.h"
22#include "dex/mir_graph.h"
Andreas Gampe53c913b2014-08-12 23:19:23 -070023#include "dex/quick/mir_to_lir.h"
Brian Carlstrom7940e442013-07-12 13:46:57 -070024#include "x86_lir.h"
25
Dmitry Petrochenko58994cd2014-05-17 01:02:18 +070026#include <map>
Maxim Kazantsev6dccdc22014-08-18 18:43:55 +070027#include <vector>
Dmitry Petrochenko58994cd2014-05-17 01:02:18 +070028
Brian Carlstrom7940e442013-07-12 13:46:57 -070029namespace art {
30
Mark Mendelle87f9b52014-04-30 14:13:18 -040031class X86Mir2Lir : public Mir2Lir {
Ian Rogers0f9b9c52014-06-09 01:32:12 -070032 protected:
Ian Rogers0f9b9c52014-06-09 01:32:12 -070033 class InToRegStorageX86_64Mapper : public InToRegStorageMapper {
34 public:
Serguei Katkov717a3e42014-11-13 17:19:42 +060035 explicit InToRegStorageX86_64Mapper(Mir2Lir* m2l)
36 : m2l_(m2l), cur_core_reg_(0), cur_fp_reg_(0) {}
37 virtual RegStorage GetNextReg(ShortyArg arg);
38 virtual void Reset() OVERRIDE {
39 cur_core_reg_ = 0;
40 cur_fp_reg_ = 0;
41 }
Chao-ying Fua77ee512014-07-01 17:43:41 -070042 protected:
Serguei Katkov717a3e42014-11-13 17:19:42 +060043 Mir2Lir* m2l_;
Serguei Katkov717a3e42014-11-13 17:19:42 +060044 size_t cur_core_reg_;
45 size_t cur_fp_reg_;
Ian Rogers0f9b9c52014-06-09 01:32:12 -070046 };
Dmitry Petrochenko58994cd2014-05-17 01:02:18 +070047
Mark P Mendell966c3ae2015-01-27 15:45:27 +000048 class InToRegStorageX86Mapper : public InToRegStorageX86_64Mapper {
Ian Rogers0f9b9c52014-06-09 01:32:12 -070049 public:
Mark P Mendell966c3ae2015-01-27 15:45:27 +000050 explicit InToRegStorageX86Mapper(Mir2Lir* m2l)
51 : InToRegStorageX86_64Mapper(m2l) { }
Serguei Katkov717a3e42014-11-13 17:19:42 +060052 virtual RegStorage GetNextReg(ShortyArg arg);
Ian Rogers0f9b9c52014-06-09 01:32:12 -070053 };
Dmitry Petrochenko58994cd2014-05-17 01:02:18 +070054
Serguei Katkov717a3e42014-11-13 17:19:42 +060055 InToRegStorageX86_64Mapper in_to_reg_storage_x86_64_mapper_;
56 InToRegStorageX86Mapper in_to_reg_storage_x86_mapper_;
57 InToRegStorageMapper* GetResetedInToRegStorageMapper() OVERRIDE {
58 InToRegStorageMapper* res;
59 if (cu_->target64) {
60 res = &in_to_reg_storage_x86_64_mapper_;
61 } else {
62 res = &in_to_reg_storage_x86_mapper_;
63 }
64 res->Reset();
65 return res;
66 }
67
Maxim Kazantsev6dccdc22014-08-18 18:43:55 +070068 class ExplicitTempRegisterLock {
69 public:
70 ExplicitTempRegisterLock(X86Mir2Lir* mir_to_lir, int n_regs, ...);
71 ~ExplicitTempRegisterLock();
72 protected:
73 std::vector<RegStorage> temp_regs_;
74 X86Mir2Lir* const mir_to_lir_;
75 };
76
Serguei Katkov717a3e42014-11-13 17:19:42 +060077 virtual int GenDalvikArgsBulkCopy(CallInfo* info, int first, int count) OVERRIDE;
78
Ian Rogers0f9b9c52014-06-09 01:32:12 -070079 public:
Elena Sayapinadd644502014-07-01 18:39:52 +070080 X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
Brian Carlstrom7940e442013-07-12 13:46:57 -070081
Ian Rogers0f9b9c52014-06-09 01:32:12 -070082 // Required for target - codegen helpers.
83 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +070084 RegLocation rl_dest, int lit) OVERRIDE;
Ian Rogers0f9b9c52014-06-09 01:32:12 -070085 bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE;
Ningsheng Jian675e09b2014-10-23 13:48:36 +080086 void GenMultiplyByConstantFloat(RegLocation rl_dest, RegLocation rl_src1,
87 int32_t constant) OVERRIDE;
88 void GenMultiplyByConstantDouble(RegLocation rl_dest, RegLocation rl_src1,
89 int64_t constant) OVERRIDE;
Ian Rogers0f9b9c52014-06-09 01:32:12 -070090 LIR* CheckSuspendUsingLoad() OVERRIDE;
Andreas Gampe98430592014-07-27 19:44:50 -070091 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE;
Ian Rogers0f9b9c52014-06-09 01:32:12 -070092 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
Andreas Gampe3c12c512014-06-24 18:46:29 +000093 OpSize size, VolatileKind is_volatile) OVERRIDE;
Ian Rogers0f9b9c52014-06-09 01:32:12 -070094 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
Vladimir Marko3bf7c602014-05-07 14:55:43 +010095 OpSize size) OVERRIDE;
Ian Rogers0f9b9c52014-06-09 01:32:12 -070096 LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
97 LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
Yevgeny Rouban6af82062014-11-26 18:11:54 +060098 void GenLongToInt(RegLocation rl_dest, RegLocation rl_src);
Ian Rogers0f9b9c52014-06-09 01:32:12 -070099 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
Andreas Gampe3c12c512014-06-24 18:46:29 +0000100 OpSize size, VolatileKind is_volatile) OVERRIDE;
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700101 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
102 OpSize size) OVERRIDE;
Vladimir Markobf535be2014-11-19 18:52:35 +0000103
104 /// @copydoc Mir2Lir::UnconditionallyMarkGCCard(RegStorage)
105 void UnconditionallyMarkGCCard(RegStorage tgt_addr_reg) OVERRIDE;
106
Vladimir Markodc56cc52015-03-27 18:18:36 +0000107 bool CanUseOpPcRelDexCacheArrayLoad() const OVERRIDE;
108 void OpPcRelDexCacheArrayLoad(const DexFile* dex_file, int offset, RegStorage r_dest) OVERRIDE;
109
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700110 void GenImplicitNullCheck(RegStorage reg, int opt_flags) OVERRIDE;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700111
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700112 // Required for target - register utilities.
Chao-ying Fua77ee512014-07-01 17:43:41 -0700113 RegStorage TargetReg(SpecialTargetRegister reg) OVERRIDE;
Andreas Gampeccc60262014-07-04 18:02:38 -0700114 RegStorage TargetReg(SpecialTargetRegister symbolic_reg, WideKind wide_kind) OVERRIDE {
115 if (wide_kind == kWide) {
116 if (cu_->target64) {
117 return As64BitReg(TargetReg32(symbolic_reg));
118 } else {
Mark P Mendell966c3ae2015-01-27 15:45:27 +0000119 if (symbolic_reg >= kFArg0 && symbolic_reg <= kFArg3) {
120 // We want an XMM, not a pair.
121 return As64BitReg(TargetReg32(symbolic_reg));
122 }
Andreas Gampeccc60262014-07-04 18:02:38 -0700123 // x86: construct a pair.
124 DCHECK((kArg0 <= symbolic_reg && symbolic_reg < kArg3) ||
Andreas Gampeccc60262014-07-04 18:02:38 -0700125 (kRet0 == symbolic_reg));
126 return RegStorage::MakeRegPair(TargetReg32(symbolic_reg),
127 TargetReg32(static_cast<SpecialTargetRegister>(symbolic_reg + 1)));
128 }
129 } else if (wide_kind == kRef && cu_->target64) {
130 return As64BitReg(TargetReg32(symbolic_reg));
Chao-ying Fua77ee512014-07-01 17:43:41 -0700131 } else {
Andreas Gampeccc60262014-07-04 18:02:38 -0700132 return TargetReg32(symbolic_reg);
Chao-ying Fua77ee512014-07-01 17:43:41 -0700133 }
134 }
Chao-ying Fua77ee512014-07-01 17:43:41 -0700135 RegStorage TargetPtrReg(SpecialTargetRegister symbolic_reg) OVERRIDE {
Andreas Gampeccc60262014-07-04 18:02:38 -0700136 return TargetReg(symbolic_reg, cu_->target64 ? kWide : kNotWide);
Chao-ying Fua77ee512014-07-01 17:43:41 -0700137 }
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700138
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700139 RegLocation GetReturnAlt() OVERRIDE;
140 RegLocation GetReturnWideAlt() OVERRIDE;
141 RegLocation LocCReturn() OVERRIDE;
142 RegLocation LocCReturnRef() OVERRIDE;
143 RegLocation LocCReturnDouble() OVERRIDE;
144 RegLocation LocCReturnFloat() OVERRIDE;
145 RegLocation LocCReturnWide() OVERRIDE;
146
Vladimir Marko8dea81c2014-06-06 14:50:36 +0100147 ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE;
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700148 void AdjustSpillMask() OVERRIDE;
149 void ClobberCallerSave() OVERRIDE;
150 void FreeCallTemps() OVERRIDE;
151 void LockCallTemps() OVERRIDE;
152
153 void CompilerInitializeRegAlloc() OVERRIDE;
154 int VectorRegisterSize() OVERRIDE;
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700155 int NumReservableVectorRegisters(bool long_or_fp) OVERRIDE;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700156
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700157 // Required for target - miscellaneous.
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700158 void AssembleLIR() OVERRIDE;
Vladimir Marko8dea81c2014-06-06 14:50:36 +0100159 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
160 void SetupTargetResourceMasks(LIR* lir, uint64_t flags,
161 ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE;
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700162 const char* GetTargetInstFmt(int opcode) OVERRIDE;
163 const char* GetTargetInstName(int opcode) OVERRIDE;
164 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) OVERRIDE;
Vladimir Marko8dea81c2014-06-06 14:50:36 +0100165 ResourceMask GetPCUseDefEncoding() const OVERRIDE;
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700166 uint64_t GetTargetInstFlags(int opcode) OVERRIDE;
Ian Rogers5aa6e042014-06-13 16:38:24 -0700167 size_t GetInsnSize(LIR* lir) OVERRIDE;
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700168 bool IsUnconditionalBranch(LIR* lir) OVERRIDE;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700169
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700170 // Get the register class for load/store of a field.
171 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
Vladimir Marko674744e2014-04-24 15:18:26 +0100172
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700173 // Required for target - Dalvik-level generators.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700174 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700175 RegLocation rl_dest, int scale) OVERRIDE;
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700176 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700177 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) OVERRIDE;
178
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700179 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700180 RegLocation rl_src2) OVERRIDE;
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700181 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700182 RegLocation rl_src2) OVERRIDE;
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700183 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700184 RegLocation rl_src2) OVERRIDE;
185 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) OVERRIDE;
186
187 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) OVERRIDE;
188 bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) OVERRIDE;
189 bool GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double) OVERRIDE;
Yixin Shou8c914c02014-07-28 14:17:09 -0400190 bool GenInlinedReverseBits(CallInfo* info, OpSize size) OVERRIDE;
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700191 bool GenInlinedSqrt(CallInfo* info) OVERRIDE;
Yixin Shou7071c8d2014-03-05 06:07:48 -0500192 bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE;
193 bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE;
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700194 bool GenInlinedPeek(CallInfo* info, OpSize size) OVERRIDE;
195 bool GenInlinedPoke(CallInfo* info, OpSize size) OVERRIDE;
Andreas Gampe98430592014-07-27 19:44:50 -0700196 bool GenInlinedCharAt(CallInfo* info) OVERRIDE;
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700197
198 // Long instructions.
Andreas Gampec76c6142014-08-04 16:30:03 -0700199 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
Razvan A Lupusoru5c5676b2014-09-29 16:42:11 -0700200 RegLocation rl_src2, int flags) OVERRIDE;
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700201 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
Razvan A Lupusoru5c5676b2014-09-29 16:42:11 -0700202 RegLocation rl_src2, int flags) OVERRIDE;
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700203 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
Razvan A Lupusoru5c5676b2014-09-29 16:42:11 -0700204 RegLocation rl_src1, RegLocation rl_shift, int flags) OVERRIDE;
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700205 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) OVERRIDE;
206 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src) OVERRIDE;
207 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest,
208 RegLocation rl_src1, RegLocation rl_shift) OVERRIDE;
Razvan A Lupusoru3bc01742014-02-06 13:18:43 -0800209
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700210 /*
211 * @brief Generate a two address long operation with a constant value
212 * @param rl_dest location of result
213 * @param rl_src constant source operand
214 * @param op Opcode to be generated
215 * @return success or not
216 */
217 bool GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op);
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700218
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700219 /*
220 * @brief Generate a three address long operation with a constant value
221 * @param rl_dest location of result
222 * @param rl_src1 source operand
223 * @param rl_src2 constant source operand
224 * @param op Opcode to be generated
225 * @return success or not
226 */
227 bool GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2,
228 Instruction::Code op);
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700229 /**
230 * @brief Generate a long arithmetic operation.
231 * @param rl_dest The destination.
232 * @param rl_src1 First operand.
233 * @param rl_src2 Second operand.
234 * @param op The DEX opcode for the operation.
235 * @param is_commutative The sources can be swapped if needed.
236 */
237 virtual void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2,
238 Instruction::Code op, bool is_commutative);
Mark Mendelle02d48f2014-01-15 11:19:23 -0800239
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700240 /**
241 * @brief Generate a two operand long arithmetic operation.
242 * @param rl_dest The destination.
243 * @param rl_src Second operand.
244 * @param op The DEX opcode for the operation.
245 */
246 void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op);
Mark Mendelle02d48f2014-01-15 11:19:23 -0800247
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700248 /**
249 * @brief Generate a long operation.
250 * @param rl_dest The destination. Must be in a register
251 * @param rl_src The other operand. May be in a register or in memory.
252 * @param op The DEX opcode for the operation.
253 */
254 virtual void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700255
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700256
257 // TODO: collapse reg_lo, reg_hi
258 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div)
259 OVERRIDE;
260 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div) OVERRIDE;
261 void GenDivZeroCheckWide(RegStorage reg) OVERRIDE;
262 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) OVERRIDE;
263 void GenExitSequence() OVERRIDE;
264 void GenSpecialExitSequence() OVERRIDE;
Vladimir Marko6ce3eba2015-02-16 13:05:59 +0000265 void GenSpecialEntryForSuspend() OVERRIDE;
266 void GenSpecialExitForSuspend() OVERRIDE;
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700267 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) OVERRIDE;
268 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) OVERRIDE;
269 void GenSelect(BasicBlock* bb, MIR* mir) OVERRIDE;
270 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
271 int32_t true_val, int32_t false_val, RegStorage rs_dest,
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700272 RegisterClass dest_reg_class) OVERRIDE;
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700273 bool GenMemBarrier(MemBarrierKind barrier_kind) OVERRIDE;
274 void GenMoveException(RegLocation rl_dest) OVERRIDE;
275 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,
276 int first_bit, int second_bit) OVERRIDE;
277 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) OVERRIDE;
278 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) OVERRIDE;
Andreas Gampe48971b32014-08-06 10:09:01 -0700279 void GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE;
280 void GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE;
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700281
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700282 /**
283 * @brief Implement instanceof a final class with x86 specific code.
284 * @param use_declaring_class 'true' if we can use the class itself.
285 * @param type_idx Type index to use if use_declaring_class is 'false'.
286 * @param rl_dest Result to be set to 0 or 1.
287 * @param rl_src Object to be tested.
288 */
289 void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest,
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700290 RegLocation rl_src) OVERRIDE;
Chao-ying Fua0147762014-06-06 18:38:49 -0700291
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700292 // Single operation generators.
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700293 LIR* OpUnconditionalBranch(LIR* target) OVERRIDE;
294 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE;
295 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE;
296 LIR* OpCondBranch(ConditionCode cc, LIR* target) OVERRIDE;
297 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE;
298 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE;
299 LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE;
300 void OpEndIT(LIR* it) OVERRIDE;
301 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE;
Vladimir Markof6737f72015-03-23 17:05:14 +0000302 void OpPcRelLoad(RegStorage reg, LIR* target) OVERRIDE;
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700303 LIR* OpReg(OpKind op, RegStorage r_dest_src) OVERRIDE;
304 void OpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE;
305 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) OVERRIDE;
306 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) OVERRIDE;
307 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) OVERRIDE;
308 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) OVERRIDE;
309 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE;
310 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
311 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) OVERRIDE;
312 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE;
313 LIR* OpTestSuspend(LIR* target) OVERRIDE;
314 LIR* OpVldm(RegStorage r_base, int count) OVERRIDE;
315 LIR* OpVstm(RegStorage r_base, int count) OVERRIDE;
316 void OpRegCopyWide(RegStorage dest, RegStorage src) OVERRIDE;
317 bool GenInlinedCurrentThread(CallInfo* info) OVERRIDE;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700318
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700319 bool InexpensiveConstantInt(int32_t value) OVERRIDE;
320 bool InexpensiveConstantFloat(int32_t value) OVERRIDE;
321 bool InexpensiveConstantLong(int64_t value) OVERRIDE;
322 bool InexpensiveConstantDouble(int64_t value) OVERRIDE;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700323
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700324 /*
325 * @brief Should try to optimize for two address instructions?
326 * @return true if we try to avoid generating three operand instructions.
327 */
328 virtual bool GenerateTwoOperandInstructions() const { return true; }
Mark Mendelle87f9b52014-04-30 14:13:18 -0400329
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700330 /*
331 * @brief x86 specific codegen for int operations.
332 * @param opcode Operation to perform.
333 * @param rl_dest Destination for the result.
334 * @param rl_lhs Left hand operand.
335 * @param rl_rhs Right hand operand.
Razvan A Lupusoru5c5676b2014-09-29 16:42:11 -0700336 * @param flags The instruction optimization flags.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700337 */
338 void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs,
Razvan A Lupusoru5c5676b2014-09-29 16:42:11 -0700339 RegLocation rl_rhs, int flags) OVERRIDE;
Mark Mendell55d0eac2014-02-06 11:02:52 -0800340
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700341 /*
342 * @brief Load the Method* of a dex method into the register.
343 * @param target_method The MethodReference of the method to be invoked.
344 * @param type How the method will be invoked.
345 * @param register that will contain the code address.
346 * @note register will be passed to TargetReg to get physical register.
347 */
348 void LoadMethodAddress(const MethodReference& target_method, InvokeType type,
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700349 SpecialTargetRegister symbolic_reg) OVERRIDE;
Mark Mendell55d0eac2014-02-06 11:02:52 -0800350
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700351 /*
352 * @brief Load the Class* of a Dex Class type into the register.
Fred Shihe7f82e22014-08-06 10:46:37 -0700353 * @param dex DexFile that contains the class type.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700354 * @param type How the method will be invoked.
355 * @param register that will contain the code address.
356 * @note register will be passed to TargetReg to get physical register.
357 */
Fred Shihe7f82e22014-08-06 10:46:37 -0700358 void LoadClassType(const DexFile& dex_file, uint32_t type_idx,
359 SpecialTargetRegister symbolic_reg) OVERRIDE;
Mark Mendell55d0eac2014-02-06 11:02:52 -0800360
Vladimir Markof4da6752014-08-01 19:04:18 +0100361 NextCallInsn GetNextSDCallInsn() OVERRIDE;
Mark Mendell55d0eac2014-02-06 11:02:52 -0800362
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700363 /*
364 * @brief Generate a relative call to the method that will be patched at link time.
365 * @param target_method The MethodReference of the method to be invoked.
366 * @param type How the method will be invoked.
367 * @returns Call instruction
368 */
Vladimir Markof4da6752014-08-01 19:04:18 +0100369 LIR* CallWithLinkerFixup(const MethodReference& target_method, InvokeType type);
370
371 /*
372 * @brief Generate the actual call insn based on the method info.
373 * @param method_info the lowering info for the method call.
374 * @returns Call instruction
375 */
376 LIR* GenCallInsn(const MirMethodLoweringInfo& method_info) OVERRIDE;
Mark Mendell55d0eac2014-02-06 11:02:52 -0800377
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700378 /*
379 * @brief Handle x86 specific literals
380 */
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700381 void InstallLiteralPools() OVERRIDE;
Mark Mendellae9fd932014-02-10 16:14:35 -0800382
Andreas Gampe98430592014-07-27 19:44:50 -0700383 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
384
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700385 protected:
Ian Rogersb28c1c02014-11-08 11:21:21 -0800386 RegStorage TargetReg32(SpecialTargetRegister reg) const;
Chao-ying Fua77ee512014-07-01 17:43:41 -0700387 // Casting of RegStorage
388 RegStorage As32BitReg(RegStorage reg) {
389 DCHECK(!reg.IsPair());
390 if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) {
391 if (kFailOnSizeError) {
392 LOG(FATAL) << "Expected 64b register " << reg.GetReg();
393 } else {
394 LOG(WARNING) << "Expected 64b register " << reg.GetReg();
395 return reg;
396 }
397 }
398 RegStorage ret_val = RegStorage(RegStorage::k32BitSolo,
399 reg.GetRawBits() & RegStorage::kRegTypeMask);
400 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k32SoloStorageMask)
401 ->GetReg().GetReg(),
402 ret_val.GetReg());
403 return ret_val;
404 }
405
406 RegStorage As64BitReg(RegStorage reg) {
407 DCHECK(!reg.IsPair());
408 if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) {
409 if (kFailOnSizeError) {
410 LOG(FATAL) << "Expected 32b register " << reg.GetReg();
411 } else {
412 LOG(WARNING) << "Expected 32b register " << reg.GetReg();
413 return reg;
414 }
415 }
416 RegStorage ret_val = RegStorage(RegStorage::k64BitSolo,
417 reg.GetRawBits() & RegStorage::kRegTypeMask);
418 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k64SoloStorageMask)
419 ->GetReg().GetReg(),
420 ret_val.GetReg());
421 return ret_val;
422 }
423
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700424 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
425 RegStorage r_dest, OpSize size);
426 LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
Jean Christophe Beylerb5bce7c2014-07-25 12:32:18 -0700427 RegStorage r_src, OpSize size, int opt_flags = 0);
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700428
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700429 int AssignInsnOffsets();
430 void AssignOffsets();
431 AssemblerStatus AssembleInstructions(CodeOffset start_addr);
432
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700433 size_t ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index,
Ian Rogers5aa6e042014-06-13 16:38:24 -0700434 int32_t raw_base, int32_t displacement);
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700435 void CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg);
436 void EmitPrefix(const X86EncodingMap* entry,
Ian Rogers5aa6e042014-06-13 16:38:24 -0700437 int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b);
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700438 void EmitOpcode(const X86EncodingMap* entry);
439 void EmitPrefixAndOpcode(const X86EncodingMap* entry,
Ian Rogers5aa6e042014-06-13 16:38:24 -0700440 int32_t reg_r, int32_t reg_x, int32_t reg_b);
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700441 void EmitDisp(uint8_t base, int32_t disp);
442 void EmitModrmThread(uint8_t reg_or_opcode);
443 void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp);
444 void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale,
445 int32_t disp);
446 void EmitImm(const X86EncodingMap* entry, int64_t imm);
447 void EmitNullary(const X86EncodingMap* entry);
448 void EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg);
449 void EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg);
450 void EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp);
451 void EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale,
452 int32_t disp);
453 void EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg);
454 void EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t disp);
455 void EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base,
456 int32_t raw_index, int scale, int32_t disp);
457 void EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale,
458 int32_t disp, int32_t raw_reg);
459 void EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm);
460 void EmitArrayImm(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale,
461 int32_t raw_disp, int32_t imm);
462 void EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp);
463 void EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2);
464 void EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t imm);
465 void EmitRegMemImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp,
466 int32_t imm);
467 void EmitMemRegImm(const X86EncodingMap* entry, int32_t base, int32_t disp, int32_t raw_reg1,
468 int32_t imm);
469 void EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm);
470 void EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm);
471 void EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm);
472 void EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm);
473 void EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl);
474 void EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_cl);
Yixin Shouf40f8902014-08-14 14:10:32 -0400475 void EmitShiftRegRegCl(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2,
476 int32_t raw_cl);
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700477 void EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm);
478 void EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc);
479 void EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t cc);
480 void EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t cc);
481 void EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp,
482 int32_t cc);
Razvan A Lupusorubd288c22013-12-20 17:27:23 -0800483
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700484 void EmitJmp(const X86EncodingMap* entry, int32_t rel);
485 void EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc);
486 void EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp);
487 void EmitCallImmediate(const X86EncodingMap* entry, int32_t disp);
488 void EmitCallThread(const X86EncodingMap* entry, int32_t disp);
489 void EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table,
490 int32_t raw_index, int scale, int32_t table_or_disp);
491 void EmitMacro(const X86EncodingMap* entry, int32_t raw_reg, int32_t offset);
492 void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir);
493 void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1,
494 int64_t val, ConditionCode ccode);
495 void GenConstWide(RegLocation rl_dest, int64_t value);
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700496 void GenMultiplyVectorSignedByte(RegStorage rs_dest_src1, RegStorage rs_src2);
497 void GenMultiplyVectorLong(RegStorage rs_dest_src1, RegStorage rs_src2);
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700498 void GenShiftByteVector(MIR* mir);
Yixin Shouf40f8902014-08-14 14:10:32 -0400499 void AndMaskVectorRegister(RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3,
500 uint32_t m4);
501 void MaskVectorRegister(X86OpCode opcode, RegStorage rs_src1, uint32_t m1, uint32_t m2,
502 uint32_t m3, uint32_t m4);
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700503 void AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir);
Mark Mendell0a1174e2014-09-11 14:51:02 -0400504 virtual void LoadVectorRegister(RegStorage rs_dest, RegStorage rs_src, OpSize opsize,
505 int op_mov);
Mark Mendell2637f2e2014-04-30 10:10:47 -0400506
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700507 static bool ProvidesFullMemoryBarrier(X86OpCode opcode);
Mark Mendelle02d48f2014-01-15 11:19:23 -0800508
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700509 /*
510 * @brief Ensure that a temporary register is byte addressable.
511 * @returns a temporary guarenteed to be byte addressable.
512 */
513 virtual RegStorage AllocateByteRegister();
Razvan A Lupusoru99ad7232014-02-25 17:41:08 -0800514
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700515 /*
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700516 * @brief Use a wide temporary as a 128-bit register
517 * @returns a 128-bit temporary register.
518 */
519 virtual RegStorage Get128BitRegister(RegStorage reg);
520
521 /*
Chao-ying Fu7e399fd2014-06-10 18:11:11 -0700522 * @brief Check if a register is byte addressable.
523 * @returns true if a register is byte addressable.
524 */
Ian Rogersb28c1c02014-11-08 11:21:21 -0800525 bool IsByteRegister(RegStorage reg) const;
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700526
527 void GenDivRemLongLit(RegLocation rl_dest, RegLocation rl_src, int64_t imm, bool is_div);
528
DaniilSokolov70c4f062014-06-24 17:34:00 -0700529 bool GenInlinedArrayCopyCharArray(CallInfo* info) OVERRIDE;
Chao-ying Fu7e399fd2014-06-10 18:11:11 -0700530
531 /*
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700532 * @brief generate inline code for fast case of Strng.indexOf.
533 * @param info Call parameters
534 * @param zero_based 'true' if the index into the string is 0.
535 * @returns 'true' if the call was inlined, 'false' if a regular call needs to be
536 * generated.
537 */
538 bool GenInlinedIndexOf(CallInfo* info, bool zero_based);
Mark Mendelle87f9b52014-04-30 14:13:18 -0400539
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700540 /**
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700541 * @brief Used to reserve a range of vector registers.
542 * @see kMirOpReserveVectorRegisters
543 * @param mir The extended MIR for reservation.
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700544 */
545 void ReserveVectorRegisters(MIR* mir);
546
547 /**
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700548 * @brief Used to return a range of vector registers.
549 * @see kMirOpReturnVectorRegisters
550 * @param mir The extended MIR for returning vector regs.
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700551 */
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700552 void ReturnVectorRegisters(MIR* mir);
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700553
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700554 /*
555 * @brief Load 128 bit constant into vector register.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700556 * @param mir The MIR whose opcode is kMirConstVector
557 * @note vA is the TypeSize for the register.
558 * @note vB is the destination XMM register. arg[0..3] are 32 bit constant values.
559 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700560 void GenConst128(MIR* mir);
Mark Mendell4028a6c2014-02-19 20:06:20 -0800561
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700562 /*
563 * @brief MIR to move a vectorized register to another.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700564 * @param mir The MIR whose opcode is kMirConstVector.
565 * @note vA: TypeSize
566 * @note vB: destination
567 * @note vC: source
568 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700569 void GenMoveVector(MIR* mir);
Mark Mendelld65c51a2014-04-29 16:55:20 -0400570
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700571 /*
Yixin Shouf40f8902014-08-14 14:10:32 -0400572 * @brief Packed multiply of units in two vector registers: vB = vB .* @note vC using vA to know
573 * the type of the vector.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700574 * @param mir The MIR whose opcode is kMirConstVector.
575 * @note vA: TypeSize
576 * @note vB: destination and source
577 * @note vC: source
578 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700579 void GenMultiplyVector(MIR* mir);
Mark Mendellfe945782014-05-22 09:52:36 -0400580
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700581 /*
Yixin Shouf40f8902014-08-14 14:10:32 -0400582 * @brief Packed addition of units in two vector registers: vB = vB .+ vC using vA to know the
583 * type of the vector.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700584 * @param mir The MIR whose opcode is kMirConstVector.
585 * @note vA: TypeSize
586 * @note vB: destination and source
587 * @note vC: source
588 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700589 void GenAddVector(MIR* mir);
Mark Mendellfe945782014-05-22 09:52:36 -0400590
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700591 /*
Yixin Shouf40f8902014-08-14 14:10:32 -0400592 * @brief Packed subtraction of units in two vector registers: vB = vB .- vC using vA to know the
593 * type of the vector.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700594 * @param mir The MIR whose opcode is kMirConstVector.
595 * @note vA: TypeSize
596 * @note vB: destination and source
597 * @note vC: source
598 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700599 void GenSubtractVector(MIR* mir);
Mark Mendellfe945782014-05-22 09:52:36 -0400600
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700601 /*
Yixin Shouf40f8902014-08-14 14:10:32 -0400602 * @brief Packed shift left of units in two vector registers: vB = vB .<< vC using vA to know the
603 * type of the vector.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700604 * @param mir The MIR whose opcode is kMirConstVector.
605 * @note vA: TypeSize
606 * @note vB: destination and source
607 * @note vC: immediate
608 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700609 void GenShiftLeftVector(MIR* mir);
Mark Mendellfe945782014-05-22 09:52:36 -0400610
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700611 /*
Yixin Shouf40f8902014-08-14 14:10:32 -0400612 * @brief Packed signed shift right of units in two vector registers: vB = vB .>> vC using vA to
613 * know the type of the vector.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700614 * @param mir The MIR whose opcode is kMirConstVector.
615 * @note vA: TypeSize
616 * @note vB: destination and source
617 * @note vC: immediate
618 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700619 void GenSignedShiftRightVector(MIR* mir);
Mark Mendellfe945782014-05-22 09:52:36 -0400620
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700621 /*
Yixin Shouf40f8902014-08-14 14:10:32 -0400622 * @brief Packed unsigned shift right of units in two vector registers: vB = vB .>>> vC using vA
623 * to know the type of the vector.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700624 * @param mir The MIR whose opcode is kMirConstVector.
625 * @note vA: TypeSize
626 * @note vB: destination and source
627 * @note vC: immediate
628 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700629 void GenUnsignedShiftRightVector(MIR* mir);
Mark Mendellfe945782014-05-22 09:52:36 -0400630
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700631 /*
Yixin Shouf40f8902014-08-14 14:10:32 -0400632 * @brief Packed bitwise and of units in two vector registers: vB = vB .& vC using vA to know the
633 * type of the vector.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700634 * @note vA: TypeSize
635 * @note vB: destination and source
636 * @note vC: source
637 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700638 void GenAndVector(MIR* mir);
Mark Mendellfe945782014-05-22 09:52:36 -0400639
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700640 /*
Yixin Shouf40f8902014-08-14 14:10:32 -0400641 * @brief Packed bitwise or of units in two vector registers: vB = vB .| vC using vA to know the
642 * type of the vector.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700643 * @param mir The MIR whose opcode is kMirConstVector.
644 * @note vA: TypeSize
645 * @note vB: destination and source
646 * @note vC: source
647 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700648 void GenOrVector(MIR* mir);
Mark Mendellfe945782014-05-22 09:52:36 -0400649
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700650 /*
Yixin Shouf40f8902014-08-14 14:10:32 -0400651 * @brief Packed bitwise xor of units in two vector registers: vB = vB .^ vC using vA to know the
652 * type of the vector.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700653 * @param mir The MIR whose opcode is kMirConstVector.
654 * @note vA: TypeSize
655 * @note vB: destination and source
656 * @note vC: source
657 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700658 void GenXorVector(MIR* mir);
Mark Mendellfe945782014-05-22 09:52:36 -0400659
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700660 /*
661 * @brief Reduce a 128-bit packed element into a single VR by taking lower bits
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700662 * @param mir The MIR whose opcode is kMirConstVector.
663 * @details Instruction does a horizontal addition of the packed elements and then adds it to VR.
664 * @note vA: TypeSize
665 * @note vB: destination and source VR (not vector register)
666 * @note vC: source (vector register)
667 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700668 void GenAddReduceVector(MIR* mir);
Mark Mendellfe945782014-05-22 09:52:36 -0400669
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700670 /*
671 * @brief Extract a packed element into a single VR.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700672 * @param mir The MIR whose opcode is kMirConstVector.
673 * @note vA: TypeSize
674 * @note vB: destination VR (not vector register)
675 * @note vC: source (vector register)
676 * @note arg[0]: The index to use for extraction from vector register (which packed element).
677 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700678 void GenReduceVector(MIR* mir);
Mark Mendellfe945782014-05-22 09:52:36 -0400679
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700680 /*
681 * @brief Create a vector value, with all TypeSize values equal to vC
682 * @param bb The basic block in which the MIR is from.
683 * @param mir The MIR whose opcode is kMirConstVector.
684 * @note vA: TypeSize.
685 * @note vB: destination vector register.
686 * @note vC: source VR (not vector register).
687 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700688 void GenSetVector(MIR* mir);
Mark Mendellfe945782014-05-22 09:52:36 -0400689
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700690 /**
691 * @brief Used to generate code for kMirOpPackedArrayGet.
692 * @param bb The basic block of MIR.
693 * @param mir The mir whose opcode is kMirOpPackedArrayGet.
694 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700695 void GenPackedArrayGet(BasicBlock* bb, MIR* mir);
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700696
697 /**
698 * @brief Used to generate code for kMirOpPackedArrayPut.
699 * @param bb The basic block of MIR.
700 * @param mir The mir whose opcode is kMirOpPackedArrayPut.
701 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700702 void GenPackedArrayPut(BasicBlock* bb, MIR* mir);
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700703
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700704 /*
705 * @brief Generate code for a vector opcode.
706 * @param bb The basic block in which the MIR is from.
707 * @param mir The MIR whose opcode is a non-standard opcode.
708 */
709 void GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir);
Mark Mendellfe945782014-05-22 09:52:36 -0400710
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700711 /*
712 * @brief Return the correct x86 opcode for the Dex operation
713 * @param op Dex opcode for the operation
714 * @param loc Register location of the operand
715 * @param is_high_op 'true' if this is an operation on the high word
716 * @param value Immediate value for the operation. Used for byte variants
717 * @returns the correct x86 opcode to perform the operation
718 */
719 X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value);
Mark Mendelld65c51a2014-04-29 16:55:20 -0400720
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700721 /*
722 * @brief Return the correct x86 opcode for the Dex operation
723 * @param op Dex opcode for the operation
724 * @param dest location of the destination. May be register or memory.
725 * @param rhs Location for the rhs of the operation. May be in register or memory.
726 * @param is_high_op 'true' if this is an operation on the high word
727 * @returns the correct x86 opcode to perform the operation
728 * @note at most one location may refer to memory
729 */
730 X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs,
731 bool is_high_op);
Mark Mendelle02d48f2014-01-15 11:19:23 -0800732
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700733 /*
734 * @brief Is this operation a no-op for this opcode and value
735 * @param op Dex opcode for the operation
736 * @param value Immediate value for the operation.
737 * @returns 'true' if the operation will have no effect
738 */
739 bool IsNoOp(Instruction::Code op, int32_t value);
Mark Mendelle02d48f2014-01-15 11:19:23 -0800740
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700741 /**
742 * @brief Calculate magic number and shift for a given divisor
743 * @param divisor divisor number for calculation
744 * @param magic hold calculated magic number
745 * @param shift hold calculated shift
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700746 * @param is_long 'true' if divisor is jlong, 'false' for jint.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700747 */
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700748 void CalculateMagicAndShift(int64_t divisor, int64_t& magic, int& shift, bool is_long);
Mark Mendelle02d48f2014-01-15 11:19:23 -0800749
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700750 /*
751 * @brief Generate an integer div or rem operation.
752 * @param rl_dest Destination Location.
753 * @param rl_src1 Numerator Location.
754 * @param rl_src2 Divisor Location.
755 * @param is_div 'true' if this is a division, 'false' for a remainder.
Razvan A Lupusoru5c5676b2014-09-29 16:42:11 -0700756 * @param flags The instruction optimization flags. It can include information
757 * if exception check can be elided.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700758 */
759 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2,
Razvan A Lupusoru5c5676b2014-09-29 16:42:11 -0700760 bool is_div, int flags);
Mark Mendell2bf31e62014-01-23 12:13:40 -0800761
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700762 /*
763 * @brief Generate an integer div or rem operation by a literal.
764 * @param rl_dest Destination Location.
765 * @param rl_src Numerator Location.
766 * @param lit Divisor.
767 * @param is_div 'true' if this is a division, 'false' for a remainder.
768 */
769 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div);
Mark Mendell2bf31e62014-01-23 12:13:40 -0800770
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700771 /*
772 * Generate code to implement long shift operations.
773 * @param opcode The DEX opcode to specify the shift type.
774 * @param rl_dest The destination.
775 * @param rl_src The value to be shifted.
776 * @param shift_amount How much to shift.
Razvan A Lupusoru5c5676b2014-09-29 16:42:11 -0700777 * @param flags The instruction optimization flags.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700778 * @returns the RegLocation of the result.
779 */
780 RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
Razvan A Lupusoru5c5676b2014-09-29 16:42:11 -0700781 RegLocation rl_src, int shift_amount, int flags);
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700782 /*
783 * Generate an imul of a register by a constant or a better sequence.
784 * @param dest Destination Register.
785 * @param src Source Register.
786 * @param val Constant multiplier.
787 */
788 void GenImulRegImm(RegStorage dest, RegStorage src, int val);
Mark Mendell4708dcd2014-01-22 09:05:18 -0800789
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700790 /*
791 * Generate an imul of a memory location by a constant or a better sequence.
792 * @param dest Destination Register.
793 * @param sreg Symbolic register.
794 * @param displacement Displacement on stack of Symbolic Register.
795 * @param val Constant multiplier.
796 */
797 void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val);
Mark Mendellfeb2b4e2014-01-28 12:59:49 -0800798
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700799 /*
800 * @brief Compare memory to immediate, and branch if condition true.
801 * @param cond The condition code that when true will branch to the target.
802 * @param temp_reg A temporary register that can be used if compare memory is not
803 * supported by the architecture.
804 * @param base_reg The register holding the base address.
805 * @param offset The offset from the base.
806 * @param check_value The immediate to compare to.
Dave Allison69dfe512014-07-11 17:11:58 +0000807 * @param target branch target (or nullptr)
808 * @param compare output for getting LIR for comparison (or nullptr)
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700809 */
810 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
Dave Allison69dfe512014-07-11 17:11:58 +0000811 int offset, int check_value, LIR* target, LIR** compare);
Mark Mendell766e9292014-01-27 07:55:47 -0800812
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700813 void GenRemFP(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, bool is_double);
814
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700815 /*
816 * Can this operation be using core registers without temporaries?
817 * @param rl_lhs Left hand operand.
818 * @param rl_rhs Right hand operand.
819 * @returns 'true' if the operation can proceed without needing temporary regs.
820 */
821 bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs);
Razvan A Lupusoru614c2b42014-01-28 17:05:21 -0800822
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700823 /**
824 * @brief Generates inline code for conversion of long to FP by using x87/
825 * @param rl_dest The destination of the FP.
826 * @param rl_src The source of the long.
827 * @param is_double 'true' if dealing with double, 'false' for float.
828 */
829 virtual void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double);
Mark Mendell67c39c42014-01-31 17:28:00 -0800830
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700831 void GenArrayBoundsCheck(RegStorage index, RegStorage array_base, int32_t len_offset);
832 void GenArrayBoundsCheck(int32_t index, RegStorage array_base, int32_t len_offset);
833
834 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset);
835 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value);
836 LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value);
837 LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset);
838 LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset);
839 void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset);
840 void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset);
841 void OpTlsCmp(ThreadOffset<4> offset, int val);
842 void OpTlsCmp(ThreadOffset<8> offset, int val);
843
844 void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset);
845
Andreas Gampec76c6142014-08-04 16:30:03 -0700846 // Try to do a long multiplication where rl_src2 is a constant. This simplified setup might fail,
847 // in which case false will be returned.
Razvan A Lupusoru5c5676b2014-09-29 16:42:11 -0700848 bool GenMulLongConst(RegLocation rl_dest, RegLocation rl_src1, int64_t val, int flags);
Andreas Gampec76c6142014-08-04 16:30:03 -0700849 void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
Razvan A Lupusoru5c5676b2014-09-29 16:42:11 -0700850 RegLocation rl_src2, int flags);
Andreas Gampec76c6142014-08-04 16:30:03 -0700851 void GenNotLong(RegLocation rl_dest, RegLocation rl_src);
852 void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
853 void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1,
Razvan A Lupusoru5c5676b2014-09-29 16:42:11 -0700854 RegLocation rl_src2, bool is_div, int flags);
Andreas Gampec76c6142014-08-04 16:30:03 -0700855
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700856 void SpillCoreRegs();
857 void UnSpillCoreRegs();
858 void UnSpillFPRegs();
859 void SpillFPRegs();
860
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700861 /*
862 * @brief Perform MIR analysis before compiling method.
863 * @note Invokes Mir2LiR::Materialize after analysis.
864 */
865 void Materialize();
Razvan A Lupusoru614c2b42014-01-28 17:05:21 -0800866
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700867 /*
868 * Mir2Lir's UpdateLoc() looks to see if the Dalvik value is currently live in any temp register
869 * without regard to data type. In practice, this can result in UpdateLoc returning a
870 * location record for a Dalvik float value in a core register, and vis-versa. For targets
871 * which can inexpensively move data between core and float registers, this can often be a win.
872 * However, for x86 this is generally not a win. These variants of UpdateLoc()
873 * take a register class argument - and will return an in-register location record only if
874 * the value is live in a temp register of the correct class. Additionally, if the value is in
875 * a temp register of the wrong register class, it will be clobbered.
876 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700877 RegLocation UpdateLocTyped(RegLocation loc);
878 RegLocation UpdateLocWideTyped(RegLocation loc);
Mark Mendell67c39c42014-01-31 17:28:00 -0800879
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700880 /*
881 * @brief Analyze MIR before generating code, to prepare for the code generation.
882 */
883 void AnalyzeMIR();
buzbee30adc732014-05-09 15:10:18 -0700884
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700885 /*
886 * @brief Analyze one basic block.
887 * @param bb Basic block to analyze.
888 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700889 void AnalyzeBB(BasicBlock* bb);
Mark Mendell67c39c42014-01-31 17:28:00 -0800890
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700891 /*
892 * @brief Analyze one extended MIR instruction
893 * @param opcode MIR instruction opcode.
894 * @param bb Basic block containing instruction.
895 * @param mir Extended instruction to analyze.
896 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700897 void AnalyzeExtendedMIR(int opcode, BasicBlock* bb, MIR* mir);
Mark Mendell67c39c42014-01-31 17:28:00 -0800898
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700899 /*
900 * @brief Analyze one MIR instruction
901 * @param opcode MIR instruction opcode.
902 * @param bb Basic block containing instruction.
903 * @param mir Instruction to analyze.
904 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700905 virtual void AnalyzeMIR(int opcode, BasicBlock* bb, MIR* mir);
Mark Mendell67c39c42014-01-31 17:28:00 -0800906
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700907 /*
908 * @brief Analyze one MIR float/double instruction
909 * @param opcode MIR instruction opcode.
910 * @param bb Basic block containing instruction.
911 * @param mir Instruction to analyze.
912 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700913 virtual void AnalyzeFPInstruction(int opcode, BasicBlock* bb, MIR* mir);
Mark Mendell67c39c42014-01-31 17:28:00 -0800914
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700915 /*
916 * @brief Analyze one use of a double operand.
917 * @param rl_use Double RegLocation for the operand.
918 */
919 void AnalyzeDoubleUse(RegLocation rl_use);
Mark Mendell67c39c42014-01-31 17:28:00 -0800920
Yixin Shou7071c8d2014-03-05 06:07:48 -0500921 /*
922 * @brief Analyze one invoke-static MIR instruction
923 * @param opcode MIR instruction opcode.
924 * @param bb Basic block containing instruction.
925 * @param mir Instruction to analyze.
926 */
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700927 void AnalyzeInvokeStatic(int opcode, BasicBlock* bb, MIR* mir);
Yixin Shou7071c8d2014-03-05 06:07:48 -0500928
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700929 // Information derived from analysis of MIR
Dmitry Petrochenko9ee801f2014-05-12 11:31:37 +0700930
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700931 // The compiler temporary for the code address of the method.
932 CompilerTemp *base_of_code_;
Mark Mendell67c39c42014-01-31 17:28:00 -0800933
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700934 // Have we decided to compute a ptr to code and store in temporary VR?
935 bool store_method_addr_;
Mark Mendell55d0eac2014-02-06 11:02:52 -0800936
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700937 // Have we used the stored method address?
938 bool store_method_addr_used_;
Mark Mendell67c39c42014-01-31 17:28:00 -0800939
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700940 // Instructions to remove if we didn't use the stored method address.
941 LIR* setup_method_address_[2];
Mark Mendell55d0eac2014-02-06 11:02:52 -0800942
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700943 // Instructions needing patching with Method* values.
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100944 ArenaVector<LIR*> method_address_insns_;
Mark Mendell55d0eac2014-02-06 11:02:52 -0800945
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700946 // Instructions needing patching with Class Type* values.
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100947 ArenaVector<LIR*> class_type_address_insns_;
Mark Mendell55d0eac2014-02-06 11:02:52 -0800948
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700949 // Instructions needing patching with PC relative code addresses.
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100950 ArenaVector<LIR*> call_method_insns_;
Mark Mendell55d0eac2014-02-06 11:02:52 -0800951
Vladimir Markodc56cc52015-03-27 18:18:36 +0000952 // Instructions needing patching with PC relative code addresses.
953 ArenaVector<LIR*> dex_cache_access_insns_;
954
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700955 // The list of const vector literals.
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700956 LIR* const_vectors_;
Mark Mendelld65c51a2014-04-29 16:55:20 -0400957
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700958 /*
959 * @brief Search for a matching vector literal
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700960 * @param constants An array of size 4 which contains all of 32-bit constants.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700961 * @returns pointer to matching LIR constant, or nullptr if not found.
962 */
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700963 LIR* ScanVectorLiteral(int32_t* constants);
Mark Mendelld65c51a2014-04-29 16:55:20 -0400964
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700965 /*
966 * @brief Add a constant vector literal
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700967 * @param constants An array of size 4 which contains all of 32-bit constants.
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700968 */
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700969 LIR* AddVectorLiteral(int32_t* constants);
Mark Mendelld65c51a2014-04-29 16:55:20 -0400970
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700971 bool WideGPRsAreAliases() const OVERRIDE {
Serguei Katkov59a42af2014-07-05 00:55:46 +0700972 return cu_->target64; // On 64b, we have 64b GPRs.
973 }
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700974
975 bool WideFPRsAreAliases() const OVERRIDE {
Serguei Katkov59a42af2014-07-05 00:55:46 +0700976 return true; // xmm registers have 64b views even on x86.
977 }
978
Alexei Zavjalov6bbf0962014-07-15 02:19:41 +0700979 /*
980 * @brief Dump a RegLocation using printf
981 * @param loc Register location to dump
982 */
983 static void DumpRegLocation(RegLocation loc);
984
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700985 private:
Yixin Shou8c914c02014-07-28 14:17:09 -0400986 void SwapBits(RegStorage result_reg, int shift, int32_t value);
987 void SwapBits64(RegStorage result_reg, int shift, int64_t value);
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700988
Vladimir Markodc56cc52015-03-27 18:18:36 +0000989 static int X86NextSDCallInsn(CompilationUnit* cu, CallInfo* info,
990 int state, const MethodReference& target_method,
991 uint32_t,
992 uintptr_t direct_code, uintptr_t direct_method,
993 InvokeType type);
994
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700995 static const X86EncodingMap EncodingMap[kX86Last];
996
997 friend std::ostream& operator<<(std::ostream& os, const X86OpCode& rhs);
998
999 DISALLOW_COPY_AND_ASSIGN(X86Mir2Lir);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001000};
1001
1002} // namespace art
1003
Brian Carlstromfc0e3212013-07-17 14:40:12 -07001004#endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_