Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 17 | #ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ |
| 18 | #define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 19 | |
Andreas Gampe | 0b9203e | 2015-01-22 20:39:27 -0800 | [diff] [blame] | 20 | #include "base/logging.h" |
| 21 | #include "dex/compiler_ir.h" |
| 22 | #include "dex/mir_graph.h" |
Andreas Gampe | 53c913b | 2014-08-12 23:19:23 -0700 | [diff] [blame] | 23 | #include "dex/quick/mir_to_lir.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 24 | #include "x86_lir.h" |
| 25 | |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 26 | #include <map> |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 27 | #include <vector> |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 28 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 29 | namespace art { |
| 30 | |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 31 | class X86Mir2Lir : public Mir2Lir { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 32 | protected: |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 33 | class InToRegStorageX86_64Mapper : public InToRegStorageMapper { |
| 34 | public: |
Serguei Katkov | 717a3e4 | 2014-11-13 17:19:42 +0600 | [diff] [blame] | 35 | explicit InToRegStorageX86_64Mapper(Mir2Lir* m2l) |
| 36 | : m2l_(m2l), cur_core_reg_(0), cur_fp_reg_(0) {} |
| 37 | virtual RegStorage GetNextReg(ShortyArg arg); |
| 38 | virtual void Reset() OVERRIDE { |
| 39 | cur_core_reg_ = 0; |
| 40 | cur_fp_reg_ = 0; |
| 41 | } |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 42 | protected: |
Serguei Katkov | 717a3e4 | 2014-11-13 17:19:42 +0600 | [diff] [blame] | 43 | Mir2Lir* m2l_; |
Serguei Katkov | 717a3e4 | 2014-11-13 17:19:42 +0600 | [diff] [blame] | 44 | size_t cur_core_reg_; |
| 45 | size_t cur_fp_reg_; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 46 | }; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 47 | |
Mark P Mendell | 966c3ae | 2015-01-27 15:45:27 +0000 | [diff] [blame] | 48 | class InToRegStorageX86Mapper : public InToRegStorageX86_64Mapper { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 49 | public: |
Mark P Mendell | 966c3ae | 2015-01-27 15:45:27 +0000 | [diff] [blame] | 50 | explicit InToRegStorageX86Mapper(Mir2Lir* m2l) |
| 51 | : InToRegStorageX86_64Mapper(m2l) { } |
Serguei Katkov | 717a3e4 | 2014-11-13 17:19:42 +0600 | [diff] [blame] | 52 | virtual RegStorage GetNextReg(ShortyArg arg); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 53 | }; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 54 | |
Serguei Katkov | 717a3e4 | 2014-11-13 17:19:42 +0600 | [diff] [blame] | 55 | InToRegStorageX86_64Mapper in_to_reg_storage_x86_64_mapper_; |
| 56 | InToRegStorageX86Mapper in_to_reg_storage_x86_mapper_; |
| 57 | InToRegStorageMapper* GetResetedInToRegStorageMapper() OVERRIDE { |
| 58 | InToRegStorageMapper* res; |
| 59 | if (cu_->target64) { |
| 60 | res = &in_to_reg_storage_x86_64_mapper_; |
| 61 | } else { |
| 62 | res = &in_to_reg_storage_x86_mapper_; |
| 63 | } |
| 64 | res->Reset(); |
| 65 | return res; |
| 66 | } |
| 67 | |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 68 | class ExplicitTempRegisterLock { |
| 69 | public: |
| 70 | ExplicitTempRegisterLock(X86Mir2Lir* mir_to_lir, int n_regs, ...); |
| 71 | ~ExplicitTempRegisterLock(); |
| 72 | protected: |
| 73 | std::vector<RegStorage> temp_regs_; |
| 74 | X86Mir2Lir* const mir_to_lir_; |
| 75 | }; |
| 76 | |
Serguei Katkov | 717a3e4 | 2014-11-13 17:19:42 +0600 | [diff] [blame] | 77 | virtual int GenDalvikArgsBulkCopy(CallInfo* info, int first, int count) OVERRIDE; |
| 78 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 79 | public: |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 80 | X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 81 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 82 | // Required for target - codegen helpers. |
| 83 | bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 84 | RegLocation rl_dest, int lit) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 85 | bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; |
Ningsheng Jian | 675e09b | 2014-10-23 13:48:36 +0800 | [diff] [blame] | 86 | void GenMultiplyByConstantFloat(RegLocation rl_dest, RegLocation rl_src1, |
| 87 | int32_t constant) OVERRIDE; |
| 88 | void GenMultiplyByConstantDouble(RegLocation rl_dest, RegLocation rl_src1, |
| 89 | int64_t constant) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 90 | LIR* CheckSuspendUsingLoad() OVERRIDE; |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 91 | RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 92 | LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 93 | OpSize size, VolatileKind is_volatile) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 94 | LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 95 | OpSize size) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 96 | LIR* LoadConstantNoClobber(RegStorage r_dest, int value); |
| 97 | LIR* LoadConstantWide(RegStorage r_dest, int64_t value); |
Yevgeny Rouban | 6af8206 | 2014-11-26 18:11:54 +0600 | [diff] [blame] | 98 | void GenLongToInt(RegLocation rl_dest, RegLocation rl_src); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 99 | LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 100 | OpSize size, VolatileKind is_volatile) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 101 | LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, |
| 102 | OpSize size) OVERRIDE; |
Vladimir Marko | bf535be | 2014-11-19 18:52:35 +0000 | [diff] [blame] | 103 | |
| 104 | /// @copydoc Mir2Lir::UnconditionallyMarkGCCard(RegStorage) |
| 105 | void UnconditionallyMarkGCCard(RegStorage tgt_addr_reg) OVERRIDE; |
| 106 | |
Vladimir Marko | dc56cc5 | 2015-03-27 18:18:36 +0000 | [diff] [blame] | 107 | bool CanUseOpPcRelDexCacheArrayLoad() const OVERRIDE; |
| 108 | void OpPcRelDexCacheArrayLoad(const DexFile* dex_file, int offset, RegStorage r_dest) OVERRIDE; |
| 109 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 110 | void GenImplicitNullCheck(RegStorage reg, int opt_flags) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 111 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 112 | // Required for target - register utilities. |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 113 | RegStorage TargetReg(SpecialTargetRegister reg) OVERRIDE; |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 114 | RegStorage TargetReg(SpecialTargetRegister symbolic_reg, WideKind wide_kind) OVERRIDE { |
| 115 | if (wide_kind == kWide) { |
| 116 | if (cu_->target64) { |
| 117 | return As64BitReg(TargetReg32(symbolic_reg)); |
| 118 | } else { |
Mark P Mendell | 966c3ae | 2015-01-27 15:45:27 +0000 | [diff] [blame] | 119 | if (symbolic_reg >= kFArg0 && symbolic_reg <= kFArg3) { |
| 120 | // We want an XMM, not a pair. |
| 121 | return As64BitReg(TargetReg32(symbolic_reg)); |
| 122 | } |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 123 | // x86: construct a pair. |
| 124 | DCHECK((kArg0 <= symbolic_reg && symbolic_reg < kArg3) || |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 125 | (kRet0 == symbolic_reg)); |
| 126 | return RegStorage::MakeRegPair(TargetReg32(symbolic_reg), |
| 127 | TargetReg32(static_cast<SpecialTargetRegister>(symbolic_reg + 1))); |
| 128 | } |
| 129 | } else if (wide_kind == kRef && cu_->target64) { |
| 130 | return As64BitReg(TargetReg32(symbolic_reg)); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 131 | } else { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 132 | return TargetReg32(symbolic_reg); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 133 | } |
| 134 | } |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 135 | RegStorage TargetPtrReg(SpecialTargetRegister symbolic_reg) OVERRIDE { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 136 | return TargetReg(symbolic_reg, cu_->target64 ? kWide : kNotWide); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 137 | } |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 138 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 139 | RegLocation GetReturnAlt() OVERRIDE; |
| 140 | RegLocation GetReturnWideAlt() OVERRIDE; |
| 141 | RegLocation LocCReturn() OVERRIDE; |
| 142 | RegLocation LocCReturnRef() OVERRIDE; |
| 143 | RegLocation LocCReturnDouble() OVERRIDE; |
| 144 | RegLocation LocCReturnFloat() OVERRIDE; |
| 145 | RegLocation LocCReturnWide() OVERRIDE; |
| 146 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 147 | ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 148 | void AdjustSpillMask() OVERRIDE; |
| 149 | void ClobberCallerSave() OVERRIDE; |
| 150 | void FreeCallTemps() OVERRIDE; |
| 151 | void LockCallTemps() OVERRIDE; |
| 152 | |
| 153 | void CompilerInitializeRegAlloc() OVERRIDE; |
| 154 | int VectorRegisterSize() OVERRIDE; |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 155 | int NumReservableVectorRegisters(bool long_or_fp) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 156 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 157 | // Required for target - miscellaneous. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 158 | void AssembleLIR() OVERRIDE; |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 159 | void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; |
| 160 | void SetupTargetResourceMasks(LIR* lir, uint64_t flags, |
| 161 | ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 162 | const char* GetTargetInstFmt(int opcode) OVERRIDE; |
| 163 | const char* GetTargetInstName(int opcode) OVERRIDE; |
| 164 | std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) OVERRIDE; |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 165 | ResourceMask GetPCUseDefEncoding() const OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 166 | uint64_t GetTargetInstFlags(int opcode) OVERRIDE; |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 167 | size_t GetInsnSize(LIR* lir) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 168 | bool IsUnconditionalBranch(LIR* lir) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 169 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 170 | // Get the register class for load/store of a field. |
| 171 | RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 172 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 173 | // Required for target - Dalvik-level generators. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 174 | void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 175 | RegLocation rl_dest, int scale) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 176 | void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 177 | RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) OVERRIDE; |
| 178 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 179 | void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 180 | RegLocation rl_src2) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 181 | void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 182 | RegLocation rl_src2) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 183 | void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 184 | RegLocation rl_src2) OVERRIDE; |
| 185 | void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) OVERRIDE; |
| 186 | |
| 187 | bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) OVERRIDE; |
| 188 | bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) OVERRIDE; |
| 189 | bool GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double) OVERRIDE; |
Yixin Shou | 8c914c0 | 2014-07-28 14:17:09 -0400 | [diff] [blame] | 190 | bool GenInlinedReverseBits(CallInfo* info, OpSize size) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 191 | bool GenInlinedSqrt(CallInfo* info) OVERRIDE; |
Yixin Shou | 7071c8d | 2014-03-05 06:07:48 -0500 | [diff] [blame] | 192 | bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE; |
| 193 | bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 194 | bool GenInlinedPeek(CallInfo* info, OpSize size) OVERRIDE; |
| 195 | bool GenInlinedPoke(CallInfo* info, OpSize size) OVERRIDE; |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 196 | bool GenInlinedCharAt(CallInfo* info) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 197 | |
| 198 | // Long instructions. |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 199 | void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 200 | RegLocation rl_src2, int flags) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 201 | void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 202 | RegLocation rl_src2, int flags) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 203 | void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 204 | RegLocation rl_src1, RegLocation rl_shift, int flags) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 205 | void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) OVERRIDE; |
| 206 | void GenIntToLong(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; |
| 207 | void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 208 | RegLocation rl_src1, RegLocation rl_shift) OVERRIDE; |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 209 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 210 | /* |
| 211 | * @brief Generate a two address long operation with a constant value |
| 212 | * @param rl_dest location of result |
| 213 | * @param rl_src constant source operand |
| 214 | * @param op Opcode to be generated |
| 215 | * @return success or not |
| 216 | */ |
| 217 | bool GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 218 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 219 | /* |
| 220 | * @brief Generate a three address long operation with a constant value |
| 221 | * @param rl_dest location of result |
| 222 | * @param rl_src1 source operand |
| 223 | * @param rl_src2 constant source operand |
| 224 | * @param op Opcode to be generated |
| 225 | * @return success or not |
| 226 | */ |
| 227 | bool GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 228 | Instruction::Code op); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 229 | /** |
| 230 | * @brief Generate a long arithmetic operation. |
| 231 | * @param rl_dest The destination. |
| 232 | * @param rl_src1 First operand. |
| 233 | * @param rl_src2 Second operand. |
| 234 | * @param op The DEX opcode for the operation. |
| 235 | * @param is_commutative The sources can be swapped if needed. |
| 236 | */ |
| 237 | virtual void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 238 | Instruction::Code op, bool is_commutative); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 239 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 240 | /** |
| 241 | * @brief Generate a two operand long arithmetic operation. |
| 242 | * @param rl_dest The destination. |
| 243 | * @param rl_src Second operand. |
| 244 | * @param op The DEX opcode for the operation. |
| 245 | */ |
| 246 | void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 247 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 248 | /** |
| 249 | * @brief Generate a long operation. |
| 250 | * @param rl_dest The destination. Must be in a register |
| 251 | * @param rl_src The other operand. May be in a register or in memory. |
| 252 | * @param op The DEX opcode for the operation. |
| 253 | */ |
| 254 | virtual void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 255 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 256 | |
| 257 | // TODO: collapse reg_lo, reg_hi |
| 258 | RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div) |
| 259 | OVERRIDE; |
| 260 | RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div) OVERRIDE; |
| 261 | void GenDivZeroCheckWide(RegStorage reg) OVERRIDE; |
| 262 | void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) OVERRIDE; |
| 263 | void GenExitSequence() OVERRIDE; |
| 264 | void GenSpecialExitSequence() OVERRIDE; |
Vladimir Marko | 6ce3eba | 2015-02-16 13:05:59 +0000 | [diff] [blame] | 265 | void GenSpecialEntryForSuspend() OVERRIDE; |
| 266 | void GenSpecialExitForSuspend() OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 267 | void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) OVERRIDE; |
| 268 | void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) OVERRIDE; |
| 269 | void GenSelect(BasicBlock* bb, MIR* mir) OVERRIDE; |
| 270 | void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, |
| 271 | int32_t true_val, int32_t false_val, RegStorage rs_dest, |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 272 | RegisterClass dest_reg_class) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 273 | bool GenMemBarrier(MemBarrierKind barrier_kind) OVERRIDE; |
| 274 | void GenMoveException(RegLocation rl_dest) OVERRIDE; |
| 275 | void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, |
| 276 | int first_bit, int second_bit) OVERRIDE; |
| 277 | void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; |
| 278 | void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; |
Andreas Gampe | 48971b3 | 2014-08-06 10:09:01 -0700 | [diff] [blame] | 279 | void GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE; |
| 280 | void GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 281 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 282 | /** |
| 283 | * @brief Implement instanceof a final class with x86 specific code. |
| 284 | * @param use_declaring_class 'true' if we can use the class itself. |
| 285 | * @param type_idx Type index to use if use_declaring_class is 'false'. |
| 286 | * @param rl_dest Result to be set to 0 or 1. |
| 287 | * @param rl_src Object to be tested. |
| 288 | */ |
| 289 | void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 290 | RegLocation rl_src) OVERRIDE; |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 291 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 292 | // Single operation generators. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 293 | LIR* OpUnconditionalBranch(LIR* target) OVERRIDE; |
| 294 | LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE; |
| 295 | LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE; |
| 296 | LIR* OpCondBranch(ConditionCode cc, LIR* target) OVERRIDE; |
| 297 | LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE; |
| 298 | LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE; |
| 299 | LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE; |
| 300 | void OpEndIT(LIR* it) OVERRIDE; |
| 301 | LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE; |
Vladimir Marko | f6737f7 | 2015-03-23 17:05:14 +0000 | [diff] [blame] | 302 | void OpPcRelLoad(RegStorage reg, LIR* target) OVERRIDE; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 303 | LIR* OpReg(OpKind op, RegStorage r_dest_src) OVERRIDE; |
| 304 | void OpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE; |
| 305 | LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) OVERRIDE; |
| 306 | LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) OVERRIDE; |
| 307 | LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) OVERRIDE; |
| 308 | LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) OVERRIDE; |
| 309 | LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE; |
| 310 | LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE; |
| 311 | LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) OVERRIDE; |
| 312 | LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE; |
| 313 | LIR* OpTestSuspend(LIR* target) OVERRIDE; |
| 314 | LIR* OpVldm(RegStorage r_base, int count) OVERRIDE; |
| 315 | LIR* OpVstm(RegStorage r_base, int count) OVERRIDE; |
| 316 | void OpRegCopyWide(RegStorage dest, RegStorage src) OVERRIDE; |
| 317 | bool GenInlinedCurrentThread(CallInfo* info) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 318 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 319 | bool InexpensiveConstantInt(int32_t value) OVERRIDE; |
| 320 | bool InexpensiveConstantFloat(int32_t value) OVERRIDE; |
| 321 | bool InexpensiveConstantLong(int64_t value) OVERRIDE; |
| 322 | bool InexpensiveConstantDouble(int64_t value) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 323 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 324 | /* |
| 325 | * @brief Should try to optimize for two address instructions? |
| 326 | * @return true if we try to avoid generating three operand instructions. |
| 327 | */ |
| 328 | virtual bool GenerateTwoOperandInstructions() const { return true; } |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 329 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 330 | /* |
| 331 | * @brief x86 specific codegen for int operations. |
| 332 | * @param opcode Operation to perform. |
| 333 | * @param rl_dest Destination for the result. |
| 334 | * @param rl_lhs Left hand operand. |
| 335 | * @param rl_rhs Right hand operand. |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 336 | * @param flags The instruction optimization flags. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 337 | */ |
| 338 | void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 339 | RegLocation rl_rhs, int flags) OVERRIDE; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 340 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 341 | /* |
| 342 | * @brief Load the Method* of a dex method into the register. |
| 343 | * @param target_method The MethodReference of the method to be invoked. |
| 344 | * @param type How the method will be invoked. |
| 345 | * @param register that will contain the code address. |
| 346 | * @note register will be passed to TargetReg to get physical register. |
| 347 | */ |
| 348 | void LoadMethodAddress(const MethodReference& target_method, InvokeType type, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 349 | SpecialTargetRegister symbolic_reg) OVERRIDE; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 350 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 351 | /* |
| 352 | * @brief Load the Class* of a Dex Class type into the register. |
Fred Shih | e7f82e2 | 2014-08-06 10:46:37 -0700 | [diff] [blame] | 353 | * @param dex DexFile that contains the class type. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 354 | * @param type How the method will be invoked. |
| 355 | * @param register that will contain the code address. |
| 356 | * @note register will be passed to TargetReg to get physical register. |
| 357 | */ |
Fred Shih | e7f82e2 | 2014-08-06 10:46:37 -0700 | [diff] [blame] | 358 | void LoadClassType(const DexFile& dex_file, uint32_t type_idx, |
| 359 | SpecialTargetRegister symbolic_reg) OVERRIDE; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 360 | |
Vladimir Marko | f4da675 | 2014-08-01 19:04:18 +0100 | [diff] [blame] | 361 | NextCallInsn GetNextSDCallInsn() OVERRIDE; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 362 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 363 | /* |
| 364 | * @brief Generate a relative call to the method that will be patched at link time. |
| 365 | * @param target_method The MethodReference of the method to be invoked. |
| 366 | * @param type How the method will be invoked. |
| 367 | * @returns Call instruction |
| 368 | */ |
Vladimir Marko | f4da675 | 2014-08-01 19:04:18 +0100 | [diff] [blame] | 369 | LIR* CallWithLinkerFixup(const MethodReference& target_method, InvokeType type); |
| 370 | |
| 371 | /* |
| 372 | * @brief Generate the actual call insn based on the method info. |
| 373 | * @param method_info the lowering info for the method call. |
| 374 | * @returns Call instruction |
| 375 | */ |
| 376 | LIR* GenCallInsn(const MirMethodLoweringInfo& method_info) OVERRIDE; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 377 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 378 | /* |
| 379 | * @brief Handle x86 specific literals |
| 380 | */ |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 381 | void InstallLiteralPools() OVERRIDE; |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 382 | |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 383 | LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE; |
| 384 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 385 | protected: |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 386 | RegStorage TargetReg32(SpecialTargetRegister reg) const; |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 387 | // Casting of RegStorage |
| 388 | RegStorage As32BitReg(RegStorage reg) { |
| 389 | DCHECK(!reg.IsPair()); |
| 390 | if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { |
| 391 | if (kFailOnSizeError) { |
| 392 | LOG(FATAL) << "Expected 64b register " << reg.GetReg(); |
| 393 | } else { |
| 394 | LOG(WARNING) << "Expected 64b register " << reg.GetReg(); |
| 395 | return reg; |
| 396 | } |
| 397 | } |
| 398 | RegStorage ret_val = RegStorage(RegStorage::k32BitSolo, |
| 399 | reg.GetRawBits() & RegStorage::kRegTypeMask); |
| 400 | DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k32SoloStorageMask) |
| 401 | ->GetReg().GetReg(), |
| 402 | ret_val.GetReg()); |
| 403 | return ret_val; |
| 404 | } |
| 405 | |
| 406 | RegStorage As64BitReg(RegStorage reg) { |
| 407 | DCHECK(!reg.IsPair()); |
| 408 | if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { |
| 409 | if (kFailOnSizeError) { |
| 410 | LOG(FATAL) << "Expected 32b register " << reg.GetReg(); |
| 411 | } else { |
| 412 | LOG(WARNING) << "Expected 32b register " << reg.GetReg(); |
| 413 | return reg; |
| 414 | } |
| 415 | } |
| 416 | RegStorage ret_val = RegStorage(RegStorage::k64BitSolo, |
| 417 | reg.GetRawBits() & RegStorage::kRegTypeMask); |
| 418 | DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k64SoloStorageMask) |
| 419 | ->GetReg().GetReg(), |
| 420 | ret_val.GetReg()); |
| 421 | return ret_val; |
| 422 | } |
| 423 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 424 | LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, |
| 425 | RegStorage r_dest, OpSize size); |
| 426 | LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, |
Jean Christophe Beyler | b5bce7c | 2014-07-25 12:32:18 -0700 | [diff] [blame] | 427 | RegStorage r_src, OpSize size, int opt_flags = 0); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 428 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 429 | int AssignInsnOffsets(); |
| 430 | void AssignOffsets(); |
| 431 | AssemblerStatus AssembleInstructions(CodeOffset start_addr); |
| 432 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 433 | size_t ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 434 | int32_t raw_base, int32_t displacement); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 435 | void CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg); |
| 436 | void EmitPrefix(const X86EncodingMap* entry, |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 437 | int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 438 | void EmitOpcode(const X86EncodingMap* entry); |
| 439 | void EmitPrefixAndOpcode(const X86EncodingMap* entry, |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 440 | int32_t reg_r, int32_t reg_x, int32_t reg_b); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 441 | void EmitDisp(uint8_t base, int32_t disp); |
| 442 | void EmitModrmThread(uint8_t reg_or_opcode); |
| 443 | void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp); |
| 444 | void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, |
| 445 | int32_t disp); |
| 446 | void EmitImm(const X86EncodingMap* entry, int64_t imm); |
| 447 | void EmitNullary(const X86EncodingMap* entry); |
| 448 | void EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg); |
| 449 | void EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg); |
| 450 | void EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); |
| 451 | void EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, |
| 452 | int32_t disp); |
| 453 | void EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg); |
| 454 | void EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t disp); |
| 455 | void EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, |
| 456 | int32_t raw_index, int scale, int32_t disp); |
| 457 | void EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, |
| 458 | int32_t disp, int32_t raw_reg); |
| 459 | void EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); |
| 460 | void EmitArrayImm(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, |
| 461 | int32_t raw_disp, int32_t imm); |
| 462 | void EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp); |
| 463 | void EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2); |
| 464 | void EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t imm); |
| 465 | void EmitRegMemImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, |
| 466 | int32_t imm); |
| 467 | void EmitMemRegImm(const X86EncodingMap* entry, int32_t base, int32_t disp, int32_t raw_reg1, |
| 468 | int32_t imm); |
| 469 | void EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); |
| 470 | void EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm); |
| 471 | void EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm); |
| 472 | void EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); |
| 473 | void EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl); |
| 474 | void EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_cl); |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 475 | void EmitShiftRegRegCl(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, |
| 476 | int32_t raw_cl); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 477 | void EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); |
| 478 | void EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc); |
| 479 | void EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t cc); |
| 480 | void EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t cc); |
| 481 | void EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, |
| 482 | int32_t cc); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 483 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 484 | void EmitJmp(const X86EncodingMap* entry, int32_t rel); |
| 485 | void EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc); |
| 486 | void EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); |
| 487 | void EmitCallImmediate(const X86EncodingMap* entry, int32_t disp); |
| 488 | void EmitCallThread(const X86EncodingMap* entry, int32_t disp); |
| 489 | void EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table, |
| 490 | int32_t raw_index, int scale, int32_t table_or_disp); |
| 491 | void EmitMacro(const X86EncodingMap* entry, int32_t raw_reg, int32_t offset); |
| 492 | void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir); |
| 493 | void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, |
| 494 | int64_t val, ConditionCode ccode); |
| 495 | void GenConstWide(RegLocation rl_dest, int64_t value); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 496 | void GenMultiplyVectorSignedByte(RegStorage rs_dest_src1, RegStorage rs_src2); |
| 497 | void GenMultiplyVectorLong(RegStorage rs_dest_src1, RegStorage rs_src2); |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 498 | void GenShiftByteVector(MIR* mir); |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 499 | void AndMaskVectorRegister(RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, |
| 500 | uint32_t m4); |
| 501 | void MaskVectorRegister(X86OpCode opcode, RegStorage rs_src1, uint32_t m1, uint32_t m2, |
| 502 | uint32_t m3, uint32_t m4); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 503 | void AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir); |
Mark Mendell | 0a1174e | 2014-09-11 14:51:02 -0400 | [diff] [blame] | 504 | virtual void LoadVectorRegister(RegStorage rs_dest, RegStorage rs_src, OpSize opsize, |
| 505 | int op_mov); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 506 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 507 | static bool ProvidesFullMemoryBarrier(X86OpCode opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 508 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 509 | /* |
| 510 | * @brief Ensure that a temporary register is byte addressable. |
| 511 | * @returns a temporary guarenteed to be byte addressable. |
| 512 | */ |
| 513 | virtual RegStorage AllocateByteRegister(); |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 514 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 515 | /* |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 516 | * @brief Use a wide temporary as a 128-bit register |
| 517 | * @returns a 128-bit temporary register. |
| 518 | */ |
| 519 | virtual RegStorage Get128BitRegister(RegStorage reg); |
| 520 | |
| 521 | /* |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 522 | * @brief Check if a register is byte addressable. |
| 523 | * @returns true if a register is byte addressable. |
| 524 | */ |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 525 | bool IsByteRegister(RegStorage reg) const; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 526 | |
| 527 | void GenDivRemLongLit(RegLocation rl_dest, RegLocation rl_src, int64_t imm, bool is_div); |
| 528 | |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 529 | bool GenInlinedArrayCopyCharArray(CallInfo* info) OVERRIDE; |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 530 | |
| 531 | /* |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 532 | * @brief generate inline code for fast case of Strng.indexOf. |
| 533 | * @param info Call parameters |
| 534 | * @param zero_based 'true' if the index into the string is 0. |
| 535 | * @returns 'true' if the call was inlined, 'false' if a regular call needs to be |
| 536 | * generated. |
| 537 | */ |
| 538 | bool GenInlinedIndexOf(CallInfo* info, bool zero_based); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 539 | |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 540 | /** |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 541 | * @brief Used to reserve a range of vector registers. |
| 542 | * @see kMirOpReserveVectorRegisters |
| 543 | * @param mir The extended MIR for reservation. |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 544 | */ |
| 545 | void ReserveVectorRegisters(MIR* mir); |
| 546 | |
| 547 | /** |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 548 | * @brief Used to return a range of vector registers. |
| 549 | * @see kMirOpReturnVectorRegisters |
| 550 | * @param mir The extended MIR for returning vector regs. |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 551 | */ |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 552 | void ReturnVectorRegisters(MIR* mir); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 553 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 554 | /* |
| 555 | * @brief Load 128 bit constant into vector register. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 556 | * @param mir The MIR whose opcode is kMirConstVector |
| 557 | * @note vA is the TypeSize for the register. |
| 558 | * @note vB is the destination XMM register. arg[0..3] are 32 bit constant values. |
| 559 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 560 | void GenConst128(MIR* mir); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 561 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 562 | /* |
| 563 | * @brief MIR to move a vectorized register to another. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 564 | * @param mir The MIR whose opcode is kMirConstVector. |
| 565 | * @note vA: TypeSize |
| 566 | * @note vB: destination |
| 567 | * @note vC: source |
| 568 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 569 | void GenMoveVector(MIR* mir); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 570 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 571 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 572 | * @brief Packed multiply of units in two vector registers: vB = vB .* @note vC using vA to know |
| 573 | * the type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 574 | * @param mir The MIR whose opcode is kMirConstVector. |
| 575 | * @note vA: TypeSize |
| 576 | * @note vB: destination and source |
| 577 | * @note vC: source |
| 578 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 579 | void GenMultiplyVector(MIR* mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 580 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 581 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 582 | * @brief Packed addition of units in two vector registers: vB = vB .+ vC using vA to know the |
| 583 | * type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 584 | * @param mir The MIR whose opcode is kMirConstVector. |
| 585 | * @note vA: TypeSize |
| 586 | * @note vB: destination and source |
| 587 | * @note vC: source |
| 588 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 589 | void GenAddVector(MIR* mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 590 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 591 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 592 | * @brief Packed subtraction of units in two vector registers: vB = vB .- vC using vA to know the |
| 593 | * type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 594 | * @param mir The MIR whose opcode is kMirConstVector. |
| 595 | * @note vA: TypeSize |
| 596 | * @note vB: destination and source |
| 597 | * @note vC: source |
| 598 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 599 | void GenSubtractVector(MIR* mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 600 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 601 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 602 | * @brief Packed shift left of units in two vector registers: vB = vB .<< vC using vA to know the |
| 603 | * type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 604 | * @param mir The MIR whose opcode is kMirConstVector. |
| 605 | * @note vA: TypeSize |
| 606 | * @note vB: destination and source |
| 607 | * @note vC: immediate |
| 608 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 609 | void GenShiftLeftVector(MIR* mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 610 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 611 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 612 | * @brief Packed signed shift right of units in two vector registers: vB = vB .>> vC using vA to |
| 613 | * know the type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 614 | * @param mir The MIR whose opcode is kMirConstVector. |
| 615 | * @note vA: TypeSize |
| 616 | * @note vB: destination and source |
| 617 | * @note vC: immediate |
| 618 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 619 | void GenSignedShiftRightVector(MIR* mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 620 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 621 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 622 | * @brief Packed unsigned shift right of units in two vector registers: vB = vB .>>> vC using vA |
| 623 | * to know the type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 624 | * @param mir The MIR whose opcode is kMirConstVector. |
| 625 | * @note vA: TypeSize |
| 626 | * @note vB: destination and source |
| 627 | * @note vC: immediate |
| 628 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 629 | void GenUnsignedShiftRightVector(MIR* mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 630 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 631 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 632 | * @brief Packed bitwise and of units in two vector registers: vB = vB .& vC using vA to know the |
| 633 | * type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 634 | * @note vA: TypeSize |
| 635 | * @note vB: destination and source |
| 636 | * @note vC: source |
| 637 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 638 | void GenAndVector(MIR* mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 639 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 640 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 641 | * @brief Packed bitwise or of units in two vector registers: vB = vB .| vC using vA to know the |
| 642 | * type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 643 | * @param mir The MIR whose opcode is kMirConstVector. |
| 644 | * @note vA: TypeSize |
| 645 | * @note vB: destination and source |
| 646 | * @note vC: source |
| 647 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 648 | void GenOrVector(MIR* mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 649 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 650 | /* |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 651 | * @brief Packed bitwise xor of units in two vector registers: vB = vB .^ vC using vA to know the |
| 652 | * type of the vector. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 653 | * @param mir The MIR whose opcode is kMirConstVector. |
| 654 | * @note vA: TypeSize |
| 655 | * @note vB: destination and source |
| 656 | * @note vC: source |
| 657 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 658 | void GenXorVector(MIR* mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 659 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 660 | /* |
| 661 | * @brief Reduce a 128-bit packed element into a single VR by taking lower bits |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 662 | * @param mir The MIR whose opcode is kMirConstVector. |
| 663 | * @details Instruction does a horizontal addition of the packed elements and then adds it to VR. |
| 664 | * @note vA: TypeSize |
| 665 | * @note vB: destination and source VR (not vector register) |
| 666 | * @note vC: source (vector register) |
| 667 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 668 | void GenAddReduceVector(MIR* mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 669 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 670 | /* |
| 671 | * @brief Extract a packed element into a single VR. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 672 | * @param mir The MIR whose opcode is kMirConstVector. |
| 673 | * @note vA: TypeSize |
| 674 | * @note vB: destination VR (not vector register) |
| 675 | * @note vC: source (vector register) |
| 676 | * @note arg[0]: The index to use for extraction from vector register (which packed element). |
| 677 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 678 | void GenReduceVector(MIR* mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 679 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 680 | /* |
| 681 | * @brief Create a vector value, with all TypeSize values equal to vC |
| 682 | * @param bb The basic block in which the MIR is from. |
| 683 | * @param mir The MIR whose opcode is kMirConstVector. |
| 684 | * @note vA: TypeSize. |
| 685 | * @note vB: destination vector register. |
| 686 | * @note vC: source VR (not vector register). |
| 687 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 688 | void GenSetVector(MIR* mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 689 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 690 | /** |
| 691 | * @brief Used to generate code for kMirOpPackedArrayGet. |
| 692 | * @param bb The basic block of MIR. |
| 693 | * @param mir The mir whose opcode is kMirOpPackedArrayGet. |
| 694 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 695 | void GenPackedArrayGet(BasicBlock* bb, MIR* mir); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 696 | |
| 697 | /** |
| 698 | * @brief Used to generate code for kMirOpPackedArrayPut. |
| 699 | * @param bb The basic block of MIR. |
| 700 | * @param mir The mir whose opcode is kMirOpPackedArrayPut. |
| 701 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 702 | void GenPackedArrayPut(BasicBlock* bb, MIR* mir); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 703 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 704 | /* |
| 705 | * @brief Generate code for a vector opcode. |
| 706 | * @param bb The basic block in which the MIR is from. |
| 707 | * @param mir The MIR whose opcode is a non-standard opcode. |
| 708 | */ |
| 709 | void GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 710 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 711 | /* |
| 712 | * @brief Return the correct x86 opcode for the Dex operation |
| 713 | * @param op Dex opcode for the operation |
| 714 | * @param loc Register location of the operand |
| 715 | * @param is_high_op 'true' if this is an operation on the high word |
| 716 | * @param value Immediate value for the operation. Used for byte variants |
| 717 | * @returns the correct x86 opcode to perform the operation |
| 718 | */ |
| 719 | X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 720 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 721 | /* |
| 722 | * @brief Return the correct x86 opcode for the Dex operation |
| 723 | * @param op Dex opcode for the operation |
| 724 | * @param dest location of the destination. May be register or memory. |
| 725 | * @param rhs Location for the rhs of the operation. May be in register or memory. |
| 726 | * @param is_high_op 'true' if this is an operation on the high word |
| 727 | * @returns the correct x86 opcode to perform the operation |
| 728 | * @note at most one location may refer to memory |
| 729 | */ |
| 730 | X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, |
| 731 | bool is_high_op); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 732 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 733 | /* |
| 734 | * @brief Is this operation a no-op for this opcode and value |
| 735 | * @param op Dex opcode for the operation |
| 736 | * @param value Immediate value for the operation. |
| 737 | * @returns 'true' if the operation will have no effect |
| 738 | */ |
| 739 | bool IsNoOp(Instruction::Code op, int32_t value); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 740 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 741 | /** |
| 742 | * @brief Calculate magic number and shift for a given divisor |
| 743 | * @param divisor divisor number for calculation |
| 744 | * @param magic hold calculated magic number |
| 745 | * @param shift hold calculated shift |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 746 | * @param is_long 'true' if divisor is jlong, 'false' for jint. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 747 | */ |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 748 | void CalculateMagicAndShift(int64_t divisor, int64_t& magic, int& shift, bool is_long); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 749 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 750 | /* |
| 751 | * @brief Generate an integer div or rem operation. |
| 752 | * @param rl_dest Destination Location. |
| 753 | * @param rl_src1 Numerator Location. |
| 754 | * @param rl_src2 Divisor Location. |
| 755 | * @param is_div 'true' if this is a division, 'false' for a remainder. |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 756 | * @param flags The instruction optimization flags. It can include information |
| 757 | * if exception check can be elided. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 758 | */ |
| 759 | RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 760 | bool is_div, int flags); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 761 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 762 | /* |
| 763 | * @brief Generate an integer div or rem operation by a literal. |
| 764 | * @param rl_dest Destination Location. |
| 765 | * @param rl_src Numerator Location. |
| 766 | * @param lit Divisor. |
| 767 | * @param is_div 'true' if this is a division, 'false' for a remainder. |
| 768 | */ |
| 769 | RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 770 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 771 | /* |
| 772 | * Generate code to implement long shift operations. |
| 773 | * @param opcode The DEX opcode to specify the shift type. |
| 774 | * @param rl_dest The destination. |
| 775 | * @param rl_src The value to be shifted. |
| 776 | * @param shift_amount How much to shift. |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 777 | * @param flags The instruction optimization flags. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 778 | * @returns the RegLocation of the result. |
| 779 | */ |
| 780 | RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 781 | RegLocation rl_src, int shift_amount, int flags); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 782 | /* |
| 783 | * Generate an imul of a register by a constant or a better sequence. |
| 784 | * @param dest Destination Register. |
| 785 | * @param src Source Register. |
| 786 | * @param val Constant multiplier. |
| 787 | */ |
| 788 | void GenImulRegImm(RegStorage dest, RegStorage src, int val); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 789 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 790 | /* |
| 791 | * Generate an imul of a memory location by a constant or a better sequence. |
| 792 | * @param dest Destination Register. |
| 793 | * @param sreg Symbolic register. |
| 794 | * @param displacement Displacement on stack of Symbolic Register. |
| 795 | * @param val Constant multiplier. |
| 796 | */ |
| 797 | void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 798 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 799 | /* |
| 800 | * @brief Compare memory to immediate, and branch if condition true. |
| 801 | * @param cond The condition code that when true will branch to the target. |
| 802 | * @param temp_reg A temporary register that can be used if compare memory is not |
| 803 | * supported by the architecture. |
| 804 | * @param base_reg The register holding the base address. |
| 805 | * @param offset The offset from the base. |
| 806 | * @param check_value The immediate to compare to. |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 807 | * @param target branch target (or nullptr) |
| 808 | * @param compare output for getting LIR for comparison (or nullptr) |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 809 | */ |
| 810 | LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 811 | int offset, int check_value, LIR* target, LIR** compare); |
Mark Mendell | 766e929 | 2014-01-27 07:55:47 -0800 | [diff] [blame] | 812 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 813 | void GenRemFP(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, bool is_double); |
| 814 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 815 | /* |
| 816 | * Can this operation be using core registers without temporaries? |
| 817 | * @param rl_lhs Left hand operand. |
| 818 | * @param rl_rhs Right hand operand. |
| 819 | * @returns 'true' if the operation can proceed without needing temporary regs. |
| 820 | */ |
| 821 | bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs); |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 822 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 823 | /** |
| 824 | * @brief Generates inline code for conversion of long to FP by using x87/ |
| 825 | * @param rl_dest The destination of the FP. |
| 826 | * @param rl_src The source of the long. |
| 827 | * @param is_double 'true' if dealing with double, 'false' for float. |
| 828 | */ |
| 829 | virtual void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 830 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 831 | void GenArrayBoundsCheck(RegStorage index, RegStorage array_base, int32_t len_offset); |
| 832 | void GenArrayBoundsCheck(int32_t index, RegStorage array_base, int32_t len_offset); |
| 833 | |
| 834 | LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); |
| 835 | LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value); |
| 836 | LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value); |
| 837 | LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset); |
| 838 | LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset); |
| 839 | void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset); |
| 840 | void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset); |
| 841 | void OpTlsCmp(ThreadOffset<4> offset, int val); |
| 842 | void OpTlsCmp(ThreadOffset<8> offset, int val); |
| 843 | |
| 844 | void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); |
| 845 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 846 | // Try to do a long multiplication where rl_src2 is a constant. This simplified setup might fail, |
| 847 | // in which case false will be returned. |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 848 | bool GenMulLongConst(RegLocation rl_dest, RegLocation rl_src1, int64_t val, int flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 849 | void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 850 | RegLocation rl_src2, int flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 851 | void GenNotLong(RegLocation rl_dest, RegLocation rl_src); |
| 852 | void GenNegLong(RegLocation rl_dest, RegLocation rl_src); |
| 853 | void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 854 | RegLocation rl_src2, bool is_div, int flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 855 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 856 | void SpillCoreRegs(); |
| 857 | void UnSpillCoreRegs(); |
| 858 | void UnSpillFPRegs(); |
| 859 | void SpillFPRegs(); |
| 860 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 861 | /* |
| 862 | * @brief Perform MIR analysis before compiling method. |
| 863 | * @note Invokes Mir2LiR::Materialize after analysis. |
| 864 | */ |
| 865 | void Materialize(); |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 866 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 867 | /* |
| 868 | * Mir2Lir's UpdateLoc() looks to see if the Dalvik value is currently live in any temp register |
| 869 | * without regard to data type. In practice, this can result in UpdateLoc returning a |
| 870 | * location record for a Dalvik float value in a core register, and vis-versa. For targets |
| 871 | * which can inexpensively move data between core and float registers, this can often be a win. |
| 872 | * However, for x86 this is generally not a win. These variants of UpdateLoc() |
| 873 | * take a register class argument - and will return an in-register location record only if |
| 874 | * the value is live in a temp register of the correct class. Additionally, if the value is in |
| 875 | * a temp register of the wrong register class, it will be clobbered. |
| 876 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 877 | RegLocation UpdateLocTyped(RegLocation loc); |
| 878 | RegLocation UpdateLocWideTyped(RegLocation loc); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 879 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 880 | /* |
| 881 | * @brief Analyze MIR before generating code, to prepare for the code generation. |
| 882 | */ |
| 883 | void AnalyzeMIR(); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 884 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 885 | /* |
| 886 | * @brief Analyze one basic block. |
| 887 | * @param bb Basic block to analyze. |
| 888 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 889 | void AnalyzeBB(BasicBlock* bb); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 890 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 891 | /* |
| 892 | * @brief Analyze one extended MIR instruction |
| 893 | * @param opcode MIR instruction opcode. |
| 894 | * @param bb Basic block containing instruction. |
| 895 | * @param mir Extended instruction to analyze. |
| 896 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 897 | void AnalyzeExtendedMIR(int opcode, BasicBlock* bb, MIR* mir); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 898 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 899 | /* |
| 900 | * @brief Analyze one MIR instruction |
| 901 | * @param opcode MIR instruction opcode. |
| 902 | * @param bb Basic block containing instruction. |
| 903 | * @param mir Instruction to analyze. |
| 904 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 905 | virtual void AnalyzeMIR(int opcode, BasicBlock* bb, MIR* mir); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 906 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 907 | /* |
| 908 | * @brief Analyze one MIR float/double instruction |
| 909 | * @param opcode MIR instruction opcode. |
| 910 | * @param bb Basic block containing instruction. |
| 911 | * @param mir Instruction to analyze. |
| 912 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 913 | virtual void AnalyzeFPInstruction(int opcode, BasicBlock* bb, MIR* mir); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 914 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 915 | /* |
| 916 | * @brief Analyze one use of a double operand. |
| 917 | * @param rl_use Double RegLocation for the operand. |
| 918 | */ |
| 919 | void AnalyzeDoubleUse(RegLocation rl_use); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 920 | |
Yixin Shou | 7071c8d | 2014-03-05 06:07:48 -0500 | [diff] [blame] | 921 | /* |
| 922 | * @brief Analyze one invoke-static MIR instruction |
| 923 | * @param opcode MIR instruction opcode. |
| 924 | * @param bb Basic block containing instruction. |
| 925 | * @param mir Instruction to analyze. |
| 926 | */ |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 927 | void AnalyzeInvokeStatic(int opcode, BasicBlock* bb, MIR* mir); |
Yixin Shou | 7071c8d | 2014-03-05 06:07:48 -0500 | [diff] [blame] | 928 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 929 | // Information derived from analysis of MIR |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 930 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 931 | // The compiler temporary for the code address of the method. |
| 932 | CompilerTemp *base_of_code_; |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 933 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 934 | // Have we decided to compute a ptr to code and store in temporary VR? |
| 935 | bool store_method_addr_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 936 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 937 | // Have we used the stored method address? |
| 938 | bool store_method_addr_used_; |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 939 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 940 | // Instructions to remove if we didn't use the stored method address. |
| 941 | LIR* setup_method_address_[2]; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 942 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 943 | // Instructions needing patching with Method* values. |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 944 | ArenaVector<LIR*> method_address_insns_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 945 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 946 | // Instructions needing patching with Class Type* values. |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 947 | ArenaVector<LIR*> class_type_address_insns_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 948 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 949 | // Instructions needing patching with PC relative code addresses. |
Vladimir Marko | e39c54e | 2014-09-22 14:50:02 +0100 | [diff] [blame] | 950 | ArenaVector<LIR*> call_method_insns_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 951 | |
Vladimir Marko | dc56cc5 | 2015-03-27 18:18:36 +0000 | [diff] [blame] | 952 | // Instructions needing patching with PC relative code addresses. |
| 953 | ArenaVector<LIR*> dex_cache_access_insns_; |
| 954 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 955 | // The list of const vector literals. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 956 | LIR* const_vectors_; |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 957 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 958 | /* |
| 959 | * @brief Search for a matching vector literal |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 960 | * @param constants An array of size 4 which contains all of 32-bit constants. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 961 | * @returns pointer to matching LIR constant, or nullptr if not found. |
| 962 | */ |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 963 | LIR* ScanVectorLiteral(int32_t* constants); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 964 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 965 | /* |
| 966 | * @brief Add a constant vector literal |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 967 | * @param constants An array of size 4 which contains all of 32-bit constants. |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 968 | */ |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 969 | LIR* AddVectorLiteral(int32_t* constants); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 970 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 971 | bool WideGPRsAreAliases() const OVERRIDE { |
Serguei Katkov | 59a42af | 2014-07-05 00:55:46 +0700 | [diff] [blame] | 972 | return cu_->target64; // On 64b, we have 64b GPRs. |
| 973 | } |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 974 | |
| 975 | bool WideFPRsAreAliases() const OVERRIDE { |
Serguei Katkov | 59a42af | 2014-07-05 00:55:46 +0700 | [diff] [blame] | 976 | return true; // xmm registers have 64b views even on x86. |
| 977 | } |
| 978 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 979 | /* |
| 980 | * @brief Dump a RegLocation using printf |
| 981 | * @param loc Register location to dump |
| 982 | */ |
| 983 | static void DumpRegLocation(RegLocation loc); |
| 984 | |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 985 | private: |
Yixin Shou | 8c914c0 | 2014-07-28 14:17:09 -0400 | [diff] [blame] | 986 | void SwapBits(RegStorage result_reg, int shift, int32_t value); |
| 987 | void SwapBits64(RegStorage result_reg, int shift, int64_t value); |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 988 | |
Vladimir Marko | dc56cc5 | 2015-03-27 18:18:36 +0000 | [diff] [blame] | 989 | static int X86NextSDCallInsn(CompilationUnit* cu, CallInfo* info, |
| 990 | int state, const MethodReference& target_method, |
| 991 | uint32_t, |
| 992 | uintptr_t direct_code, uintptr_t direct_method, |
| 993 | InvokeType type); |
| 994 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 995 | static const X86EncodingMap EncodingMap[kX86Last]; |
| 996 | |
| 997 | friend std::ostream& operator<<(std::ostream& os, const X86OpCode& rhs); |
| 998 | |
| 999 | DISALLOW_COPY_AND_ASSIGN(X86Mir2Lir); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1000 | }; |
| 1001 | |
| 1002 | } // namespace art |
| 1003 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 1004 | #endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ |