Blame - src/compiler/codegen/x86/assemble_x86.cc - platform_art

2012-03-06 22:14:17 -0800

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2012-06-28 11:29:57 -0700

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{ kX86 ## opname ## 16MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16MR", "[!0r+!1d],!2r" }, \

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{ kX86 ## opname ## 16AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \

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{ kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16TR", "fs:[!0d],!1r" }, \

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{ kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RR", "!0r,!1r" }, \

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{ kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \

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{ kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RT", "!0r,fs:[!1d]" }, \

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{ kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16TI", "fs:[!0d],!1d" }, \

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{ kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16RI8", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16MI8", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16TI8", "fs:[!0d],!1d" }, \

Ian Rogers

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jeffhao

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{ kX86 ## opname ## 32MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32MR", "[!0r+!1d],!2r" }, \

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{ kX86 ## opname ## 32AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \

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{ kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32TR", "fs:[!0d],!1r" }, \

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{ kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RR", "!0r,!1r" }, \

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{ kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \

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{ kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RT", "!0r,fs:[!1d]" }, \

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{ kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32TI", "fs:[!0d],!1d" }, \

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{ kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32RI8", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32MI8", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32TI8", "fs:[!0d],!1d" }

Ian Rogers

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jeffhao

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ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */,

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0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */,

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0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */,

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0x80, 0x0 /* RegMem8/imm8 */,

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0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */),

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ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */,

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0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */,

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0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */,

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0x80, 0x1 /* RegMem8/imm8 */,

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0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */),

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ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,

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0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */,

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0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */,

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0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */,

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0x80, 0x2 /* RegMem8/imm8 */,

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0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */),

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ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,

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0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */,

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0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */,

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0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */,

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0x80, 0x3 /* RegMem8/imm8 */,

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0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */),

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ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */,

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0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */,

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0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */,

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0x80, 0x4 /* RegMem8/imm8 */,

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0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */),

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ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */,

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0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */,

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0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */,

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0x80, 0x5 /* RegMem8/imm8 */,

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0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */),

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ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */,

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0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */,

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0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */,

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0x80, 0x6 /* RegMem8/imm8 */,

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0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */),

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ENCODING_MAP(Cmp, IS_LOAD, 0, 0,

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0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */,

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0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */,

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0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */,

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0x80, 0x7 /* RegMem8/imm8 */,

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0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */),

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#undef ENCODING_MAP

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{ kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RRI", "!0r,!1r,!2d" },

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{ kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RMI", "!0r,[!1r+!2d],!3d" },

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{ kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },

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{ kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RRI", "!0r,!1r,!2d" },

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{ kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RMI", "!0r,[!1r+!2d],!3d" },

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{ kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },

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{ kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RRI8", "!0r,!1r,!2d" },

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{ kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" },

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{ kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" },

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jeffhao

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{ kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8MR", "[!0r+!1d],!2r" },

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{ kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8TR", "fs:[!0d],!1r" },

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{ kX86Mov8RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RR", "!0r,!1r" },

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{ kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RM", "!0r,[!1r+!2d]" },

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{ kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RT", "!0r,fs:[!1d]" },

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{ kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1 }, "Mov8RI", "!0r,!1d" },

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{ kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8MI", "[!0r+!1d],!2d" },

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{ kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8TI", "fs:[!0d],!1d" },

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{ kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16MR", "[!0r+!1d],!2r" },

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{ kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0 }, "Mov16TR", "fs:[!0d],!1r" },

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{ kX86Mov16RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RR", "!0r,!1r" },

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{ kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RM", "!0r,[!1r+!2d]" },

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{ kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RT", "!0r,fs:[!1d]" },

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{ kX86Mov16RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2 }, "Mov16RI", "!0r,!1d" },

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{ kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16MI", "[!0r+!1d],!2d" },

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{ kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2 }, "Mov16TI", "fs:[!0d],!1d" },

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{ kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32MR", "[!0r+!1d],!2r" },

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{ kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32TR", "fs:[!0d],!1r" },

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{ kX86Mov32RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RR", "!0r,!1r" },

169

{ kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RM", "!0r,[!1r+!2d]" },

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{ kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RT", "!0r,fs:[!1d]" },

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{ kX86Mov32RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "Mov32RI", "!0r,!1d" },

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{ kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32MI", "[!0r+!1d],!2d" },

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{ kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32TI", "fs:[!0d],!1d" },

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{ kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \

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{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \

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{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \

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{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \

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{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }

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SHIFT_ENCODING_MAP(Rol, 0x0),

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SHIFT_ENCODING_MAP(Ror, 0x1),

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SHIFT_ENCODING_MAP(Rcl, 0x2),

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SHIFT_ENCODING_MAP(Rcr, 0x3),

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SHIFT_ENCODING_MAP(Sal, 0x4),

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SHIFT_ENCODING_MAP(Shr, 0x5),

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SHIFT_ENCODING_MAP(Sar, 0x7),

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#undef SHIFT_ENCODING_MAP

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{ kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0}, "Cmc", "" },

211

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{ kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" },

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{ kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" },

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{ kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" },

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{ kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" },

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{ kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" },

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{ kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" },

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{ kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0}, "Test32RR", "!0r,!1r" },

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#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \

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reg, reg_kind, reg_flags, \

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mem, mem_kind, mem_flags, \

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arr, arr_kind, arr_flags, imm, \

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b_flags, hw_flags, w_flags, \

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b_format, hw_format, w_format) \

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{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, #b_format "!0r" }, \

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{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, #b_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, #b_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, #hw_format "!0r" }, \

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{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, #hw_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, #hw_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, #w_format "!0r" }, \

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{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, #w_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, #w_format "[!0r+!1r<<!2d+!3d]" }

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UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

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UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

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#undef UNARY_ENCODING_MAP

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#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \

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{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

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{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

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EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),

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{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

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{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),

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{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

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{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0),

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EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0),

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{ kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" },

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{ kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" },

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286

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EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),

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{ kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" },

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{ kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" },

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{ kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

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{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

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{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

295

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

296

// TODO: load/store?

297

// Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.

298

{ kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },

299

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

300

EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES),

301

EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES),

jeffhao

8302576

2012-08-02 11:08:56 -0700

[diff] [blame]

302

303

{ kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" },

304

{ kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" },

305

{ kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

306

{ kX86LockCmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "!0r,!1r" },

307

{ kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" },

308

{ kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

309

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

310

EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),

311

EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),

312

EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),

313

EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

314

#undef EXT_0F_ENCODING_MAP

315

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

316

{ kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },

317

{ kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },

318

{ kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },

319

{ kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },

320

{ kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" },

321

{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

322

{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

323

{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

324

{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

325

{ kX86Ret, kNullary,NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

326

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

327

{ kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" },

328

{ kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },

329

{ kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" },

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

330

};

331

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

332

static size_t computeSize(X86EncodingMap* entry, int displacement, bool has_sib) {

333

size_t size = 0;

334

if (entry->skeleton.prefix1 > 0) {

335

++size;

336

if (entry->skeleton.prefix2 > 0) {

337

++size;

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

338

}

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

339

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

340

++size; // opcode

341

if (entry->skeleton.opcode == 0x0F) {

342

++size;

343

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

if (has_sib) {

++size;

}

if (displacement != 0) {

352

if (entry->opcode != kX86Lea32RA) {

buzbee

ec13743

2012-11-13 12:13:16 -0800

[diff] [blame]

353

DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

354

}

355

size += IS_SIMM8(displacement) ? 1 : 4;

356

}

357

size += entry->skeleton.immediate_bytes;

return size;

}

int oatGetInsnSize(LIR* lir) {

362

X86EncodingMap* entry = &EncodingMap[lir->opcode];

363

switch (entry->kind) {

364

case kData:

365

return 4; // 4 bytes of data

366

case kNop:

367

return lir->operands[0]; // length of nop is sole operand

368

case kNullary:

369

return 1; // 1 byte of opcode

370

case kReg: // lir operands - 0: reg

371

return computeSize(entry, 0, false);

372

case kMem: { // lir operands - 0: base, 1: disp

373

int base = lir->operands[0];

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

374

int disp = lir->operands[1];

375

// SP requires a special extra SIB byte. BP requires explicit disp,

376

// so add a byte for disp 0 which would normally be omitted.

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

377

return computeSize(entry, disp, false) + ((base == rX86_SP) || (base == rBP && disp == 0) ? 1 : 0);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

378

}

379

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

380

return computeSize(entry, lir->operands[3], true);

381

case kMemReg: { // lir operands - 0: base, 1: disp, 2: reg

382

int base = lir->operands[0];

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

383

int disp = lir->operands[1];

384

// SP requires a special extra SIB byte. BP requires explicit disp,

385

// so add a byte for disp 0 which would normally be omitted.

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

386

return computeSize(entry, disp, false) + ((base == rX86_SP) || (base == rBP && disp == 0) ? 1 : 0);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

387

}

388

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

389

return computeSize(entry, lir->operands[3], true);

390

case kThreadReg: // lir operands - 0: disp, 1: reg

391

return computeSize(entry, lir->operands[0], false);

392

case kRegReg:

393

return computeSize(entry, 0, false);

jeffhao

2012-07-11 16:08:43 -0700

[diff] [blame]

394

case kRegRegStore:

395

return computeSize(entry, 0, false);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

396

case kRegMem: { // lir operands - 0: reg, 1: base, 2: disp

397

int base = lir->operands[1];

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

398

int disp = lir->operands[2];

399

// SP requires a special extra SIB byte. BP requires explicit disp,

400

// so add a byte for disp 0 which would normally be omitted.

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

401

return computeSize(entry, disp, false) + ((base == rX86_SP) || (base == rBP && disp == 0) ? 1 : 0);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

402

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

403

case kRegArray: { // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

404

int base = lir->operands[1];

405

int disp = lir->operands[4];

406

// BP requires explicit disp, so add a byte for disp 0 which would normally be omitted.

407

return computeSize(entry, disp, true) + ((base == rBP && disp == 0) ? 1 : 0);

408

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

409

case kRegThread: // lir operands - 0: reg, 1: disp

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

410

return computeSize(entry, 0x12345678, false); // displacement size is always 32bit

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

411

case kRegImm: { // lir operands - 0: reg, 1: immediate

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

412

size_t size = computeSize(entry, 0, false);

413

if (entry->skeleton.ax_opcode == 0) {

414

return size;

415

} else {

416

// AX opcodes don't require the modrm byte.

417

int reg = lir->operands[0];

418

return size - (reg == rAX ? 1 : 0);

419

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

420

}

421

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

422

CHECK_NE(lir->operands[0], static_cast<int>(rX86_SP)); // TODO: add extra SIB byte

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

423

return computeSize(entry, lir->operands[1], false);

424

case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

425

return computeSize(entry, lir->operands[3], true);

426

case kThreadImm: // lir operands - 0: disp, 1: imm

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

427

return computeSize(entry, 0x12345678, false); // displacement size is always 32bit

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

428

case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

429

return computeSize(entry, 0, false);

430

case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

431

CHECK_NE(lir->operands[1], static_cast<int>(rX86_SP)); // TODO: add extra SIB byte

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

432

return computeSize(entry, lir->operands[2], false);

433

case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

434

return computeSize(entry, lir->operands[4], true);

435

case kMovRegImm: // lir operands - 0: reg, 1: immediate

436

return 1 + entry->skeleton.immediate_bytes;

437

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

438

// Shift by immediate one has a shorter opcode.

439

return computeSize(entry, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

440

case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

441

CHECK_NE(lir->operands[0], static_cast<int>(rX86_SP)); // TODO: add extra SIB byte

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

442

// Shift by immediate one has a shorter opcode.

443

return computeSize(entry, lir->operands[1], false) - (lir->operands[2] == 1 ? 1 : 0);

444

case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

445

// Shift by immediate one has a shorter opcode.

446

return computeSize(entry, lir->operands[3], true) - (lir->operands[4] == 1 ? 1 : 0);

447

case kShiftRegCl:

448

return computeSize(entry, 0, false);

449

case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

450

CHECK_NE(lir->operands[0], static_cast<int>(rX86_SP)); // TODO: add extra SIB byte

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

451

return computeSize(entry, lir->operands[1], false);

452

case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

453

return computeSize(entry, lir->operands[3], true);

454

case kRegCond: // lir operands - 0: reg, 1: cond

455

return computeSize(entry, 0, false);

456

case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

457

CHECK_NE(lir->operands[0], static_cast<int>(rX86_SP)); // TODO: add extra SIB byte

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

458

return computeSize(entry, lir->operands[1], false);

459

case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

460

return computeSize(entry, lir->operands[3], true);

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

461

case kJcc:

462

if (lir->opcode == kX86Jcc8) {

463

return 2; // opcode + rel8

464

} else {

465

DCHECK(lir->opcode == kX86Jcc32);

466

return 6; // 2 byte opcode + rel32

467

}

468

case kJmp:

469

if (lir->opcode == kX86Jmp8) {

470

return 2; // opcode + rel8

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

471

} else if (lir->opcode == kX86Jmp32) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

472

return 5; // opcode + rel32

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

473

} else {

474

DCHECK(lir->opcode == kX86JmpR);

475

return 2; // opcode + modrm

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

476

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

477

case kCall:

Elliott Hughes

b25c3f6

2012-03-26 16:35:06 -0700

[diff] [blame]

478

switch (lir->opcode) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

479

case kX86CallR: return 2; // opcode modrm

480

case kX86CallM: // lir operands - 0: base, 1: disp

481

return computeSize(entry, lir->operands[1], false);

482

case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

483

return computeSize(entry, lir->operands[3], true);

Ian Rogers

6cbb2bd

2012-03-16 13:45:30 -0700

[diff] [blame]

484

case kX86CallT: // lir operands - 0: disp

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

485

return computeSize(entry, 0x12345678, false); // displacement size is always 32bit

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

default:

break;

}

break;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

490

case kPcRel:

491

if (entry->opcode == kX86PcRelLoadRA) {

492

// lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

493

return computeSize(entry, 0x12345678, true);

494

} else {

495

DCHECK(entry->opcode == kX86PcRelAdr);

496

return 5; // opcode with reg + 4 byte immediate

497

}

498

case kMacro:

499

DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));

500

return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +

501

computeSize(&EncodingMap[kX86Sub32RI], 0, false) -

502

(lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

507

return 0;

508

}

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

509

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

510

static uint8_t modrmForDisp(int base, int disp) {

511

// BP requires an explicit disp, so do not omit it in the 0 case

512

if (disp == 0 && base != rBP) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

513

return 0;

514

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

521

static void emitDisp(CompilationUnit* cUnit, int base, int disp) {

522

// BP requires an explicit disp, so do not omit it in the 0 case

523

if (disp == 0 && base != rBP) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

524

return;

525

} else if (IS_SIMM8(disp)) {

526

cUnit->codeBuffer.push_back(disp & 0xFF);

527

} else {

528

cUnit->codeBuffer.push_back(disp & 0xFF);

529

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

530

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

531

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

}

}

static void emitOpReg(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg) {

536

if (entry->skeleton.prefix1 != 0) {

537

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

538

if (entry->skeleton.prefix2 != 0) {

539

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

540

}

541

} else {

542

DCHECK_EQ(0, entry->skeleton.prefix2);

543

}

544

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

545

if (entry->skeleton.opcode == 0x0F) {

546

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

547

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

548

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

549

} else {

550

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

551

}

552

} else {

553

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

554

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

555

}

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

556

if (X86_FPREG(reg)) {

557

reg = reg & X86_FP_REG_MASK;

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

558

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

559

if (reg >= 4) {

buzbee

2012-11-17 14:11:25 -0800

[diff] [blame]

560

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

561

<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);

562

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

563

DCHECK_LT(reg, 8);

564

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

565

cUnit->codeBuffer.push_back(modrm);

566

DCHECK_EQ(0, entry->skeleton.ax_opcode);

567

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

568

}

569

570

static void emitOpMem(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t base, int disp) {

571

if (entry->skeleton.prefix1 != 0) {

572

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

573

if (entry->skeleton.prefix2 != 0) {

574

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

575

}

576

} else {

577

DCHECK_EQ(0, entry->skeleton.prefix2);

578

}

579

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

580

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

581

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

582

DCHECK_LT(entry->skeleton.modrm_opcode, 8);

583

DCHECK_LT(base, 8);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

584

uint8_t modrm = (modrmForDisp(base, disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

585

cUnit->codeBuffer.push_back(modrm);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

586

emitDisp(cUnit, base, disp);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

587

DCHECK_EQ(0, entry->skeleton.ax_opcode);

588

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

589

}

590

591

static void emitMemReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

592

uint8_t base, int disp, uint8_t reg) {

593

if (entry->skeleton.prefix1 != 0) {

594

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

595

if (entry->skeleton.prefix2 != 0) {

596

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

597

}

598

} else {

599

DCHECK_EQ(0, entry->skeleton.prefix2);

600

}

601

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

602

if (entry->skeleton.opcode == 0x0F) {

603

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

604

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

605

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

606

} else {

607

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

608

}

609

} else {

610

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

611

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

612

}

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

613

if (X86_FPREG(reg)) {

614

reg = reg & X86_FP_REG_MASK;

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

615

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

616

if (reg >= 4) {

buzbee

2012-11-17 14:11:25 -0800

[diff] [blame]

617

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

618

<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);

619

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

620

DCHECK_LT(reg, 8);

621

DCHECK_LT(base, 8);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

622

uint8_t modrm = (modrmForDisp(base, disp) << 6) | (reg << 3) | base;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

623

cUnit->codeBuffer.push_back(modrm);

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

624

if (base == rX86_SP) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

625

// Special SIB for SP base

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

626

cUnit->codeBuffer.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

627

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

628

emitDisp(cUnit, base, disp);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

629

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

630

DCHECK_EQ(0, entry->skeleton.ax_opcode);

631

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

632

}

633

634

static void emitRegMem(CompilationUnit* cUnit, const X86EncodingMap* entry,

635

uint8_t reg, uint8_t base, int disp) {

636

// Opcode will flip operands.

637

emitMemReg(cUnit, entry, base, disp, reg);

638

}

639

640

static void emitRegArray(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg,

641

uint8_t base, uint8_t index, int scale, int disp) {

642

if (entry->skeleton.prefix1 != 0) {

643

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

644

if (entry->skeleton.prefix2 != 0) {

645

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

646

}

647

} else {

648

DCHECK_EQ(0, entry->skeleton.prefix2);

649

}

650

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

651

if (entry->skeleton.opcode == 0x0F) {

652

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

653

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

654

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

655

} else {

656

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

657

}

658

} else {

659

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

660

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

661

}

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

662

if (X86_FPREG(reg)) {

663

reg = reg & X86_FP_REG_MASK;

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

664

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

665

DCHECK_LT(reg, 8);

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

666

uint8_t modrm = (modrmForDisp(base, disp) << 6) | (reg << 3) | rX86_SP;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

667

cUnit->codeBuffer.push_back(modrm);

DCHECK_LT(scale, 4);

DCHECK_LT(index, 8);

DCHECK_LT(base, 8);

uint8_t sib = (scale << 6) | (index << 3) | base;

672

cUnit->codeBuffer.push_back(sib);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

673

emitDisp(cUnit, base, disp);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

674

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

675

DCHECK_EQ(0, entry->skeleton.ax_opcode);

676

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

677

}

678

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

679

static void emitArrayReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

680

uint8_t base, uint8_t index, int scale, int disp, uint8_t reg) {

681

// Opcode will flip operands.

682

emitRegArray(cUnit, entry, reg, base, index, scale, disp);

683

}

684

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

685

static void emitRegThread(CompilationUnit* cUnit, const X86EncodingMap* entry,

686

uint8_t reg, int disp) {

687

DCHECK_NE(entry->skeleton.prefix1, 0);

688

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

689

if (entry->skeleton.prefix2 != 0) {

690

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

691

}

692

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

693

if (entry->skeleton.opcode == 0x0F) {

694

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

695

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

696

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

697

} else {

698

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

699

}

700

} else {

701

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

702

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

703

}

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

704

if (X86_FPREG(reg)) {

705

reg = reg & X86_FP_REG_MASK;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

706

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

707

if (reg >= 4) {

buzbee

2012-11-17 14:11:25 -0800

[diff] [blame]

708

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

709

<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);

710

}

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

711

DCHECK_LT(reg, 8);

712

uint8_t modrm = (0 << 6) | (reg << 3) | rBP;

713

cUnit->codeBuffer.push_back(modrm);

714

cUnit->codeBuffer.push_back(disp & 0xFF);

715

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

716

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

717

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

718

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

719

DCHECK_EQ(0, entry->skeleton.ax_opcode);

720

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

721

}

722

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

723

static void emitRegReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

724

uint8_t reg1, uint8_t reg2) {

725

if (entry->skeleton.prefix1 != 0) {

726

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

727

if (entry->skeleton.prefix2 != 0) {

728

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

729

}

730

} else {

731

DCHECK_EQ(0, entry->skeleton.prefix2);

732

}

733

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

734

if (entry->skeleton.opcode == 0x0F) {

735

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

736

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

737

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

738

} else {

739

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

740

}

741

} else {

742

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

743

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

744

}

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

745

if (X86_FPREG(reg1)) {

746

reg1 = reg1 & X86_FP_REG_MASK;

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

747

}

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

748

if (X86_FPREG(reg2)) {

749

reg2 = reg2 & X86_FP_REG_MASK;

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

750

}

751

DCHECK_LT(reg1, 8);

752

DCHECK_LT(reg2, 8);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

753

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

754

cUnit->codeBuffer.push_back(modrm);

755

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

756

DCHECK_EQ(0, entry->skeleton.ax_opcode);

757

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

758

}

759

Elliott Hughes

2012-04-16 20:21:45 -0700

[diff] [blame]

760

static void emitRegRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

761

uint8_t reg1, uint8_t reg2, int32_t imm) {

762

if (entry->skeleton.prefix1 != 0) {

763

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

764

if (entry->skeleton.prefix2 != 0) {

765

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

766

}

767

} else {

768

DCHECK_EQ(0, entry->skeleton.prefix2);

769

}

770

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

771

if (entry->skeleton.opcode == 0x0F) {

772

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

773

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

774

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

775

} else {

776

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

777

}

778

} else {

779

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

780

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

781

}

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

782

if (X86_FPREG(reg1)) {

783

reg1 = reg1 & X86_FP_REG_MASK;

Elliott Hughes

2012-04-16 20:21:45 -0700

[diff] [blame]

784

}

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

785

if (X86_FPREG(reg2)) {

786

reg2 = reg2 & X86_FP_REG_MASK;

Elliott Hughes

2012-04-16 20:21:45 -0700

[diff] [blame]

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

791

cUnit->codeBuffer.push_back(modrm);

792

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

793

DCHECK_EQ(0, entry->skeleton.ax_opcode);

794

switch (entry->skeleton.immediate_bytes) {

795

case 1:

796

DCHECK(IS_SIMM8(imm));

797

cUnit->codeBuffer.push_back(imm & 0xFF);

798

break;

799

case 2:

800

DCHECK(IS_SIMM16(imm));

801

cUnit->codeBuffer.push_back(imm & 0xFF);

802

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

803

break;

804

case 4:

805

cUnit->codeBuffer.push_back(imm & 0xFF);

806

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

807

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

808

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

809

break;

810

default:

811

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

812

<< ") for instruction: " << entry->name;

break;

}

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

817

static void emitRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

818

uint8_t reg, int imm) {

819

if (entry->skeleton.prefix1 != 0) {

820

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

821

if (entry->skeleton.prefix2 != 0) {

822

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

823

}

824

} else {

825

DCHECK_EQ(0, entry->skeleton.prefix2);

826

}

827

if (reg == rAX && entry->skeleton.ax_opcode != 0) {

828

cUnit->codeBuffer.push_back(entry->skeleton.ax_opcode);

829

} else {

830

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

831

if (entry->skeleton.opcode == 0x0F) {

832

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

833

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

834

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

835

} else {

836

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

837

}

838

} else {

839

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

840

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

841

}

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

842

if (X86_FPREG(reg)) {

843

reg = reg & X86_FP_REG_MASK;

jeffhao

2012-07-11 16:08:43 -0700

[diff] [blame]

844

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

845

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

846

cUnit->codeBuffer.push_back(modrm);

847

}

848

switch (entry->skeleton.immediate_bytes) {

849

case 1:

850

DCHECK(IS_SIMM8(imm));

851

cUnit->codeBuffer.push_back(imm & 0xFF);

852

break;

853

case 2:

854

DCHECK(IS_SIMM16(imm));

855

cUnit->codeBuffer.push_back(imm & 0xFF);

856

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

857

break;

858

case 4:

859

cUnit->codeBuffer.push_back(imm & 0xFF);

860

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

861

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

862

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

863

break;

864

default:

865

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

866

<< ") for instruction: " << entry->name;

break;

}

}

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

871

static void emitThreadImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

872

int disp, int imm) {

873

if (entry->skeleton.prefix1 != 0) {

874

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

875

if (entry->skeleton.prefix2 != 0) {

876

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

877

}

878

} else {

879

DCHECK_EQ(0, entry->skeleton.prefix2);

880

}

881

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

882

if (entry->skeleton.opcode == 0x0F) {

883

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

884

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

885

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

886

} else {

887

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

888

}

889

} else {

890

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

891

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

892

}

893

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

894

cUnit->codeBuffer.push_back(modrm);

895

cUnit->codeBuffer.push_back(disp & 0xFF);

896

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

897

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

898

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

899

switch (entry->skeleton.immediate_bytes) {

900

case 1:

901

DCHECK(IS_SIMM8(imm));

902

cUnit->codeBuffer.push_back(imm & 0xFF);

903

break;

904

case 2:

905

DCHECK(IS_SIMM16(imm));

906

cUnit->codeBuffer.push_back(imm & 0xFF);

907

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

908

break;

909

case 4:

910

cUnit->codeBuffer.push_back(imm & 0xFF);

911

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

912

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

913

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

914

break;

915

default:

916

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

917

<< ") for instruction: " << entry->name;

918

break;

919

}

920

DCHECK_EQ(entry->skeleton.ax_opcode, 0);

921

}

922

923

static void emitMovRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

924

uint8_t reg, int imm) {

925

DCHECK_LT(reg, 8);

926

cUnit->codeBuffer.push_back(0xB8 + reg);

927

cUnit->codeBuffer.push_back(imm & 0xFF);

928

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

929

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

930

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

931

}

932

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

933

static void emitShiftRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

934

uint8_t reg, int imm) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

935

if (entry->skeleton.prefix1 != 0) {

936

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

937

if (entry->skeleton.prefix2 != 0) {

938

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

939

}

940

} else {

941

DCHECK_EQ(0, entry->skeleton.prefix2);

942

}

943

if (imm != 1) {

944

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

945

} else {

946

// Shorter encoding for 1 bit shift

947

cUnit->codeBuffer.push_back(entry->skeleton.ax_opcode);

948

}

949

if (entry->skeleton.opcode == 0x0F) {

950

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

951

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

952

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

953

} else {

954

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

955

}

956

} else {

957

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

958

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

959

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

960

if (reg >= 4) {

buzbee

2012-11-17 14:11:25 -0800

[diff] [blame]

961

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

962

<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);

963

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

964

DCHECK_LT(reg, 8);

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

965

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

966

cUnit->codeBuffer.push_back(modrm);

967

if (imm != 1) {

968

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

969

DCHECK(IS_SIMM8(imm));

970

cUnit->codeBuffer.push_back(imm & 0xFF);

}

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

974

static void emitShiftRegCl(CompilationUnit* cUnit, const X86EncodingMap* entry,

975

uint8_t reg, uint8_t cl) {

976

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

977

if (entry->skeleton.prefix1 != 0) {

978

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

979

if (entry->skeleton.prefix2 != 0) {

980

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

981

}

982

} else {

983

DCHECK_EQ(0, entry->skeleton.prefix2);

984

}

985

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

986

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

987

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

988

DCHECK_LT(reg, 8);

989

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

990

cUnit->codeBuffer.push_back(modrm);

991

DCHECK_EQ(0, entry->skeleton.ax_opcode);

992

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

993

}

994

995

static void emitRegCond(CompilationUnit* cUnit, const X86EncodingMap* entry,

996

uint8_t reg, uint8_t condition) {

997

if (entry->skeleton.prefix1 != 0) {

998

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

999

if (entry->skeleton.prefix2 != 0) {

1000

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1001

}

1002

} else {

1003

DCHECK_EQ(0, entry->skeleton.prefix2);

1004

}

1005

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1006

DCHECK_EQ(0x0F, entry->skeleton.opcode);

1007

cUnit->codeBuffer.push_back(0x0F);

1008

DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);

1009

cUnit->codeBuffer.push_back(0x90 | condition);

1010

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1011

DCHECK_LT(reg, 8);

1012

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

1013

cUnit->codeBuffer.push_back(modrm);

1014

DCHECK_EQ(entry->skeleton.immediate_bytes, 0);

1015

}

1016

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1017

static void emitJmp(CompilationUnit* cUnit, const X86EncodingMap* entry, int rel) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1018

if (entry->opcode == kX86Jmp8) {

1019

DCHECK(IS_SIMM8(rel));

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1020

cUnit->codeBuffer.push_back(0xEB);

1021

cUnit->codeBuffer.push_back(rel & 0xFF);

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1022

} else if (entry->opcode == kX86Jmp32) {

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1023

cUnit->codeBuffer.push_back(0xE9);

1024

cUnit->codeBuffer.push_back(rel & 0xFF);

1025

cUnit->codeBuffer.push_back((rel >> 8) & 0xFF);

1026

cUnit->codeBuffer.push_back((rel >> 16) & 0xFF);

1027

cUnit->codeBuffer.push_back((rel >> 24) & 0xFF);

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1028

} else {

1029

DCHECK(entry->opcode == kX86JmpR);

1030

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1031

uint8_t reg = static_cast<uint8_t>(rel);

1032

DCHECK_LT(reg, 8);

1033

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

1034

cUnit->codeBuffer.push_back(modrm);

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

}

}

static void emitJcc(CompilationUnit* cUnit, const X86EncodingMap* entry,

1039

int rel, uint8_t cc) {

1040

DCHECK_LT(cc, 16);

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1041

if (entry->opcode == kX86Jcc8) {

1042

DCHECK(IS_SIMM8(rel));

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1043

cUnit->codeBuffer.push_back(0x70 | cc);

1044

cUnit->codeBuffer.push_back(rel & 0xFF);

1045

} else {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1046

DCHECK(entry->opcode == kX86Jcc32);

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1047

cUnit->codeBuffer.push_back(0x0F);

1048

cUnit->codeBuffer.push_back(0x80 | cc);

1049

cUnit->codeBuffer.push_back(rel & 0xFF);

1050

cUnit->codeBuffer.push_back((rel >> 8) & 0xFF);

1051

cUnit->codeBuffer.push_back((rel >> 16) & 0xFF);

1052

cUnit->codeBuffer.push_back((rel >> 24) & 0xFF);

}

}

static void emitCallMem(CompilationUnit* cUnit, const X86EncodingMap* entry,

1057

uint8_t base, int disp) {

1058

if (entry->skeleton.prefix1 != 0) {

1059

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

1060

if (entry->skeleton.prefix2 != 0) {

1061

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1062

}

1063

} else {

1064

DCHECK_EQ(0, entry->skeleton.prefix2);

1065

}

1066

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1067

if (entry->skeleton.opcode == 0x0F) {

1068

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

1069

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

1070

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

1071

} else {

1072

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1073

}

1074

} else {

1075

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1076

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1077

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

1078

uint8_t modrm = (modrmForDisp(base, disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1079

cUnit->codeBuffer.push_back(modrm);

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

1080

if (base == rX86_SP) {

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1081

// Special SIB for SP base

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

1082

cUnit->codeBuffer.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1083

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

1084

emitDisp(cUnit, base, disp);

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1085

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1086

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1087

}

1088

1089

static void emitCallThread(CompilationUnit* cUnit, const X86EncodingMap* entry, int disp) {

1090

DCHECK_NE(entry->skeleton.prefix1, 0);

1091

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

1092

if (entry->skeleton.prefix2 != 0) {

1093

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1094

}

1095

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1096

if (entry->skeleton.opcode == 0x0F) {

1097

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

1098

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

1099

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

1100

} else {

1101

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1102

}

1103

} else {

1104

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1105

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1106

}

1107

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

1108

cUnit->codeBuffer.push_back(modrm);

1109

cUnit->codeBuffer.push_back(disp & 0xFF);

1110

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

1111

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

1112

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

1113

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1114

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1115

}

1116

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1117

static void emitPcRel(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg,

1118

int base_or_table, uint8_t index, int scale, int table_or_disp) {

1119

int disp;

1120

if (entry->opcode == kX86PcRelLoadRA) {

buzbee

2012-11-17 14:11:25 -0800

[diff] [blame]

1121

SwitchTable *tabRec = reinterpret_cast<SwitchTable*>(table_or_disp);

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1122

disp = tabRec->offset;

1123

} else {

1124

DCHECK(entry->opcode == kX86PcRelAdr);

buzbee

2012-11-17 14:11:25 -0800

[diff] [blame]

1125

FillArrayData *tabRec = reinterpret_cast<FillArrayData*>(base_or_table);

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1126

disp = tabRec->offset;

1127

}

1128

if (entry->skeleton.prefix1 != 0) {

1129

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

1130

if (entry->skeleton.prefix2 != 0) {

1131

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1132

}

1133

} else {

1134

DCHECK_EQ(0, entry->skeleton.prefix2);

1135

}

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

1136

if (X86_FPREG(reg)) {

1137

reg = reg & X86_FP_REG_MASK;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1138

}

1139

DCHECK_LT(reg, 8);

1140

if (entry->opcode == kX86PcRelLoadRA) {

1141

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1142

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1143

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

buzbee

2012-11-13 16:31:10 -0800

[diff] [blame]

1144

uint8_t modrm = (2 << 6) | (reg << 3) | rX86_SP;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1145

cUnit->codeBuffer.push_back(modrm);

1146

DCHECK_LT(scale, 4);

1147

DCHECK_LT(index, 8);

1148

DCHECK_LT(base_or_table, 8);

1149

uint8_t base = static_cast<uint8_t>(base_or_table);

1150

uint8_t sib = (scale << 6) | (index << 3) | base;

1151

cUnit->codeBuffer.push_back(sib);

1152

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1153

} else {

1154

cUnit->codeBuffer.push_back(entry->skeleton.opcode + reg);

1155

}

1156

cUnit->codeBuffer.push_back(disp & 0xFF);

1157

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

1158

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

1159

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

1160

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1161

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1162

}

1163

1164

static void emitMacro(CompilationUnit* cUnit, const X86EncodingMap* entry,

1165

uint8_t reg, int offset) {

1166

DCHECK(entry->opcode == kX86StartOfMethod) << entry->name;

1167

cUnit->codeBuffer.push_back(0xE8); // call +0

1168

cUnit->codeBuffer.push_back(0);

1169

cUnit->codeBuffer.push_back(0);

1170

cUnit->codeBuffer.push_back(0);

1171

cUnit->codeBuffer.push_back(0);

1172

1173

DCHECK_LT(reg, 8);

1174

cUnit->codeBuffer.push_back(0x58 + reg); // pop reg

1175

1176

emitRegImm(cUnit, &EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */);

1177

}

1178

Ian Rogers

6cbb2bd

2012-03-16 13:45:30 -0700

[diff] [blame]

1179

void emitUnimplemented(CompilationUnit* cUnit, const X86EncodingMap* entry, LIR* lir) {

Elliott Hughes

2012-04-16 20:21:45 -0700

[diff] [blame]

1180

UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " " << buildInsnString(entry->fmt, lir, 0);

Ian Rogers

141b0c7

2012-03-15 18:18:52 -0700

[diff] [blame]

1181

for (int i = 0; i < oatGetInsnSize(lir); ++i) {

1182

cUnit->codeBuffer.push_back(0xCC); // push breakpoint instruction - int 3

}

}

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1186

/*

1187

* Assemble the LIR into binary instruction format. Note that we may

1188

* discover that pc-relative displacements may not fit the selected

1189

* instruction. In those cases we will try to substitute a new code

1190

* sequence or request that the trace be shortened and retried.

1191

*/

buzbee

2012-11-17 14:11:25 -0800

[diff] [blame]

1192

AssemblerStatus oatAssembleInstructions(CompilationUnit *cUnit, uintptr_t startAddr) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1193

LIR *lir;

1194

AssemblerStatus res = kSuccess; // Assume success

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1195

Ian Rogers

141d622

2012-04-05 12:23:06 -0700

[diff] [blame]

1196

const bool kVerbosePcFixup = false;

buzbee

2012-11-17 14:11:25 -0800

[diff] [blame]

1197

for (lir = cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1198

if (lir->opcode < 0) {

1199

continue;

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1200

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1201

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1202

if (lir->flags.isNop) {

continue;

}

if (lir->flags.pcRelFixup) {

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1207

switch (lir->opcode) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1208

case kX86Jcc8: {

1209

LIR *targetLIR = lir->target;

1210

DCHECK(targetLIR != NULL);

1211

int delta = 0;

buzbee

2012-11-17 14:11:25 -0800

[diff] [blame]

1212

uintptr_t pc;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1213

if (IS_SIMM8(lir->operands[0])) {

1214

pc = lir->offset + 2 /* opcode + rel8 */;

1215

} else {

1216

pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1217

}

buzbee

2012-11-17 14:11:25 -0800

[diff] [blame]

1218

uintptr_t target = targetLIR->offset;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1219

delta = target - pc;

1220

if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1221

if (kVerbosePcFixup) {

1222

LOG(INFO) << "Retry for JCC growth at " << lir->offset

1223

<< " delta: " << delta << " old delta: " << lir->operands[0];

1224

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1225

lir->opcode = kX86Jcc32;

buzbee

b046e16

2012-10-30 15:48:42 -0700

[diff] [blame]

1226

oatSetupResourceMasks(cUnit, lir);

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1227

res = kRetryAll;

1228

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1229

if (kVerbosePcFixup) {

1230

LOG(INFO) << "Source:";

1231

oatDumpLIRInsn(cUnit, lir, 0);

1232

LOG(INFO) << "Target:";

1233

oatDumpLIRInsn(cUnit, targetLIR, 0);

1234

LOG(INFO) << "Delta " << delta;

1235

}

1236

lir->operands[0] = delta;

break;

}

case kX86Jcc32: {

LIR *targetLIR = lir->target;

1241

DCHECK(targetLIR != NULL);

buzbee

2012-11-17 14:11:25 -0800

[diff] [blame]

1242

uintptr_t pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1243

uintptr_t target = targetLIR->offset;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1244

int delta = target - pc;

1245

if (kVerbosePcFixup) {

1246

LOG(INFO) << "Source:";

1247

oatDumpLIRInsn(cUnit, lir, 0);

1248

LOG(INFO) << "Target:";

1249

oatDumpLIRInsn(cUnit, targetLIR, 0);

1250

LOG(INFO) << "Delta " << delta;

1251

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1252

lir->operands[0] = delta;

1253

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1254

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1255

case kX86Jmp8: {

1256

LIR *targetLIR = lir->target;

1257

DCHECK(targetLIR != NULL);

1258

int delta = 0;

buzbee

2012-11-17 14:11:25 -0800

[diff] [blame]

1259

uintptr_t pc;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1260

if (IS_SIMM8(lir->operands[0])) {

1261

pc = lir->offset + 2 /* opcode + rel8 */;

1262

} else {

1263

pc = lir->offset + 5 /* opcode + rel32 */;

1264

}

buzbee

2012-11-17 14:11:25 -0800

[diff] [blame]

1265

uintptr_t target = targetLIR->offset;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1266

delta = target - pc;

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

1267

if (!(cUnit->disableOpt & (1 << kSafeOptimizations)) && delta == 0) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1268

// Useless branch

1269

lir->flags.isNop = true;

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1270

if (kVerbosePcFixup) {

1271

LOG(INFO) << "Retry for useless branch at " << lir->offset;

1272

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1273

res = kRetryAll;

1274

} else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1275

if (kVerbosePcFixup) {

1276

LOG(INFO) << "Retry for JMP growth at " << lir->offset;

1277

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1278

lir->opcode = kX86Jmp32;

buzbee

b046e16

2012-10-30 15:48:42 -0700

[diff] [blame]

1279

oatSetupResourceMasks(cUnit, lir);

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1280

res = kRetryAll;

1281

}

1282

lir->operands[0] = delta;

1283

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1284

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1285

case kX86Jmp32: {

1286

LIR *targetLIR = lir->target;

1287

DCHECK(targetLIR != NULL);

buzbee

2012-11-17 14:11:25 -0800

[diff] [blame]

1288

uintptr_t pc = lir->offset + 5 /* opcode + rel32 */;

1289

uintptr_t target = targetLIR->offset;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1290

int delta = target - pc;

1291

lir->operands[0] = delta;

1292

break;

1293

}

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1294

default:

1295

break;

1296

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

}

/*

* If one of the pc-relative instructions expanded we'll have

1301

* to make another pass. Don't bother to fully assemble the

1302

* instruction.

1303

*/

1304

if (res != kSuccess) {

1305

continue;

1306

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1307

CHECK_EQ(static_cast<size_t>(lir->offset), cUnit->codeBuffer.size());

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1308

const X86EncodingMap *entry = &EncodingMap[lir->opcode];

Ian Rogers

141b0c7

2012-03-15 18:18:52 -0700

[diff] [blame]

1309

size_t starting_cbuf_size = cUnit->codeBuffer.size();

Elliott Hughes

b25c3f6

2012-03-26 16:35:06 -0700

[diff] [blame]

1310

switch (entry->kind) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1311

case kData: // 4 bytes of data

1312

cUnit->codeBuffer.push_back(lir->operands[0]);

1313

break;

1314

case kNullary: // 1 byte of opcode

1315

DCHECK_EQ(0, entry->skeleton.prefix1);

1316

DCHECK_EQ(0, entry->skeleton.prefix2);

1317

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1318

if (entry->skeleton.extra_opcode1 != 0) {

1319

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

1320

if (entry->skeleton.extra_opcode2 != 0) {

1321

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

1322

}

1323

} else {

1324

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1325

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1326

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1327

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1328

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1329

break;

1330

case kReg: // lir operands - 0: reg

1331

emitOpReg(cUnit, entry, lir->operands[0]);

1332

break;

1333

case kMem: // lir operands - 0: base, 1: disp

1334

emitOpMem(cUnit, entry, lir->operands[0], lir->operands[1]);

1335

break;

1336

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

1337

emitMemReg(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1338

break;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1339

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

1340

emitArrayReg(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

1341

lir->operands[3], lir->operands[4]);

1342

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1343

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

1344

emitRegMem(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1345

break;

1346

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

1347

emitRegArray(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

1348

lir->operands[3], lir->operands[4]);

1349

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1350

case kRegThread: // lir operands - 0: reg, 1: disp

1351

emitRegThread(cUnit, entry, lir->operands[0], lir->operands[1]);

1352

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1353

case kRegReg: // lir operands - 0: reg1, 1: reg2

1354

emitRegReg(cUnit, entry, lir->operands[0], lir->operands[1]);

1355

break;

jeffhao

2012-07-11 16:08:43 -0700

[diff] [blame]

1356

case kRegRegStore: // lir operands - 0: reg2, 1: reg1

1357

emitRegReg(cUnit, entry, lir->operands[1], lir->operands[0]);

1358

break;

Elliott Hughes

2012-04-16 20:21:45 -0700

[diff] [blame]

1359

case kRegRegImm:

1360

emitRegRegImm(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1361

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1362

case kRegImm: // lir operands - 0: reg, 1: immediate

1363

emitRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1364

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1365

case kThreadImm: // lir operands - 0: disp, 1: immediate

1366

emitThreadImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1367

break;

1368

case kMovRegImm: // lir operands - 0: reg, 1: immediate

1369

emitMovRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1370

break;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1371

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

1372

emitShiftRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1373

break;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1374

case kShiftRegCl: // lir operands - 0: reg, 1: cl

1375

emitShiftRegCl(cUnit, entry, lir->operands[0], lir->operands[1]);

1376

break;

1377

case kRegCond: // lir operands - 0: reg, 1: condition

1378

emitRegCond(cUnit, entry, lir->operands[0], lir->operands[1]);

1379

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1380

case kJmp: // lir operands - 0: rel

1381

emitJmp(cUnit, entry, lir->operands[0]);

1382

break;

1383

case kJcc: // lir operands - 0: rel, 1: CC, target assigned

1384

emitJcc(cUnit, entry, lir->operands[0], lir->operands[1]);

1385

break;

1386

case kCall:

Elliott Hughes

b25c3f6

2012-03-26 16:35:06 -0700

[diff] [blame]

1387

switch (entry->opcode) {

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1388

case kX86CallM: // lir operands - 0: base, 1: disp

1389

emitCallMem(cUnit, entry, lir->operands[0], lir->operands[1]);

1390

break;

1391

case kX86CallT: // lir operands - 0: disp

1392

emitCallThread(cUnit, entry, lir->operands[0]);

1393

break;

1394

default:

1395

emitUnimplemented(cUnit, entry, lir);

1396

break;

1397

}

1398

break;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1399

case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

1400

emitPcRel(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

1401

lir->operands[3], lir->operands[4]);

1402

break;

1403

case kMacro:

1404

emitMacro(cUnit, entry, lir->operands[0], lir->offset);

1405

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1406

default:

Ian Rogers

6cbb2bd

2012-03-16 13:45:30 -0700

[diff] [blame]

1407

emitUnimplemented(cUnit, entry, lir);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1408

break;

1409

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1410

CHECK_EQ(static_cast<size_t>(oatGetInsnSize(lir)),

1411

cUnit->codeBuffer.size() - starting_cbuf_size)

1412

<< "Instruction size mismatch for entry: " << EncodingMap[lir->opcode].name;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1413

}

1414

return res;

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1415

}

1416

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1417

/*

1418

* Target-dependent offset assignment.

1419

* independent.

1420

*/

1421

int oatAssignInsnOffsets(CompilationUnit* cUnit)

{

LIR* x86LIR;

int offset = 0;

buzbee

2012-11-17 14:11:25 -0800

[diff] [blame]

1426

for (x86LIR = cUnit->firstLIRInsn; x86LIR; x86LIR = NEXT_LIR(x86LIR)) {

buzbee