Blame - src/compiler/codegen/x86/Assemble.cc - platform_art

2012-03-06 22:14:17 -0800

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{ kX86 ## opname ## 16MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16MR", "[!0r+!1d],!2r" }, \

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{ kX86 ## opname ## 16AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \

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{ kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16TR", "fs:[!0d],!1r" }, \

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{ kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RR", "!0r,!1r" }, \

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{ kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \

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{ kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RT", "!0r,fs:[!1d]" }, \

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{ kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16TI", "fs:[!0d],!1d" }, \

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{ kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16RI8", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16MI8", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16TI8", "fs:[!0d],!1d" }, \

Ian Rogers

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jeffhao

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{ kX86 ## opname ## 32MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32MR", "[!0r+!1d],!2r" }, \

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{ kX86 ## opname ## 32AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \

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{ kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32TR", "fs:[!0d],!1r" }, \

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{ kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RR", "!0r,!1r" }, \

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{ kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \

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{ kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RT", "!0r,fs:[!1d]" }, \

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{ kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32TI", "fs:[!0d],!1d" }, \

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{ kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32RI8", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32MI8", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32TI8", "fs:[!0d],!1d" }

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ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */,

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0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */,

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0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */,

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0x80, 0x0 /* RegMem8/imm8 */,

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0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */),

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ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */,

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0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */,

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0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */,

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0x80, 0x1 /* RegMem8/imm8 */,

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0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */),

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ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,

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0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */,

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0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */,

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0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */,

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0x80, 0x2 /* RegMem8/imm8 */,

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0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */),

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ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,

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0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */,

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0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */,

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0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */,

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0x80, 0x3 /* RegMem8/imm8 */,

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0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */),

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ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */,

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0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */,

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0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */,

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0x80, 0x4 /* RegMem8/imm8 */,

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0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */),

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ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */,

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0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */,

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0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */,

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0x80, 0x5 /* RegMem8/imm8 */,

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0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */),

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ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */,

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0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */,

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0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */,

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0x80, 0x6 /* RegMem8/imm8 */,

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0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */),

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ENCODING_MAP(Cmp, IS_LOAD, 0, 0,

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0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */,

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0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */,

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0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */,

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0x80, 0x7 /* RegMem8/imm8 */,

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0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */),

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#undef ENCODING_MAP

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{ kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RRI", "!0r,!1r,!2d" },

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{ kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RMI", "!0r,[!1r+!2d],!3d" },

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{ kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },

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{ kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RRI", "!0r,!1r,!2d" },

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{ kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RMI", "!0r,[!1r+!2d],!3d" },

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{ kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },

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{ kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RRI8", "!0r,!1r,!2d" },

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{ kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" },

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{ kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" },

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jeffhao

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{ kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8MR", "[!0r+!1d],!2r" },

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{ kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8TR", "fs:[!0d],!1r" },

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{ kX86Mov8RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RR", "!0r,!1r" },

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{ kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RM", "!0r,[!1r+!2d]" },

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{ kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RT", "!0r,fs:[!1d]" },

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{ kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1 }, "Mov8RI", "!0r,!1d" },

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{ kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8MI", "[!0r+!1d],!2d" },

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{ kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8TI", "fs:[!0d],!1d" },

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{ kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16MR", "[!0r+!1d],!2r" },

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{ kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0 }, "Mov16TR", "fs:[!0d],!1r" },

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{ kX86Mov16RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RR", "!0r,!1r" },

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{ kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RM", "!0r,[!1r+!2d]" },

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{ kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RT", "!0r,fs:[!1d]" },

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{ kX86Mov16RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2 }, "Mov16RI", "!0r,!1d" },

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{ kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16MI", "[!0r+!1d],!2d" },

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{ kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2 }, "Mov16TI", "fs:[!0d],!1d" },

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{ kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32MR", "[!0r+!1d],!2r" },

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{ kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32TR", "fs:[!0d],!1r" },

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{ kX86Mov32RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RR", "!0r,!1r" },

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{ kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RM", "!0r,[!1r+!2d]" },

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{ kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RT", "!0r,fs:[!1d]" },

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{ kX86Mov32RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "Mov32RI", "!0r,!1d" },

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{ kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32MI", "[!0r+!1d],!2d" },

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{ kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32TI", "fs:[!0d],!1d" },

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{ kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \

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{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \

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{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \

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{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \

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{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }

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203

SHIFT_ENCODING_MAP(Rol, 0x0),

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SHIFT_ENCODING_MAP(Ror, 0x1),

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SHIFT_ENCODING_MAP(Rcl, 0x2),

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SHIFT_ENCODING_MAP(Rcr, 0x3),

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SHIFT_ENCODING_MAP(Sal, 0x4),

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SHIFT_ENCODING_MAP(Shr, 0x5),

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SHIFT_ENCODING_MAP(Sar, 0x7),

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#undef SHIFT_ENCODING_MAP

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{ kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0}, "Cmc", "" },

213

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{ kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" },

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{ kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" },

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{ kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" },

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{ kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" },

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{ kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" },

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{ kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" },

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{ kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \

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reg, reg_kind, reg_flags, \

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mem, mem_kind, mem_flags, \

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arr, arr_kind, arr_flags, imm, \

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b_flags, hw_flags, w_flags, \

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b_format, hw_format, w_format) \

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{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, #b_format "!0r" }, \

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{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, #b_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, #b_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, #hw_format "!0r" }, \

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{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, #hw_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, #hw_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, #w_format "!0r" }, \

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{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, #w_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, #w_format "[!0r+!1r<<!2d+!3d]" }

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UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

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UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

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#undef UNARY_ENCODING_MAP

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#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \

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{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

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{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

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EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),

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{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

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{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),

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{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

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{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0),

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EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0),

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284

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{ kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" },

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{ kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" },

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287

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EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),

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{ kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" },

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{ kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" },

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{ kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },

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292

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{ kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

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{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

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{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

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// TODO: load/store?

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// Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.

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{ kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },

300

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

301

EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES),

302

EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES),

jeffhao

8302576

2012-08-02 11:08:56 -0700

[diff] [blame]

303

304

{ kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" },

305

{ kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" },

306

{ kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

307

{ kX86LockCmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "!0r,!1r" },

308

{ kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" },

309

{ kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

310

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

311

EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),

312

EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),

313

EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),

314

EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

315

#undef EXT_0F_ENCODING_MAP

316

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

317

{ kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },

318

{ kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },

319

{ kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },

320

{ kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },

321

{ kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" },

322

{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

323

{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

324

{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

325

{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

326

{ kX86Ret, kNullary,NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

327

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

328

{ kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" },

329

{ kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },

330

{ kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" },

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

331

};

332

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

333

static size_t computeSize(X86EncodingMap* entry, int displacement, bool has_sib) {

334

size_t size = 0;

335

if (entry->skeleton.prefix1 > 0) {

336

++size;

337

if (entry->skeleton.prefix2 > 0) {

338

++size;

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

339

}

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

340

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

341

++size; // opcode

342

if (entry->skeleton.opcode == 0x0F) {

343

++size;

344

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

if (has_sib) {

++size;

}

if (displacement != 0) {

353

if (entry->opcode != kX86Lea32RA) {

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

354

DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0) << entry->name;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

355

}

356

size += IS_SIMM8(displacement) ? 1 : 4;

357

}

358

size += entry->skeleton.immediate_bytes;

return size;

}

int oatGetInsnSize(LIR* lir) {

363

X86EncodingMap* entry = &EncodingMap[lir->opcode];

364

switch (entry->kind) {

365

case kData:

366

return 4; // 4 bytes of data

367

case kNop:

368

return lir->operands[0]; // length of nop is sole operand

369

case kNullary:

370

return 1; // 1 byte of opcode

371

case kReg: // lir operands - 0: reg

372

return computeSize(entry, 0, false);

373

case kMem: { // lir operands - 0: base, 1: disp

374

int base = lir->operands[0];

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

375

int disp = lir->operands[1];

376

// SP requires a special extra SIB byte. BP requires explicit disp,

377

// so add a byte for disp 0 which would normally be omitted.

378

return computeSize(entry, disp, false) + ((base == rSP) || (base == rBP && disp == 0) ? 1 : 0);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

379

}

380

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

381

return computeSize(entry, lir->operands[3], true);

382

case kMemReg: { // lir operands - 0: base, 1: disp, 2: reg

383

int base = lir->operands[0];

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

384

int disp = lir->operands[1];

385

// SP requires a special extra SIB byte. BP requires explicit disp,

386

// so add a byte for disp 0 which would normally be omitted.

387

return computeSize(entry, disp, false) + ((base == rSP) || (base == rBP && disp == 0) ? 1 : 0);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

388

}

389

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

390

return computeSize(entry, lir->operands[3], true);

391

case kThreadReg: // lir operands - 0: disp, 1: reg

392

return computeSize(entry, lir->operands[0], false);

393

case kRegReg:

394

return computeSize(entry, 0, false);

jeffhao

2012-07-11 16:08:43 -0700

[diff] [blame]

395

case kRegRegStore:

396

return computeSize(entry, 0, false);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

397

case kRegMem: { // lir operands - 0: reg, 1: base, 2: disp

398

int base = lir->operands[1];

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

399

int disp = lir->operands[2];

400

// SP requires a special extra SIB byte. BP requires explicit disp,

401

// so add a byte for disp 0 which would normally be omitted.

402

return computeSize(entry, disp, false) + ((base == rSP) || (base == rBP && disp == 0) ? 1 : 0);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

403

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

404

case kRegArray: { // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

405

int base = lir->operands[1];

406

int disp = lir->operands[4];

407

// BP requires explicit disp, so add a byte for disp 0 which would normally be omitted.

408

return computeSize(entry, disp, true) + ((base == rBP && disp == 0) ? 1 : 0);

409

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

410

case kRegThread: // lir operands - 0: reg, 1: disp

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

411

return computeSize(entry, 0x12345678, false); // displacement size is always 32bit

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

412

case kRegImm: { // lir operands - 0: reg, 1: immediate

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

413

size_t size = computeSize(entry, 0, false);

414

if (entry->skeleton.ax_opcode == 0) {

415

return size;

416

} else {

417

// AX opcodes don't require the modrm byte.

418

int reg = lir->operands[0];

419

return size - (reg == rAX ? 1 : 0);

420

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

421

}

422

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

423

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

424

return computeSize(entry, lir->operands[1], false);

425

case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

426

return computeSize(entry, lir->operands[3], true);

427

case kThreadImm: // lir operands - 0: disp, 1: imm

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

428

return computeSize(entry, 0x12345678, false); // displacement size is always 32bit

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

429

case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

430

return computeSize(entry, 0, false);

431

case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

432

CHECK_NE(lir->operands[1], static_cast<int>(rSP)); // TODO: add extra SIB byte

433

return computeSize(entry, lir->operands[2], false);

434

case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

435

return computeSize(entry, lir->operands[4], true);

436

case kMovRegImm: // lir operands - 0: reg, 1: immediate

437

return 1 + entry->skeleton.immediate_bytes;

438

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

439

// Shift by immediate one has a shorter opcode.

440

return computeSize(entry, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

441

case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

442

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

443

// Shift by immediate one has a shorter opcode.

444

return computeSize(entry, lir->operands[1], false) - (lir->operands[2] == 1 ? 1 : 0);

445

case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

446

// Shift by immediate one has a shorter opcode.

447

return computeSize(entry, lir->operands[3], true) - (lir->operands[4] == 1 ? 1 : 0);

448

case kShiftRegCl:

449

return computeSize(entry, 0, false);

450

case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

451

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

452

return computeSize(entry, lir->operands[1], false);

453

case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

454

return computeSize(entry, lir->operands[3], true);

455

case kRegCond: // lir operands - 0: reg, 1: cond

456

return computeSize(entry, 0, false);

457

case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

458

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

459

return computeSize(entry, lir->operands[1], false);

460

case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

461

return computeSize(entry, lir->operands[3], true);

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

462

case kJcc:

463

if (lir->opcode == kX86Jcc8) {

464

return 2; // opcode + rel8

465

} else {

466

DCHECK(lir->opcode == kX86Jcc32);

467

return 6; // 2 byte opcode + rel32

468

}

469

case kJmp:

470

if (lir->opcode == kX86Jmp8) {

471

return 2; // opcode + rel8

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

472

} else if (lir->opcode == kX86Jmp32) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

473

return 5; // opcode + rel32

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

474

} else {

475

DCHECK(lir->opcode == kX86JmpR);

476

return 2; // opcode + modrm

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

477

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

478

case kCall:

Elliott Hughes

b25c3f6

2012-03-26 16:35:06 -0700

[diff] [blame]

479

switch (lir->opcode) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

480

case kX86CallR: return 2; // opcode modrm

481

case kX86CallM: // lir operands - 0: base, 1: disp

482

return computeSize(entry, lir->operands[1], false);

483

case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

484

return computeSize(entry, lir->operands[3], true);

Ian Rogers

6cbb2bd

2012-03-16 13:45:30 -0700

[diff] [blame]

485

case kX86CallT: // lir operands - 0: disp

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

486

return computeSize(entry, 0x12345678, false); // displacement size is always 32bit

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

default:

break;

}

break;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

491

case kPcRel:

492

if (entry->opcode == kX86PcRelLoadRA) {

493

// lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

494

return computeSize(entry, 0x12345678, true);

495

} else {

496

DCHECK(entry->opcode == kX86PcRelAdr);

497

return 5; // opcode with reg + 4 byte immediate

498

}

499

case kMacro:

500

DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));

501

return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +

502

computeSize(&EncodingMap[kX86Sub32RI], 0, false) -

503

(lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

508

return 0;

509

}

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

510

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

511

static uint8_t modrmForDisp(int base, int disp) {

512

// BP requires an explicit disp, so do not omit it in the 0 case

513

if (disp == 0 && base != rBP) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

514

return 0;

515

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

522

static void emitDisp(CompilationUnit* cUnit, int base, int disp) {

523

// BP requires an explicit disp, so do not omit it in the 0 case

524

if (disp == 0 && base != rBP) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

525

return;

526

} else if (IS_SIMM8(disp)) {

527

cUnit->codeBuffer.push_back(disp & 0xFF);

528

} else {

529

cUnit->codeBuffer.push_back(disp & 0xFF);

530

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

531

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

532

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

}

}

static void emitOpReg(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg) {

537

if (entry->skeleton.prefix1 != 0) {

538

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

539

if (entry->skeleton.prefix2 != 0) {

540

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

541

}

542

} else {

543

DCHECK_EQ(0, entry->skeleton.prefix2);

544

}

545

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

546

if (entry->skeleton.opcode == 0x0F) {

547

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

548

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

549

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

550

} else {

551

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

552

}

553

} else {

554

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

555

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

556

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

557

if (FPREG(reg)) {

558

reg = reg & FP_REG_MASK;

559

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

560

if (reg >= 4) {

561

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg

562

<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);

563

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

564

DCHECK_LT(reg, 8);

565

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

566

cUnit->codeBuffer.push_back(modrm);

567

DCHECK_EQ(0, entry->skeleton.ax_opcode);

568

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

569

}

570

571

static void emitOpMem(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t base, int disp) {

572

if (entry->skeleton.prefix1 != 0) {

573

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

574

if (entry->skeleton.prefix2 != 0) {

575

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

576

}

577

} else {

578

DCHECK_EQ(0, entry->skeleton.prefix2);

579

}

580

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

581

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

582

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

583

DCHECK_LT(entry->skeleton.modrm_opcode, 8);

584

DCHECK_LT(base, 8);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

585

uint8_t modrm = (modrmForDisp(base, disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

586

cUnit->codeBuffer.push_back(modrm);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

587

emitDisp(cUnit, base, disp);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

588

DCHECK_EQ(0, entry->skeleton.ax_opcode);

589

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

590

}

591

592

static void emitMemReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

593

uint8_t base, int disp, uint8_t reg) {

594

if (entry->skeleton.prefix1 != 0) {

595

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

596

if (entry->skeleton.prefix2 != 0) {

597

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

598

}

599

} else {

600

DCHECK_EQ(0, entry->skeleton.prefix2);

601

}

602

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

603

if (entry->skeleton.opcode == 0x0F) {

604

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

605

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

606

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

607

} else {

608

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

609

}

610

} else {

611

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

612

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

613

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

614

if (FPREG(reg)) {

615

reg = reg & FP_REG_MASK;

616

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

617

if (reg >= 4) {

618

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg

619

<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);

620

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

621

DCHECK_LT(reg, 8);

622

DCHECK_LT(base, 8);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

623

uint8_t modrm = (modrmForDisp(base, disp) << 6) | (reg << 3) | base;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

624

cUnit->codeBuffer.push_back(modrm);

625

if (base == rSP) {

626

// Special SIB for SP base

627

cUnit->codeBuffer.push_back(0 << 6 | (rSP << 3) | rSP);

628

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

629

emitDisp(cUnit, base, disp);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

630

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

631

DCHECK_EQ(0, entry->skeleton.ax_opcode);

632

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

633

}

634

635

static void emitRegMem(CompilationUnit* cUnit, const X86EncodingMap* entry,

636

uint8_t reg, uint8_t base, int disp) {

637

// Opcode will flip operands.

638

emitMemReg(cUnit, entry, base, disp, reg);

639

}

640

641

static void emitRegArray(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg,

642

uint8_t base, uint8_t index, int scale, int disp) {

643

if (entry->skeleton.prefix1 != 0) {

644

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

645

if (entry->skeleton.prefix2 != 0) {

646

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

647

}

648

} else {

649

DCHECK_EQ(0, entry->skeleton.prefix2);

650

}

651

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

652

if (entry->skeleton.opcode == 0x0F) {

653

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

654

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

655

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

656

} else {

657

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

658

}

659

} else {

660

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

661

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

662

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

663

if (FPREG(reg)) {

664

reg = reg & FP_REG_MASK;

665

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

666

DCHECK_LT(reg, 8);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

667

uint8_t modrm = (modrmForDisp(base, disp) << 6) | (reg << 3) | rSP;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

668

cUnit->codeBuffer.push_back(modrm);

DCHECK_LT(scale, 4);

DCHECK_LT(index, 8);

DCHECK_LT(base, 8);

uint8_t sib = (scale << 6) | (index << 3) | base;

673

cUnit->codeBuffer.push_back(sib);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

674

emitDisp(cUnit, base, disp);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

675

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

676

DCHECK_EQ(0, entry->skeleton.ax_opcode);

677

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

678

}

679

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

680

static void emitArrayReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

681

uint8_t base, uint8_t index, int scale, int disp, uint8_t reg) {

682

// Opcode will flip operands.

683

emitRegArray(cUnit, entry, reg, base, index, scale, disp);

684

}

685

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

686

static void emitRegThread(CompilationUnit* cUnit, const X86EncodingMap* entry,

687

uint8_t reg, int disp) {

688

DCHECK_NE(entry->skeleton.prefix1, 0);

689

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

690

if (entry->skeleton.prefix2 != 0) {

691

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

692

}

693

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

694

if (entry->skeleton.opcode == 0x0F) {

695

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

696

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

697

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

698

} else {

699

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

700

}

701

} else {

702

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

703

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

704

}

705

if (FPREG(reg)) {

706

reg = reg & FP_REG_MASK;

707

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

708

if (reg >= 4) {

709

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg

710

<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);

711

}

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

712

DCHECK_LT(reg, 8);

713

uint8_t modrm = (0 << 6) | (reg << 3) | rBP;

714

cUnit->codeBuffer.push_back(modrm);

715

cUnit->codeBuffer.push_back(disp & 0xFF);

716

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

717

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

718

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

719

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

720

DCHECK_EQ(0, entry->skeleton.ax_opcode);

721

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

722

}

723

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

724

static void emitRegReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

725

uint8_t reg1, uint8_t reg2) {

726

if (entry->skeleton.prefix1 != 0) {

727

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

728

if (entry->skeleton.prefix2 != 0) {

729

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

730

}

731

} else {

732

DCHECK_EQ(0, entry->skeleton.prefix2);

733

}

734

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

735

if (entry->skeleton.opcode == 0x0F) {

736

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

737

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

738

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

739

} else {

740

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

741

}

742

} else {

743

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

744

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

745

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

746

if (FPREG(reg1)) {

747

reg1 = reg1 & FP_REG_MASK;

748

}

749

if (FPREG(reg2)) {

750

reg2 = reg2 & FP_REG_MASK;

751

}

752

DCHECK_LT(reg1, 8);

753

DCHECK_LT(reg2, 8);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

754

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

755

cUnit->codeBuffer.push_back(modrm);

756

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

757

DCHECK_EQ(0, entry->skeleton.ax_opcode);

758

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

759

}

760

Elliott Hughes

225ae52

2012-04-16 20:21:45 -0700

[diff] [blame]

761

static void emitRegRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

762

uint8_t reg1, uint8_t reg2, int32_t imm) {

763

if (entry->skeleton.prefix1 != 0) {

764

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

765

if (entry->skeleton.prefix2 != 0) {

766

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

767

}

768

} else {

769

DCHECK_EQ(0, entry->skeleton.prefix2);

770

}

771

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

772

if (entry->skeleton.opcode == 0x0F) {

773

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

774

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

775

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

776

} else {

777

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

778

}

779

} else {

780

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

781

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

782

}

783

if (FPREG(reg1)) {

784

reg1 = reg1 & FP_REG_MASK;

785

}

786

if (FPREG(reg2)) {

787

reg2 = reg2 & FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

792

cUnit->codeBuffer.push_back(modrm);

793

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

794

DCHECK_EQ(0, entry->skeleton.ax_opcode);

795

switch (entry->skeleton.immediate_bytes) {

796

case 1:

797

DCHECK(IS_SIMM8(imm));

798

cUnit->codeBuffer.push_back(imm & 0xFF);

799

break;

800

case 2:

801

DCHECK(IS_SIMM16(imm));

802

cUnit->codeBuffer.push_back(imm & 0xFF);

803

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

804

break;

805

case 4:

806

cUnit->codeBuffer.push_back(imm & 0xFF);

807

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

808

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

809

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

810

break;

811

default:

812

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

813

<< ") for instruction: " << entry->name;

break;

}

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

818

static void emitRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

819

uint8_t reg, int imm) {

820

if (entry->skeleton.prefix1 != 0) {

821

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

822

if (entry->skeleton.prefix2 != 0) {

823

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

824

}

825

} else {

826

DCHECK_EQ(0, entry->skeleton.prefix2);

827

}

828

if (reg == rAX && entry->skeleton.ax_opcode != 0) {

829

cUnit->codeBuffer.push_back(entry->skeleton.ax_opcode);

830

} else {

831

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

832

if (entry->skeleton.opcode == 0x0F) {

833

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

834

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

835

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

836

} else {

837

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

838

}

839

} else {

840

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

841

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

842

}

jeffhao

2012-07-11 16:08:43 -0700

[diff] [blame]

843

if (FPREG(reg)) {

844

reg = reg & FP_REG_MASK;

845

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

846

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

847

cUnit->codeBuffer.push_back(modrm);

848

}

849

switch (entry->skeleton.immediate_bytes) {

850

case 1:

851

DCHECK(IS_SIMM8(imm));

852

cUnit->codeBuffer.push_back(imm & 0xFF);

853

break;

854

case 2:

855

DCHECK(IS_SIMM16(imm));

856

cUnit->codeBuffer.push_back(imm & 0xFF);

857

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

858

break;

859

case 4:

860

cUnit->codeBuffer.push_back(imm & 0xFF);

861

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

862

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

863

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

864

break;

865

default:

866

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

867

<< ") for instruction: " << entry->name;

break;

}

}

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

872

static void emitThreadImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

873

int disp, int imm) {

874

if (entry->skeleton.prefix1 != 0) {

875

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

876

if (entry->skeleton.prefix2 != 0) {

877

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

878

}

879

} else {

880

DCHECK_EQ(0, entry->skeleton.prefix2);

881

}

882

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

883

if (entry->skeleton.opcode == 0x0F) {

884

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

885

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

886

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

887

} else {

888

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

889

}

890

} else {

891

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

892

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

893

}

894

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

895

cUnit->codeBuffer.push_back(modrm);

896

cUnit->codeBuffer.push_back(disp & 0xFF);

897

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

898

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

899

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

900

switch (entry->skeleton.immediate_bytes) {

901

case 1:

902

DCHECK(IS_SIMM8(imm));

903

cUnit->codeBuffer.push_back(imm & 0xFF);

904

break;

905

case 2:

906

DCHECK(IS_SIMM16(imm));

907

cUnit->codeBuffer.push_back(imm & 0xFF);

908

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

909

break;

910

case 4:

911

cUnit->codeBuffer.push_back(imm & 0xFF);

912

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

913

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

914

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

915

break;

916

default:

917

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

918

<< ") for instruction: " << entry->name;

919

break;

920

}

921

DCHECK_EQ(entry->skeleton.ax_opcode, 0);

922

}

923

924

static void emitMovRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

925

uint8_t reg, int imm) {

926

DCHECK_LT(reg, 8);

927

cUnit->codeBuffer.push_back(0xB8 + reg);

928

cUnit->codeBuffer.push_back(imm & 0xFF);

929

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

930

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

931

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

932

}

933

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

934

static void emitShiftRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

935

uint8_t reg, int imm) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

936

if (entry->skeleton.prefix1 != 0) {

937

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

938

if (entry->skeleton.prefix2 != 0) {

939

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

940

}

941

} else {

942

DCHECK_EQ(0, entry->skeleton.prefix2);

943

}

944

if (imm != 1) {

945

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

946

} else {

947

// Shorter encoding for 1 bit shift

948

cUnit->codeBuffer.push_back(entry->skeleton.ax_opcode);

949

}

950

if (entry->skeleton.opcode == 0x0F) {

951

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

952

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

953

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

954

} else {

955

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

956

}

957

} else {

958

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

959

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

960

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

961

if (reg >= 4) {

962

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg

963

<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);

964

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

965

DCHECK_LT(reg, 8);

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

966

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

967

cUnit->codeBuffer.push_back(modrm);

968

if (imm != 1) {

969

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

970

DCHECK(IS_SIMM8(imm));

971

cUnit->codeBuffer.push_back(imm & 0xFF);

}

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

975

static void emitShiftRegCl(CompilationUnit* cUnit, const X86EncodingMap* entry,

976

uint8_t reg, uint8_t cl) {

977

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

978

if (entry->skeleton.prefix1 != 0) {

979

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

980

if (entry->skeleton.prefix2 != 0) {

981

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

982

}

983

} else {

984

DCHECK_EQ(0, entry->skeleton.prefix2);

985

}

986

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

987

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

988

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

989

DCHECK_LT(reg, 8);

990

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

991

cUnit->codeBuffer.push_back(modrm);

992

DCHECK_EQ(0, entry->skeleton.ax_opcode);

993

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

994

}

995

996

static void emitRegCond(CompilationUnit* cUnit, const X86EncodingMap* entry,

997

uint8_t reg, uint8_t condition) {

998

if (entry->skeleton.prefix1 != 0) {

999

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

1000

if (entry->skeleton.prefix2 != 0) {

1001

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1002

}

1003

} else {

1004

DCHECK_EQ(0, entry->skeleton.prefix2);

1005

}

1006

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1007

DCHECK_EQ(0x0F, entry->skeleton.opcode);

1008

cUnit->codeBuffer.push_back(0x0F);

1009

DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);

1010

cUnit->codeBuffer.push_back(0x90 | condition);

1011

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1012

DCHECK_LT(reg, 8);

1013

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

1014

cUnit->codeBuffer.push_back(modrm);

1015

DCHECK_EQ(entry->skeleton.immediate_bytes, 0);

1016

}

1017

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1018

static void emitJmp(CompilationUnit* cUnit, const X86EncodingMap* entry, int rel) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1019

if (entry->opcode == kX86Jmp8) {

1020

DCHECK(IS_SIMM8(rel));

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1021

cUnit->codeBuffer.push_back(0xEB);

1022

cUnit->codeBuffer.push_back(rel & 0xFF);

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1023

} else if (entry->opcode == kX86Jmp32) {

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1024

cUnit->codeBuffer.push_back(0xE9);

1025

cUnit->codeBuffer.push_back(rel & 0xFF);

1026

cUnit->codeBuffer.push_back((rel >> 8) & 0xFF);

1027

cUnit->codeBuffer.push_back((rel >> 16) & 0xFF);

1028

cUnit->codeBuffer.push_back((rel >> 24) & 0xFF);

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1029

} else {

1030

DCHECK(entry->opcode == kX86JmpR);

1031

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1032

uint8_t reg = static_cast<uint8_t>(rel);

1033

DCHECK_LT(reg, 8);

1034

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

1035

cUnit->codeBuffer.push_back(modrm);

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

}

}

static void emitJcc(CompilationUnit* cUnit, const X86EncodingMap* entry,

1040

int rel, uint8_t cc) {

1041

DCHECK_LT(cc, 16);

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1042

if (entry->opcode == kX86Jcc8) {

1043

DCHECK(IS_SIMM8(rel));

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1044

cUnit->codeBuffer.push_back(0x70 | cc);

1045

cUnit->codeBuffer.push_back(rel & 0xFF);

1046

} else {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1047

DCHECK(entry->opcode == kX86Jcc32);

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1048

cUnit->codeBuffer.push_back(0x0F);

1049

cUnit->codeBuffer.push_back(0x80 | cc);

1050

cUnit->codeBuffer.push_back(rel & 0xFF);

1051

cUnit->codeBuffer.push_back((rel >> 8) & 0xFF);

1052

cUnit->codeBuffer.push_back((rel >> 16) & 0xFF);

1053

cUnit->codeBuffer.push_back((rel >> 24) & 0xFF);

}

}

static void emitCallMem(CompilationUnit* cUnit, const X86EncodingMap* entry,

1058

uint8_t base, int disp) {

1059

if (entry->skeleton.prefix1 != 0) {

1060

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

1061

if (entry->skeleton.prefix2 != 0) {

1062

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1063

}

1064

} else {

1065

DCHECK_EQ(0, entry->skeleton.prefix2);

1066

}

1067

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1068

if (entry->skeleton.opcode == 0x0F) {

1069

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

1070

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

1071

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

1072

} else {

1073

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1074

}

1075

} else {

1076

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1077

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1078

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

1079

uint8_t modrm = (modrmForDisp(base, disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1080

cUnit->codeBuffer.push_back(modrm);

1081

if (base == rSP) {

1082

// Special SIB for SP base

1083

cUnit->codeBuffer.push_back(0 << 6 | (rSP << 3) | rSP);

1084

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

1085

emitDisp(cUnit, base, disp);

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1086

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1087

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1088

}

1089

1090

static void emitCallThread(CompilationUnit* cUnit, const X86EncodingMap* entry, int disp) {

1091

DCHECK_NE(entry->skeleton.prefix1, 0);

1092

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

1093

if (entry->skeleton.prefix2 != 0) {

1094

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1095

}

1096

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1097

if (entry->skeleton.opcode == 0x0F) {

1098

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

1099

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

1100

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

1101

} else {

1102

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1103

}

1104

} else {

1105

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1106

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1107

}

1108

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

1109

cUnit->codeBuffer.push_back(modrm);

1110

cUnit->codeBuffer.push_back(disp & 0xFF);

1111

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

1112

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

1113

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

1114

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1115

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1116

}

1117

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1118

static void emitPcRel(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg,

1119

int base_or_table, uint8_t index, int scale, int table_or_disp) {

1120

int disp;

1121

if (entry->opcode == kX86PcRelLoadRA) {

1122

SwitchTable *tabRec = (SwitchTable*)table_or_disp;

1123

disp = tabRec->offset;

1124

} else {

1125

DCHECK(entry->opcode == kX86PcRelAdr);

1126

FillArrayData *tabRec = (FillArrayData *)base_or_table;

1127

disp = tabRec->offset;

1128

}

1129

if (entry->skeleton.prefix1 != 0) {

1130

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

1131

if (entry->skeleton.prefix2 != 0) {

1132

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1133

}

1134

} else {

1135

DCHECK_EQ(0, entry->skeleton.prefix2);

1136

}

1137

if (FPREG(reg)) {

1138

reg = reg & FP_REG_MASK;

1139

}

1140

DCHECK_LT(reg, 8);

1141

if (entry->opcode == kX86PcRelLoadRA) {

1142

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1143

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1144

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1145

uint8_t modrm = (2 << 6) | (reg << 3) | rSP;

1146

cUnit->codeBuffer.push_back(modrm);

1147

DCHECK_LT(scale, 4);

1148

DCHECK_LT(index, 8);

1149

DCHECK_LT(base_or_table, 8);

1150

uint8_t base = static_cast<uint8_t>(base_or_table);

1151

uint8_t sib = (scale << 6) | (index << 3) | base;

1152

cUnit->codeBuffer.push_back(sib);

1153

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1154

} else {

1155

cUnit->codeBuffer.push_back(entry->skeleton.opcode + reg);

1156

}

1157

cUnit->codeBuffer.push_back(disp & 0xFF);

1158

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

1159

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

1160

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

1161

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1162

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1163

}

1164

1165

static void emitMacro(CompilationUnit* cUnit, const X86EncodingMap* entry,

1166

uint8_t reg, int offset) {

1167

DCHECK(entry->opcode == kX86StartOfMethod) << entry->name;

1168

cUnit->codeBuffer.push_back(0xE8); // call +0

1169

cUnit->codeBuffer.push_back(0);

1170

cUnit->codeBuffer.push_back(0);

1171

cUnit->codeBuffer.push_back(0);

1172

cUnit->codeBuffer.push_back(0);

1173

1174

DCHECK_LT(reg, 8);

1175

cUnit->codeBuffer.push_back(0x58 + reg); // pop reg

1176

1177

emitRegImm(cUnit, &EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */);

1178

}

1179

Ian Rogers

6cbb2bd

2012-03-16 13:45:30 -0700

[diff] [blame]

1180

void emitUnimplemented(CompilationUnit* cUnit, const X86EncodingMap* entry, LIR* lir) {

Elliott Hughes

225ae52

2012-04-16 20:21:45 -0700

[diff] [blame]

1181

UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " " << buildInsnString(entry->fmt, lir, 0);

Ian Rogers

141b0c7

2012-03-15 18:18:52 -0700

[diff] [blame]

1182

for (int i = 0; i < oatGetInsnSize(lir); ++i) {

1183

cUnit->codeBuffer.push_back(0xCC); // push breakpoint instruction - int 3

}

}

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1187

/*

1188

* Assemble the LIR into binary instruction format. Note that we may

1189

* discover that pc-relative displacements may not fit the selected

1190

* instruction. In those cases we will try to substitute a new code

1191

* sequence or request that the trace be shortened and retried.

1192

*/

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1193

AssemblerStatus oatAssembleInstructions(CompilationUnit *cUnit, intptr_t startAddr) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1194

LIR *lir;

1195

AssemblerStatus res = kSuccess; // Assume success

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1196

Ian Rogers

141d622

2012-04-05 12:23:06 -0700

[diff] [blame]

1197

const bool kVerbosePcFixup = false;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1198

for (lir = (LIR *) cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {

1199

if (lir->opcode < 0) {

1200

continue;

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1201

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1202

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1203

if (lir->flags.isNop) {

continue;

}

if (lir->flags.pcRelFixup) {

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1208

switch (lir->opcode) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1209

case kX86Jcc8: {

1210

LIR *targetLIR = lir->target;

1211

DCHECK(targetLIR != NULL);

1212

int delta = 0;

1213

intptr_t pc;

1214

if (IS_SIMM8(lir->operands[0])) {

1215

pc = lir->offset + 2 /* opcode + rel8 */;

1216

} else {

1217

pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1218

}

1219

intptr_t target = targetLIR->offset;

1220

delta = target - pc;

1221

if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1222

if (kVerbosePcFixup) {

1223

LOG(INFO) << "Retry for JCC growth at " << lir->offset

1224

<< " delta: " << delta << " old delta: " << lir->operands[0];

1225

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1226

lir->opcode = kX86Jcc32;

1227

oatSetupResourceMasks(lir);

1228

res = kRetryAll;

1229

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1230

if (kVerbosePcFixup) {

1231

LOG(INFO) << "Source:";

1232

oatDumpLIRInsn(cUnit, lir, 0);

1233

LOG(INFO) << "Target:";

1234

oatDumpLIRInsn(cUnit, targetLIR, 0);

1235

LOG(INFO) << "Delta " << delta;

1236

}

1237

lir->operands[0] = delta;

break;

}

case kX86Jcc32: {

LIR *targetLIR = lir->target;

1242

DCHECK(targetLIR != NULL);

1243

intptr_t pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1244

intptr_t target = targetLIR->offset;

1245

int delta = target - pc;

1246

if (kVerbosePcFixup) {

1247

LOG(INFO) << "Source:";

1248

oatDumpLIRInsn(cUnit, lir, 0);

1249

LOG(INFO) << "Target:";

1250

oatDumpLIRInsn(cUnit, targetLIR, 0);

1251

LOG(INFO) << "Delta " << delta;

1252

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1253

lir->operands[0] = delta;

1254

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1255

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1256

case kX86Jmp8: {

1257

LIR *targetLIR = lir->target;

1258

DCHECK(targetLIR != NULL);

1259

int delta = 0;

1260

intptr_t pc;

1261

if (IS_SIMM8(lir->operands[0])) {

1262

pc = lir->offset + 2 /* opcode + rel8 */;

1263

} else {

1264

pc = lir->offset + 5 /* opcode + rel32 */;

1265

}

1266

intptr_t target = targetLIR->offset;

1267

delta = target - pc;

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

1268

if (!(cUnit->disableOpt & (1 << kSafeOptimizations)) && delta == 0) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1269

// Useless branch

1270

lir->flags.isNop = true;

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1271

if (kVerbosePcFixup) {

1272

LOG(INFO) << "Retry for useless branch at " << lir->offset;

1273

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1274

res = kRetryAll;

1275

} else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1276

if (kVerbosePcFixup) {

1277

LOG(INFO) << "Retry for JMP growth at " << lir->offset;

1278

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1279

lir->opcode = kX86Jmp32;

1280

oatSetupResourceMasks(lir);

1281

res = kRetryAll;

1282

}

1283

lir->operands[0] = delta;

1284

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1285

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1286

case kX86Jmp32: {

1287

LIR *targetLIR = lir->target;

1288

DCHECK(targetLIR != NULL);

1289

intptr_t pc = lir->offset + 5 /* opcode + rel32 */;

1290

intptr_t target = targetLIR->offset;

1291

int delta = target - pc;

1292

lir->operands[0] = delta;

1293

break;

1294

}

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1295

default:

1296

break;

1297

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

}

/*

* If one of the pc-relative instructions expanded we'll have

1302

* to make another pass. Don't bother to fully assemble the

1303

* instruction.

1304

*/

1305

if (res != kSuccess) {

1306

continue;

1307

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1308

CHECK_EQ(static_cast<size_t>(lir->offset), cUnit->codeBuffer.size());

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1309

const X86EncodingMap *entry = &EncodingMap[lir->opcode];

Ian Rogers

141b0c7

2012-03-15 18:18:52 -0700

[diff] [blame]

1310

size_t starting_cbuf_size = cUnit->codeBuffer.size();

Elliott Hughes

b25c3f6

2012-03-26 16:35:06 -0700

[diff] [blame]

1311

switch (entry->kind) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1312

case kData: // 4 bytes of data

1313

cUnit->codeBuffer.push_back(lir->operands[0]);

1314

break;

1315

case kNullary: // 1 byte of opcode

1316

DCHECK_EQ(0, entry->skeleton.prefix1);

1317

DCHECK_EQ(0, entry->skeleton.prefix2);

1318

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1319

if (entry->skeleton.extra_opcode1 != 0) {

1320

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

1321

if (entry->skeleton.extra_opcode2 != 0) {

1322

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

1323

}

1324

} else {

1325

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1326

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1327

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1328

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1329

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1330

break;

1331

case kReg: // lir operands - 0: reg

1332

emitOpReg(cUnit, entry, lir->operands[0]);

1333

break;

1334

case kMem: // lir operands - 0: base, 1: disp

1335

emitOpMem(cUnit, entry, lir->operands[0], lir->operands[1]);

1336

break;

1337

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

1338

emitMemReg(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1339

break;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1340

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

1341

emitArrayReg(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

1342

lir->operands[3], lir->operands[4]);

1343

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1344

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

1345

emitRegMem(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1346

break;

1347

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

1348

emitRegArray(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

1349

lir->operands[3], lir->operands[4]);

1350

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1351

case kRegThread: // lir operands - 0: reg, 1: disp

1352

emitRegThread(cUnit, entry, lir->operands[0], lir->operands[1]);

1353

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1354

case kRegReg: // lir operands - 0: reg1, 1: reg2

1355

emitRegReg(cUnit, entry, lir->operands[0], lir->operands[1]);

1356

break;

jeffhao

2012-07-11 16:08:43 -0700

[diff] [blame]

1357

case kRegRegStore: // lir operands - 0: reg2, 1: reg1

1358

emitRegReg(cUnit, entry, lir->operands[1], lir->operands[0]);

1359

break;

Elliott Hughes

225ae52

2012-04-16 20:21:45 -0700

[diff] [blame]

1360

case kRegRegImm:

1361

emitRegRegImm(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1362

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1363

case kRegImm: // lir operands - 0: reg, 1: immediate

1364

emitRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1365

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1366

case kThreadImm: // lir operands - 0: disp, 1: immediate

1367

emitThreadImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1368

break;

1369

case kMovRegImm: // lir operands - 0: reg, 1: immediate

1370

emitMovRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1371

break;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1372

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

1373

emitShiftRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1374

break;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1375

case kShiftRegCl: // lir operands - 0: reg, 1: cl

1376

emitShiftRegCl(cUnit, entry, lir->operands[0], lir->operands[1]);

1377

break;

1378

case kRegCond: // lir operands - 0: reg, 1: condition

1379

emitRegCond(cUnit, entry, lir->operands[0], lir->operands[1]);

1380

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1381

case kJmp: // lir operands - 0: rel

1382

emitJmp(cUnit, entry, lir->operands[0]);

1383

break;

1384

case kJcc: // lir operands - 0: rel, 1: CC, target assigned

1385

emitJcc(cUnit, entry, lir->operands[0], lir->operands[1]);

1386

break;

1387

case kCall:

Elliott Hughes

b25c3f6

2012-03-26 16:35:06 -0700

[diff] [blame]

1388

switch (entry->opcode) {

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1389

case kX86CallM: // lir operands - 0: base, 1: disp

1390

emitCallMem(cUnit, entry, lir->operands[0], lir->operands[1]);

1391

break;

1392

case kX86CallT: // lir operands - 0: disp

1393

emitCallThread(cUnit, entry, lir->operands[0]);

1394

break;

1395

default:

1396

emitUnimplemented(cUnit, entry, lir);

1397

break;

1398

}

1399

break;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1400

case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

1401

emitPcRel(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

1402

lir->operands[3], lir->operands[4]);

1403

break;

1404

case kMacro:

1405

emitMacro(cUnit, entry, lir->operands[0], lir->offset);

1406

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1407

default:

Ian Rogers

6cbb2bd

2012-03-16 13:45:30 -0700

[diff] [blame]

1408

emitUnimplemented(cUnit, entry, lir);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1409

break;

1410

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1411

CHECK_EQ(static_cast<size_t>(oatGetInsnSize(lir)),

1412

cUnit->codeBuffer.size() - starting_cbuf_size)

1413

<< "Instruction size mismatch for entry: " << EncodingMap[lir->opcode].name;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1414

}

1415

return res;

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1416

}

1417

buzbee