Blame - compiler/dex/quick/x86/assemble_x86.cc - platform_art

2013-12-20 17:27:23 -0800

[diff] [blame]

180

{ kX86Cmov32RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, {0, 0, 0x0F, 0x40, 0, 0, 0, 0}, "Cmovcc32RR", "!2c !0r,!1r" },

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Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \

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{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \

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{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \

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{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \

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{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }

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SHIFT_ENCODING_MAP(Rol, 0x0),

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SHIFT_ENCODING_MAP(Ror, 0x1),

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SHIFT_ENCODING_MAP(Rcl, 0x2),

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SHIFT_ENCODING_MAP(Rcr, 0x3),

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SHIFT_ENCODING_MAP(Sal, 0x4),

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SHIFT_ENCODING_MAP(Shr, 0x5),

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SHIFT_ENCODING_MAP(Sar, 0x7),

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#undef SHIFT_ENCODING_MAP

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{ kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0}, "Cmc", "" },

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{ kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" },

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{ kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" },

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{ kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" },

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{ kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" },

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{ kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" },

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{ kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" },

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{ kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0}, "Test32RR", "!0r,!1r" },

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#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \

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reg, reg_kind, reg_flags, \

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mem, mem_kind, mem_flags, \

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arr, arr_kind, arr_flags, imm, \

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b_flags, hw_flags, w_flags, \

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b_format, hw_format, w_format) \

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{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, #b_format "!0r" }, \

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{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, #b_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, #b_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, #hw_format "!0r" }, \

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{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, #hw_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, #hw_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, #w_format "!0r" }, \

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{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, #w_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, #w_format "[!0r+!1r<<!2d+!3d]" }

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UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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Mark Mendell

2bf31e6

2014-01-23 12:13:40 -0800

[diff] [blame]

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UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

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UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#undef UNARY_ENCODING_MAP

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Mark Mendell

2bf31e6

2014-01-23 12:13:40 -0800

[diff] [blame]

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{ kx86Cdq32Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { 0, 0, 0x99, 0, 0, 0, 0, 0 }, "Cdq", "" },

Vladimir Marko

a6fd8ba

2013-12-13 10:53:49 +0000

[diff] [blame]

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{ kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0 }, "Bswap32R", "!0r" },

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{ kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0 }, "Push32R", "!0r" },

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{ kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0 }, "Pop32R", "!0r" },

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

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Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \

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{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

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{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

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EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),

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{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

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{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),

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{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

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{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0),

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EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0),

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{ kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" },

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{ kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" },

Mark Mendell

bff1ef0

2013-12-13 13:47:34 -0800

[diff] [blame]

294

{ kX86SqrtsdRR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0xF2, 0, 0x0F, 0x51, 0, 0, 0, 0 }, "SqrtsdRR", "!0r,!1r" },

Vladimir Marko

12f9628

2013-12-16 14:44:03 +0000

[diff] [blame]

295

{ kX86FstpdM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0 }, "FstpdM", "[!0r,!1d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),

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{ kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" },

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{ kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" },

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{ kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

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{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

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{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

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// TODO: load/store?

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// Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.

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{ kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },

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EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES),

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EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES),

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{ kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" },

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{ kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" },

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{ kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

316

{ kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" },

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{ kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Vladimir Marko

70b797d

2013-12-03 15:25:24 +0000

[diff] [blame]

318

{ kX86LockCmpxchg8bM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1d]" },

319

{ kX86LockCmpxchg8bA, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

320

321

EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),

322

EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),

323

EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),

324

EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),

325

#undef EXT_0F_ENCODING_MAP

326

327

{ kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },

328

{ kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },

329

{ kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },

330

{ kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },

331

{ kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" },

332

{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

333

{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

334

{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

335

{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

Brian Carlstrom

b1eba21

2013-07-17 18:07:19 -0700

[diff] [blame]

336

{ kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

337

338

{ kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" },

339

{ kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },

340

{ kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" },

341

};

342

343

static size_t ComputeSize(const X86EncodingMap* entry, int base, int displacement, bool has_sib) {

344

size_t size = 0;

345

if (entry->skeleton.prefix1 > 0) {

346

++size;

347

if (entry->skeleton.prefix2 > 0) {

++size;

}

}

++size; // opcode

if (entry->skeleton.opcode == 0x0F) {

353

++size;

354

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

if (has_sib || base == rX86_SP) {

360

// SP requires a SIB byte.

361

++size;

362

}

363

if (displacement != 0 || base == rBP) {

364

// BP requires an explicit displacement, even when it's 0.

365

if (entry->opcode != kX86Lea32RA) {

366

DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name;

367

}

368

size += IS_SIMM8(displacement) ? 1 : 4;

369

}

370

size += entry->skeleton.immediate_bytes;

return size;

}

int X86Mir2Lir::GetInsnSize(LIR* lir) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

375

DCHECK(!IsPseudoLirOp(lir->opcode));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

376

const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode];

377

switch (entry->kind) {

378

case kData:

379

return 4; // 4 bytes of data

380

case kNop:

381

return lir->operands[0]; // length of nop is sole operand

382

case kNullary:

383

return 1; // 1 byte of opcode

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

384

case kRegOpcode: // lir operands - 0: reg

385

return ComputeSize(entry, 0, 0, false) - 1; // substract 1 for modrm

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

386

case kReg: // lir operands - 0: reg

387

return ComputeSize(entry, 0, 0, false);

388

case kMem: // lir operands - 0: base, 1: disp

389

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

390

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

391

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

392

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

393

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

394

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

395

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

396

case kThreadReg: // lir operands - 0: disp, 1: reg

397

return ComputeSize(entry, 0, lir->operands[0], false);

398

case kRegReg:

399

return ComputeSize(entry, 0, 0, false);

400

case kRegRegStore:

401

return ComputeSize(entry, 0, 0, false);

402

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

403

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

404

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

405

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

406

case kRegThread: // lir operands - 0: reg, 1: disp

407

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

408

case kRegImm: { // lir operands - 0: reg, 1: immediate

409

size_t size = ComputeSize(entry, 0, 0, false);

410

if (entry->skeleton.ax_opcode == 0) {

411

return size;

412

} else {

413

// AX opcodes don't require the modrm byte.

414

int reg = lir->operands[0];

415

return size - (reg == rAX ? 1 : 0);

416

}

417

}

418

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

419

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

420

case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

421

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

422

case kThreadImm: // lir operands - 0: disp, 1: imm

423

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

424

case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

425

return ComputeSize(entry, 0, 0, false);

426

case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

427

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

428

case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

429

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

430

case kMovRegImm: // lir operands - 0: reg, 1: immediate

431

return 1 + entry->skeleton.immediate_bytes;

432

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

433

// Shift by immediate one has a shorter opcode.

434

return ComputeSize(entry, 0, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

435

case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

436

// Shift by immediate one has a shorter opcode.

437

return ComputeSize(entry, lir->operands[0], lir->operands[1], false) -

438

(lir->operands[2] == 1 ? 1 : 0);

439

case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

440

// Shift by immediate one has a shorter opcode.

441

return ComputeSize(entry, lir->operands[0], lir->operands[3], true) -

442

(lir->operands[4] == 1 ? 1 : 0);

443

case kShiftRegCl:

444

return ComputeSize(entry, 0, 0, false);

445

case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

446

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

447

case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

448

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

449

case kRegCond: // lir operands - 0: reg, 1: cond

450

return ComputeSize(entry, 0, 0, false);

451

case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

452

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

453

case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

454

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

455

case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: cond

456

return ComputeSize(entry, 0, 0, false);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

457

case kJcc:

458

if (lir->opcode == kX86Jcc8) {

459

return 2; // opcode + rel8

460

} else {

461

DCHECK(lir->opcode == kX86Jcc32);

462

return 6; // 2 byte opcode + rel32

463

}

464

case kJmp:

465

if (lir->opcode == kX86Jmp8) {

466

return 2; // opcode + rel8

467

} else if (lir->opcode == kX86Jmp32) {

468

return 5; // opcode + rel32

469

} else {

470

DCHECK(lir->opcode == kX86JmpR);

471

return 2; // opcode + modrm

472

}

473

case kCall:

474

switch (lir->opcode) {

475

case kX86CallR: return 2; // opcode modrm

476

case kX86CallM: // lir operands - 0: base, 1: disp

477

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

478

case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

479

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

480

case kX86CallT: // lir operands - 0: disp

481

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

default:

break;

}

break;

case kPcRel:

if (entry->opcode == kX86PcRelLoadRA) {

488

// lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

489

return ComputeSize(entry, lir->operands[1], 0x12345678, true);

490

} else {

491

DCHECK(entry->opcode == kX86PcRelAdr);

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

492

return 5; // opcode with reg + 4 byte immediate

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

493

}

494

case kMacro:

495

DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));

496

return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +

497

ComputeSize(&X86Mir2Lir::EncodingMap[kX86Sub32RI], 0, 0, false) -

498

(lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

return 0;

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

506

void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry) {

507

if (entry->skeleton.prefix1 != 0) {

508

code_buffer_.push_back(entry->skeleton.prefix1);

509

if (entry->skeleton.prefix2 != 0) {

510

code_buffer_.push_back(entry->skeleton.prefix2);

511

}

512

} else {

513

DCHECK_EQ(0, entry->skeleton.prefix2);

}

}

void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) {

518

code_buffer_.push_back(entry->skeleton.opcode);

519

if (entry->skeleton.opcode == 0x0F) {

520

code_buffer_.push_back(entry->skeleton.extra_opcode1);

521

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

522

code_buffer_.push_back(entry->skeleton.extra_opcode2);

523

} else {

524

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

525

}

526

} else {

527

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

528

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

}

}

void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry) {

EmitPrefix(entry);

EmitOpcode(entry);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

537

static uint8_t ModrmForDisp(int base, int disp) {

538

// BP requires an explicit disp, so do not omit it in the 0 case

539

if (disp == 0 && base != rBP) {

540

return 0;

541

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

548

void X86Mir2Lir::EmitDisp(uint8_t base, int disp) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

549

// BP requires an explicit disp, so do not omit it in the 0 case

550

if (disp == 0 && base != rBP) {

551

return;

552

} else if (IS_SIMM8(disp)) {

553

code_buffer_.push_back(disp & 0xFF);

554

} else {

555

code_buffer_.push_back(disp & 0xFF);

556

code_buffer_.push_back((disp >> 8) & 0xFF);

557

code_buffer_.push_back((disp >> 16) & 0xFF);

558

code_buffer_.push_back((disp >> 24) & 0xFF);

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

562

void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp) {

563

DCHECK_LT(reg_or_opcode, 8);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

564

DCHECK_LT(base, 8);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

565

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | base;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

566

code_buffer_.push_back(modrm);

567

if (base == rX86_SP) {

568

// Special SIB for SP base

569

code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);

570

}

571

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

572

}

573

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

574

void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index,

575

int scale, int disp) {

576

DCHECK_LT(reg_or_opcode, 8);

577

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | rX86_SP;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

578

code_buffer_.push_back(modrm);

DCHECK_LT(scale, 4);

DCHECK_LT(index, 8);

DCHECK_LT(base, 8);

uint8_t sib = (scale << 6) | (index << 3) | base;

583

code_buffer_.push_back(sib);

584

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

585

}

586

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

587

void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int imm) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

588

switch (entry->skeleton.immediate_bytes) {

589

case 1:

590

DCHECK(IS_SIMM8(imm));

591

code_buffer_.push_back(imm & 0xFF);

592

break;

593

case 2:

594

DCHECK(IS_SIMM16(imm));

595

code_buffer_.push_back(imm & 0xFF);

596

code_buffer_.push_back((imm >> 8) & 0xFF);

597

break;

598

case 4:

599

code_buffer_.push_back(imm & 0xFF);

600

code_buffer_.push_back((imm >> 8) & 0xFF);

601

code_buffer_.push_back((imm >> 16) & 0xFF);

602

code_buffer_.push_back((imm >> 24) & 0xFF);

603

break;

604

default:

605

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

606

<< ") for instruction: " << entry->name;

break;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

611

void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg) {

612

EmitPrefixAndOpcode(entry);

613

// There's no 3-byte instruction with +rd

614

DCHECK(entry->skeleton.opcode != 0x0F ||

615

(entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A));

616

DCHECK(!X86_FPREG(reg));

617

DCHECK_LT(reg, 8);

618

code_buffer_.back() += reg;

619

DCHECK_EQ(0, entry->skeleton.ax_opcode);

620

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

621

}

622

623

void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) {

624

EmitPrefixAndOpcode(entry);

625

if (X86_FPREG(reg)) {

626

reg = reg & X86_FP_REG_MASK;

627

}

628

if (reg >= 4) {

629

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

630

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

631

}

632

DCHECK_LT(reg, 8);

633

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

634

code_buffer_.push_back(modrm);

635

DCHECK_EQ(0, entry->skeleton.ax_opcode);

636

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

637

}

638

639

void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) {

640

EmitPrefix(entry);

641

code_buffer_.push_back(entry->skeleton.opcode);

642

DCHECK_NE(0x0F, entry->skeleton.opcode);

643

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

644

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

645

DCHECK_NE(rX86_SP, base);

646

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

647

DCHECK_EQ(0, entry->skeleton.ax_opcode);

648

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

649

}

650

651

void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index,

652

int scale, int disp) {

653

EmitPrefixAndOpcode(entry);

654

EmitModrmSibDisp(entry->skeleton.modrm_opcode, base, index, scale, disp);

655

DCHECK_EQ(0, entry->skeleton.ax_opcode);

656

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

657

}

658

659

void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry,

660

uint8_t base, int disp, uint8_t reg) {

661

EmitPrefixAndOpcode(entry);

662

if (X86_FPREG(reg)) {

663

reg = reg & X86_FP_REG_MASK;

664

}

665

if (reg >= 4) {

666

DCHECK(strchr(entry->name, '8') == NULL ||

667

entry->opcode == kX86Movzx8RM || entry->opcode == kX86Movsx8RM)

668

<< entry->name << " " << static_cast<int>(reg)

669

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

670

}

671

EmitModrmDisp(reg, base, disp);

672

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

673

DCHECK_EQ(0, entry->skeleton.ax_opcode);

674

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

675

}

676

677

void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry,

678

uint8_t reg, uint8_t base, int disp) {

679

// Opcode will flip operands.

680

EmitMemReg(entry, base, disp, reg);

681

}

682

683

void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index,

684

int scale, int disp) {

685

EmitPrefixAndOpcode(entry);

686

if (X86_FPREG(reg)) {

687

reg = reg & X86_FP_REG_MASK;

688

}

689

EmitModrmSibDisp(reg, base, index, scale, disp);

690

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

691

DCHECK_EQ(0, entry->skeleton.ax_opcode);

692

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

693

}

694

695

void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp,

696

uint8_t reg) {

697

// Opcode will flip operands.

698

EmitRegArray(entry, reg, base, index, scale, disp);

699

}

700

701

void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) {

702

DCHECK_NE(entry->skeleton.prefix1, 0);

703

EmitPrefixAndOpcode(entry);

704

if (X86_FPREG(reg)) {

705

reg = reg & X86_FP_REG_MASK;

706

}

707

if (reg >= 4) {

708

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

709

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

710

}

711

DCHECK_LT(reg, 8);

712

uint8_t modrm = (0 << 6) | (reg << 3) | rBP;

713

code_buffer_.push_back(modrm);

714

code_buffer_.push_back(disp & 0xFF);

715

code_buffer_.push_back((disp >> 8) & 0xFF);

716

code_buffer_.push_back((disp >> 16) & 0xFF);

717

code_buffer_.push_back((disp >> 24) & 0xFF);

718

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

719

DCHECK_EQ(0, entry->skeleton.ax_opcode);

720

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

721

}

722

723

void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) {

724

EmitPrefixAndOpcode(entry);

725

if (X86_FPREG(reg1)) {

726

reg1 = reg1 & X86_FP_REG_MASK;

727

}

728

if (X86_FPREG(reg2)) {

729

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

734

code_buffer_.push_back(modrm);

735

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

736

DCHECK_EQ(0, entry->skeleton.ax_opcode);

737

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

738

}

739

740

void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry,

741

uint8_t reg1, uint8_t reg2, int32_t imm) {

742

EmitPrefixAndOpcode(entry);

743

if (X86_FPREG(reg1)) {

744

reg1 = reg1 & X86_FP_REG_MASK;

745

}

746

if (X86_FPREG(reg2)) {

747

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

752

code_buffer_.push_back(modrm);

753

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

754

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

758

void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

759

if (entry->skeleton.prefix1 != 0) {

760

code_buffer_.push_back(entry->skeleton.prefix1);

761

if (entry->skeleton.prefix2 != 0) {

762

code_buffer_.push_back(entry->skeleton.prefix2);

763

}

764

} else {

765

DCHECK_EQ(0, entry->skeleton.prefix2);

766

}

767

if (reg == rAX && entry->skeleton.ax_opcode != 0) {

768

code_buffer_.push_back(entry->skeleton.ax_opcode);

769

} else {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

770

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

771

if (X86_FPREG(reg)) {

772

reg = reg & X86_FP_REG_MASK;

773

}

774

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

775

code_buffer_.push_back(modrm);

776

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

777

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

778

}

779

Mark Mendell

343adb5

2013-12-18 06:02:17 -0800

[diff] [blame]

780

void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm) {

781

EmitPrefixAndOpcode(entry);

782

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

783

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

787

void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

788

EmitPrefixAndOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

789

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

790

code_buffer_.push_back(modrm);

791

code_buffer_.push_back(disp & 0xFF);

792

code_buffer_.push_back((disp >> 8) & 0xFF);

793

code_buffer_.push_back((disp >> 16) & 0xFF);

794

code_buffer_.push_back((disp >> 24) & 0xFF);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

795

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

796

DCHECK_EQ(entry->skeleton.ax_opcode, 0);

797

}

798

799

void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

800

DCHECK_LT(reg, 8);

801

code_buffer_.push_back(0xB8 + reg);

802

code_buffer_.push_back(imm & 0xFF);

803

code_buffer_.push_back((imm >> 8) & 0xFF);

804

code_buffer_.push_back((imm >> 16) & 0xFF);

805

code_buffer_.push_back((imm >> 24) & 0xFF);

806

}

807

808

void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

809

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

810

if (imm != 1) {

811

code_buffer_.push_back(entry->skeleton.opcode);

812

} else {

813

// Shorter encoding for 1 bit shift

814

code_buffer_.push_back(entry->skeleton.ax_opcode);

815

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

816

DCHECK_NE(0x0F, entry->skeleton.opcode);

817

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

818

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

819

if (reg >= 4) {

820

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

821

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

822

}

823

DCHECK_LT(reg, 8);

824

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

825

code_buffer_.push_back(modrm);

826

if (imm != 1) {

827

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

828

DCHECK(IS_SIMM8(imm));

829

code_buffer_.push_back(imm & 0xFF);

}

}

void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl) {

834

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

835

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

836

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

837

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

838

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

839

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

840

DCHECK_LT(reg, 8);

841

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

842

code_buffer_.push_back(modrm);

843

DCHECK_EQ(0, entry->skeleton.ax_opcode);

844

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

845

}

846

847

void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) {

848

if (entry->skeleton.prefix1 != 0) {

849

code_buffer_.push_back(entry->skeleton.prefix1);

850

if (entry->skeleton.prefix2 != 0) {

851

code_buffer_.push_back(entry->skeleton.prefix2);

852

}

853

} else {

854

DCHECK_EQ(0, entry->skeleton.prefix2);

855

}

856

DCHECK_EQ(0, entry->skeleton.ax_opcode);

857

DCHECK_EQ(0x0F, entry->skeleton.opcode);

858

code_buffer_.push_back(0x0F);

859

DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);

860

code_buffer_.push_back(0x90 | condition);

861

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

862

DCHECK_LT(reg, 8);

863

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

864

code_buffer_.push_back(modrm);

865

DCHECK_EQ(entry->skeleton.immediate_bytes, 0);

866

}

867

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

868

void X86Mir2Lir::EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, uint8_t condition) {

869

// Generate prefix and opcode without the condition

870

EmitPrefixAndOpcode(entry);

871

872

// Now add the condition. The last byte of opcode is the one that receives it.

873

DCHECK_LE(condition, 0xF);

874

code_buffer_.back() += condition;

875

876

// Not expecting to have to encode immediate or do anything special for ModR/M since there are two registers.

877

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

878

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

879

880

// Check that registers requested for encoding are sane.

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

// For register to register encoding, the mod is 3.

885

const uint8_t mod = (3 << 6);

886

887

// Encode the ModR/M byte now.

888

const uint8_t modrm = mod | (reg1 << 3) | reg2;

889

code_buffer_.push_back(modrm);

890

}

891

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

892

void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int rel) {

893

if (entry->opcode == kX86Jmp8) {

894

DCHECK(IS_SIMM8(rel));

895

code_buffer_.push_back(0xEB);

896

code_buffer_.push_back(rel & 0xFF);

897

} else if (entry->opcode == kX86Jmp32) {

898

code_buffer_.push_back(0xE9);

899

code_buffer_.push_back(rel & 0xFF);

900

code_buffer_.push_back((rel >> 8) & 0xFF);

901

code_buffer_.push_back((rel >> 16) & 0xFF);

902

code_buffer_.push_back((rel >> 24) & 0xFF);

903

} else {

904

DCHECK(entry->opcode == kX86JmpR);

905

code_buffer_.push_back(entry->skeleton.opcode);

906

uint8_t reg = static_cast<uint8_t>(rel);

907

DCHECK_LT(reg, 8);

908

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

909

code_buffer_.push_back(modrm);

}

}

void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc) {

914

DCHECK_LT(cc, 16);

915

if (entry->opcode == kX86Jcc8) {

916

DCHECK(IS_SIMM8(rel));

917

code_buffer_.push_back(0x70 | cc);

918

code_buffer_.push_back(rel & 0xFF);

919

} else {

920

DCHECK(entry->opcode == kX86Jcc32);

921

code_buffer_.push_back(0x0F);

922

code_buffer_.push_back(0x80 | cc);

923

code_buffer_.push_back(rel & 0xFF);

924

code_buffer_.push_back((rel >> 8) & 0xFF);

925

code_buffer_.push_back((rel >> 16) & 0xFF);

926

code_buffer_.push_back((rel >> 24) & 0xFF);

}

}

void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

931

EmitPrefixAndOpcode(entry);

932

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

933

DCHECK_EQ(0, entry->skeleton.ax_opcode);

934

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

935

}

936

937

void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int disp) {

938

DCHECK_NE(entry->skeleton.prefix1, 0);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

939

EmitPrefixAndOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

940

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

941

code_buffer_.push_back(modrm);

942

code_buffer_.push_back(disp & 0xFF);

943

code_buffer_.push_back((disp >> 8) & 0xFF);

944

code_buffer_.push_back((disp >> 16) & 0xFF);

945

code_buffer_.push_back((disp >> 24) & 0xFF);

946

DCHECK_EQ(0, entry->skeleton.ax_opcode);

947

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

948

}

949

950

void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, uint8_t reg,

951

int base_or_table, uint8_t index, int scale, int table_or_disp) {

952

int disp;

953

if (entry->opcode == kX86PcRelLoadRA) {

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

954

Mir2Lir::EmbeddedData *tab_rec =

955

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

956

disp = tab_rec->offset;

957

} else {

958

DCHECK(entry->opcode == kX86PcRelAdr);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

959

Mir2Lir::EmbeddedData *tab_rec =

960

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(base_or_table));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

961

disp = tab_rec->offset;

962

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

963

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

964

if (X86_FPREG(reg)) {

965

reg = reg & X86_FP_REG_MASK;

966

}

967

DCHECK_LT(reg, 8);

968

if (entry->opcode == kX86PcRelLoadRA) {

969

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

970

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

971

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

972

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

973

uint8_t modrm = (2 << 6) | (reg << 3) | rX86_SP;

974

code_buffer_.push_back(modrm);

975

DCHECK_LT(scale, 4);

976

DCHECK_LT(index, 8);

977

DCHECK_LT(base_or_table, 8);

978

uint8_t base = static_cast<uint8_t>(base_or_table);

979

uint8_t sib = (scale << 6) | (index << 3) | base;

980

code_buffer_.push_back(sib);

981

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

982

} else {

983

code_buffer_.push_back(entry->skeleton.opcode + reg);

984

}

985

code_buffer_.push_back(disp & 0xFF);

986

code_buffer_.push_back((disp >> 8) & 0xFF);

987

code_buffer_.push_back((disp >> 16) & 0xFF);

988

code_buffer_.push_back((disp >> 24) & 0xFF);

989

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

990

DCHECK_EQ(0, entry->skeleton.ax_opcode);

991

}

992

993

void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset) {

994

DCHECK(entry->opcode == kX86StartOfMethod) << entry->name;

995

code_buffer_.push_back(0xE8); // call +0

996

code_buffer_.push_back(0);

997

code_buffer_.push_back(0);

998

code_buffer_.push_back(0);

999

code_buffer_.push_back(0);

1000

1001

DCHECK_LT(reg, 8);

1002

code_buffer_.push_back(0x58 + reg); // pop reg

1003

1004

EmitRegImm(&X86Mir2Lir::EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */);

1005

}

1006

1007

void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) {

1008

UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " "

1009

<< BuildInsnString(entry->fmt, lir, 0);

1010

for (int i = 0; i < GetInsnSize(lir); ++i) {

1011

code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3

}

}

/*

* Assemble the LIR into binary instruction format. Note that we may

1017

* discover that pc-relative displacements may not fit the selected

1018

* instruction. In those cases we will try to substitute a new code

1019

* sequence or request that the trace be shortened and retried.

1020

*/

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1021

AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1022

LIR *lir;

1023

AssemblerStatus res = kSuccess; // Assume success

1024

1025

const bool kVerbosePcFixup = false;

1026

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1027

if (IsPseudoLirOp(lir->opcode)) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

continue;

}

if (lir->flags.is_nop) {

continue;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1035

if (lir->flags.fixup != kFixupNone) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1036

switch (lir->opcode) {

1037

case kX86Jcc8: {

1038

LIR *target_lir = lir->target;

1039

DCHECK(target_lir != NULL);

1040

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1041

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1042

if (IS_SIMM8(lir->operands[0])) {

1043

pc = lir->offset + 2 /* opcode + rel8 */;

1044

} else {

1045

pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1046

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1047

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1048

delta = target - pc;

1049

if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1050

if (kVerbosePcFixup) {

1051

LOG(INFO) << "Retry for JCC growth at " << lir->offset

1052

<< " delta: " << delta << " old delta: " << lir->operands[0];

1053

}

1054

lir->opcode = kX86Jcc32;

1055

SetupResourceMasks(lir);

1056

res = kRetryAll;

1057

}

1058

if (kVerbosePcFixup) {

1059

LOG(INFO) << "Source:";

1060

DumpLIRInsn(lir, 0);

1061

LOG(INFO) << "Target:";

1062

DumpLIRInsn(target_lir, 0);

1063

LOG(INFO) << "Delta " << delta;

1064

}

1065

lir->operands[0] = delta;

break;

}

case kX86Jcc32: {

LIR *target_lir = lir->target;

1070

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1071

CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1072

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1073

int delta = target - pc;

1074

if (kVerbosePcFixup) {

1075

LOG(INFO) << "Source:";

1076

DumpLIRInsn(lir, 0);

1077

LOG(INFO) << "Target:";

1078

DumpLIRInsn(target_lir, 0);

1079

LOG(INFO) << "Delta " << delta;

1080

}

1081

lir->operands[0] = delta;

break;

}

case kX86Jmp8: {

LIR *target_lir = lir->target;

1086

DCHECK(target_lir != NULL);

1087

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1088

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1089

if (IS_SIMM8(lir->operands[0])) {

1090

pc = lir->offset + 2 /* opcode + rel8 */;

1091

} else {

1092

pc = lir->offset + 5 /* opcode + rel32 */;

1093

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1094

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1095

delta = target - pc;

1096

if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) {

1097

// Useless branch

buzbee

252254b

2013-09-08 16:20:53 -0700

[diff] [blame]

1098

NopLIR(lir);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1099

if (kVerbosePcFixup) {

1100

LOG(INFO) << "Retry for useless branch at " << lir->offset;

1101

}

1102

res = kRetryAll;

1103

} else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1104

if (kVerbosePcFixup) {

1105

LOG(INFO) << "Retry for JMP growth at " << lir->offset;

1106

}

1107

lir->opcode = kX86Jmp32;

1108

SetupResourceMasks(lir);

1109

res = kRetryAll;

1110

}

1111

lir->operands[0] = delta;

break;

}

case kX86Jmp32: {

LIR *target_lir = lir->target;

1116

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1117

CodeOffset pc = lir->offset + 5 /* opcode + rel32 */;

1118

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1119

int delta = target - pc;

1120

lir->operands[0] = delta;

break;

}

default:

break;

}

}

/*

* If one of the pc-relative instructions expanded we'll have

1130

* to make another pass. Don't bother to fully assemble the

1131

* instruction.

1132

*/

1133

if (res != kSuccess) {

1134

continue;

1135

}

1136

CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size());

1137

const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode];

1138

size_t starting_cbuf_size = code_buffer_.size();

1139

switch (entry->kind) {

1140

case kData: // 4 bytes of data

1141

code_buffer_.push_back(lir->operands[0]);

1142

break;

1143

case kNullary: // 1 byte of opcode

1144

DCHECK_EQ(0, entry->skeleton.prefix1);

1145

DCHECK_EQ(0, entry->skeleton.prefix2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1146

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1147

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1148

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1149

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1150

break;

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

1151

case kRegOpcode: // lir operands - 0: reg

1152

EmitOpRegOpcode(entry, lir->operands[0]);

1153

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1154

case kReg: // lir operands - 0: reg

1155

EmitOpReg(entry, lir->operands[0]);

1156

break;

1157

case kMem: // lir operands - 0: base, 1: disp

1158

EmitOpMem(entry, lir->operands[0], lir->operands[1]);

1159

break;

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1160

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

1161

EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]);

1162

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1163

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

1164

EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1165

break;

Mark Mendell

343adb5

2013-12-18 06:02:17 -0800

[diff] [blame]

1166

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

1167

EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1168

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1169

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

1170

EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1171

lir->operands[3], lir->operands[4]);

1172

break;

1173

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

1174

EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1175

break;

1176

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

1177

EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1178

lir->operands[3], lir->operands[4]);

1179

break;

1180

case kRegThread: // lir operands - 0: reg, 1: disp

1181

EmitRegThread(entry, lir->operands[0], lir->operands[1]);

1182

break;

1183

case kRegReg: // lir operands - 0: reg1, 1: reg2

1184

EmitRegReg(entry, lir->operands[0], lir->operands[1]);

1185

break;

1186

case kRegRegStore: // lir operands - 0: reg2, 1: reg1

1187

EmitRegReg(entry, lir->operands[1], lir->operands[0]);

1188

break;

1189

case kRegRegImm:

1190

EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1191

break;

1192

case kRegImm: // lir operands - 0: reg, 1: immediate

1193

EmitRegImm(entry, lir->operands[0], lir->operands[1]);

1194

break;

1195

case kThreadImm: // lir operands - 0: disp, 1: immediate

1196

EmitThreadImm(entry, lir->operands[0], lir->operands[1]);

1197

break;

1198

case kMovRegImm: // lir operands - 0: reg, 1: immediate

1199

EmitMovRegImm(entry, lir->operands[0], lir->operands[1]);

1200

break;

1201

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

1202

EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]);

1203

break;

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

1204

case kShiftRegCl: // lir operands - 0: reg, 1: cl

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1205

EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]);

1206

break;

1207

case kRegCond: // lir operands - 0: reg, 1: condition

1208

EmitRegCond(entry, lir->operands[0], lir->operands[1]);

1209

break;

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

1210

case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: condition

1211

EmitRegRegCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1212

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1213

case kJmp: // lir operands - 0: rel

1214

EmitJmp(entry, lir->operands[0]);

1215

break;

1216

case kJcc: // lir operands - 0: rel, 1: CC, target assigned

1217

EmitJcc(entry, lir->operands[0], lir->operands[1]);

1218

break;

1219

case kCall:

1220

switch (entry->opcode) {

1221

case kX86CallM: // lir operands - 0: base, 1: disp

1222

EmitCallMem(entry, lir->operands[0], lir->operands[1]);

1223

break;

1224

case kX86CallT: // lir operands - 0: disp

1225

EmitCallThread(entry, lir->operands[0]);

1226

break;

1227

default:

1228

EmitUnimplemented(entry, lir);

break;

}

break;

case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

1233

EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1234

lir->operands[3], lir->operands[4]);

1235

break;

1236

case kMacro:

1237

EmitMacro(entry, lir->operands[0], lir->offset);

1238

break;

1239

default:

1240

EmitUnimplemented(entry, lir);

1241

break;

1242

}

1243

CHECK_EQ(static_cast<size_t>(GetInsnSize(lir)),

1244

code_buffer_.size() - starting_cbuf_size)

1245

<< "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name;

}

return res;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1250

// LIR offset assignment.

1251

// TODO: consolidate w/ Arm assembly mechanism.

1252

int X86Mir2Lir::AssignInsnOffsets() {

LIR* lir;

int offset = 0;

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

1257

lir->offset = offset;

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1258

if (LIKELY(!IsPseudoLirOp(lir->opcode))) {

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1259

if (!lir->flags.is_nop) {

1260

offset += lir->flags.size;

1261

}

1262

} else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) {

1263

if (offset & 0x2) {

1264

offset += 2;

1265

lir->operands[0] = 1;

1266

} else {

1267

lir->operands[0] = 0;

1268

}

1269

}

1270

/* Pseudo opcodes don't consume space */

}

return offset;

}

/*

* Walk the compilation unit and assign offsets to instructions

1277

* and literals and compute the total size of the compiled unit.

1278

* TODO: consolidate w/ Arm assembly mechanism.

1279

*/

1280

void X86Mir2Lir::AssignOffsets() {

1281

int offset = AssignInsnOffsets();

1282

1283

/* Const values have to be word aligned */

1284

offset = (offset + 3) & ~3;

1285

1286

/* Set up offsets for literals */

1287

data_offset_ = offset;

1288

1289

offset = AssignLiteralOffset(offset);

1290

1291

offset = AssignSwitchTablesOffset(offset);

1292

1293

offset = AssignFillArrayDataOffset(offset);

1294

1295

total_size_ = offset;

}

/*

* Go over each instruction in the list and calculate the offset from the top

1300

* before sending them off to the assembler. If out-of-range branch distance is

1301

* seen rearrange the instructions a bit to correct it.

1302

* TODO: consolidate w/ Arm assembly mechanism.

1303

*/

1304

void X86Mir2Lir::AssembleLIR() {

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1305

cu_->NewTimingSplit("Assemble");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1306

AssignOffsets();

1307

int assembler_retries = 0;

1308

/*

1309

* Assemble here. Note that we generate code with optimistic assumptions

1310

* and if found now to work, we'll have to redo the sequence and retry.

*/

while (true) {

AssemblerStatus res = AssembleInstructions(0);

1315

if (res == kSuccess) {

break;

} else {

assembler_retries++;

if (assembler_retries > MAX_ASSEMBLER_RETRIES) {

1320

CodegenDump();

1321

LOG(FATAL) << "Assembler error - too many retries";

1322

}

1323

// Redo offsets and try again

1324

AssignOffsets();

1325

code_buffer_.clear();

}

}

// Install literals

InstallLiteralPools();

1331

1332

// Install switch tables

1333

InstallSwitchTables();

1334

1335

// Install fill array data

1336

InstallFillArrayData();

1337

1338

// Create the mapping table and native offset to reference map.

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1339

cu_->NewTimingSplit("PcMappingTable");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1340

CreateMappingTables();

1341

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1342

cu_->NewTimingSplit("GcMap");

buzbee