Blame - src/compiler/codegen/x86/Assemble.cc - platform_art

2012-03-06 22:14:17 -0800

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{ kX86 ## opname ## 16MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16MR", "[!0r+!1d],!2r" }, \

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{ kX86 ## opname ## 16AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \

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{ kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16TR", "fs:[!0d],!1r" }, \

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{ kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RR", "!0r,!1r" }, \

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{ kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \

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{ kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RT", "!0r,fs:[!1d]" }, \

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{ kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16TI", "fs:[!0d],!1d" }, \

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{ kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16RI8", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16MI8", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16TI8", "fs:[!0d],!1d" }, \

Ian Rogers

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jeffhao

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{ kX86 ## opname ## 32MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32MR", "[!0r+!1d],!2r" }, \

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{ kX86 ## opname ## 32AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \

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{ kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32TR", "fs:[!0d],!1r" }, \

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{ kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RR", "!0r,!1r" }, \

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{ kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \

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{ kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RT", "!0r,fs:[!1d]" }, \

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{ kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32TI", "fs:[!0d],!1d" }, \

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{ kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32RI8", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32MI8", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32TI8", "fs:[!0d],!1d" }

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ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */,

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0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */,

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0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */,

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0x80, 0x0 /* RegMem8/imm8 */,

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0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */),

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ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */,

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0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */,

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0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */,

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0x80, 0x1 /* RegMem8/imm8 */,

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0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */),

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ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,

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0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */,

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0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */,

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0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */,

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0x80, 0x2 /* RegMem8/imm8 */,

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0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */),

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ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,

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0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */,

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0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */,

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0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */,

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0x80, 0x3 /* RegMem8/imm8 */,

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0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */),

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ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */,

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0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */,

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0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */,

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0x80, 0x4 /* RegMem8/imm8 */,

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0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */),

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ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */,

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0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */,

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0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */,

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0x80, 0x5 /* RegMem8/imm8 */,

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0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */),

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ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0,

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0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */,

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0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */,

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0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */,

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0x80, 0x6 /* RegMem8/imm8 */,

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0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */),

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ENCODING_MAP(Cmp, IS_LOAD, 0, 0,

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0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */,

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0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */,

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0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */,

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0x80, 0x7 /* RegMem8/imm8 */,

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0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */),

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#undef ENCODING_MAP

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{ kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RRI", "!0r,!1r,!2d" },

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{ kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RMI", "!0r,[!1r+!2d],!3d" },

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{ kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },

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{ kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RRI", "!0r,!1r,!2d" },

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{ kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RMI", "!0r,[!1r+!2d],!3d" },

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{ kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },

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{ kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RRI8", "!0r,!1r,!2d" },

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{ kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" },

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{ kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" },

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jeffhao

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{ kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8MR", "[!0r+!1d],!2r" },

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{ kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8TR", "fs:[!0d],!1r" },

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{ kX86Mov8RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RR", "!0r,!1r" },

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{ kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RM", "!0r,[!1r+!2d]" },

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{ kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RT", "!0r,fs:[!1d]" },

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{ kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1 }, "Mov8RI", "!0r,!1d" },

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{ kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8MI", "[!0r+!1d],!2d" },

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{ kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8TI", "fs:[!0d],!1d" },

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{ kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16MR", "[!0r+!1d],!2r" },

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{ kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0 }, "Mov16TR", "fs:[!0d],!1r" },

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{ kX86Mov16RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RR", "!0r,!1r" },

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{ kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RM", "!0r,[!1r+!2d]" },

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{ kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RT", "!0r,fs:[!1d]" },

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{ kX86Mov16RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2 }, "Mov16RI", "!0r,!1d" },

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{ kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16MI", "[!0r+!1d],!2d" },

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{ kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2 }, "Mov16TI", "fs:[!0d],!1d" },

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{ kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32MR", "[!0r+!1d],!2r" },

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{ kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32TR", "fs:[!0d],!1r" },

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{ kX86Mov32RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RR", "!0r,!1r" },

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{ kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RM", "!0r,[!1r+!2d]" },

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{ kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RT", "!0r,fs:[!1d]" },

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{ kX86Mov32RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "Mov32RI", "!0r,!1d" },

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{ kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32MI", "[!0r+!1d],!2d" },

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{ kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32TI", "fs:[!0d],!1d" },

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{ kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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181

#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \

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{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \

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{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \

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{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \

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{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }

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203

SHIFT_ENCODING_MAP(Rol, 0x0),

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SHIFT_ENCODING_MAP(Ror, 0x1),

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SHIFT_ENCODING_MAP(Rcl, 0x2),

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SHIFT_ENCODING_MAP(Rcr, 0x3),

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SHIFT_ENCODING_MAP(Sal, 0x4),

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SHIFT_ENCODING_MAP(Shr, 0x5),

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SHIFT_ENCODING_MAP(Sar, 0x7),

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#undef SHIFT_ENCODING_MAP

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{ kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0}, "Cmc", "" },

213

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{ kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" },

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{ kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" },

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{ kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" },

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{ kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" },

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{ kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" },

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{ kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" },

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{ kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0}, "Test32RR", "!0r,!1r" },

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#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \

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reg, reg_kind, reg_flags, \

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mem, mem_kind, mem_flags, \

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arr, arr_kind, arr_flags, imm, \

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b_flags, hw_flags, w_flags, \

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b_format, hw_format, w_format) \

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{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, #b_format "!0r" }, \

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{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, #b_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, #b_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, #hw_format "!0r" }, \

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{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, #hw_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, #hw_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, #w_format "!0r" }, \

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{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, #w_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, #w_format "[!0r+!1r<<!2d+!3d]" }

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UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

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UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

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#undef UNARY_ENCODING_MAP

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#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \

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{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

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{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

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EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),

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{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

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{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),

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{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

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{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0),

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EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0),

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285

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{ kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" },

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{ kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" },

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288

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EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),

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{ kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" },

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{ kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" },

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{ kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },

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293

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{ kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

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{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

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{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

297

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

298

// TODO: load/store?

299

// Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.

300

{ kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },

301

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

302

EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES),

303

EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES),

jeffhao

8302576

2012-08-02 11:08:56 -0700

[diff] [blame]

304

305

{ kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" },

306

{ kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" },

307

{ kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

308

{ kX86LockCmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "!0r,!1r" },

309

{ kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" },

310

{ kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

311

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

312

EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),

313

EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),

314

EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),

315

EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

316

#undef EXT_0F_ENCODING_MAP

317

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

318

{ kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },

319

{ kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },

320

{ kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },

321

{ kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },

322

{ kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" },

323

{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

324

{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

325

{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

326

{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

327

{ kX86Ret, kNullary,NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

328

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

329

{ kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" },

330

{ kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },

331

{ kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" },

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

332

};

333

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

334

static size_t computeSize(X86EncodingMap* entry, int displacement, bool has_sib) {

335

size_t size = 0;

336

if (entry->skeleton.prefix1 > 0) {

337

++size;

338

if (entry->skeleton.prefix2 > 0) {

339

++size;

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

340

}

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

341

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

342

++size; // opcode

343

if (entry->skeleton.opcode == 0x0F) {

344

++size;

345

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

if (has_sib) {

++size;

}

if (displacement != 0) {

354

if (entry->opcode != kX86Lea32RA) {

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

355

DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0) << entry->name;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

356

}

357

size += IS_SIMM8(displacement) ? 1 : 4;

358

}

359

size += entry->skeleton.immediate_bytes;

return size;

}

int oatGetInsnSize(LIR* lir) {

364

X86EncodingMap* entry = &EncodingMap[lir->opcode];

365

switch (entry->kind) {

366

case kData:

367

return 4; // 4 bytes of data

368

case kNop:

369

return lir->operands[0]; // length of nop is sole operand

370

case kNullary:

371

return 1; // 1 byte of opcode

372

case kReg: // lir operands - 0: reg

373

return computeSize(entry, 0, false);

374

case kMem: { // lir operands - 0: base, 1: disp

375

int base = lir->operands[0];

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

376

int disp = lir->operands[1];

377

// SP requires a special extra SIB byte. BP requires explicit disp,

378

// so add a byte for disp 0 which would normally be omitted.

379

return computeSize(entry, disp, false) + ((base == rSP) || (base == rBP && disp == 0) ? 1 : 0);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

380

}

381

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

382

return computeSize(entry, lir->operands[3], true);

383

case kMemReg: { // lir operands - 0: base, 1: disp, 2: reg

384

int base = lir->operands[0];

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

385

int disp = lir->operands[1];

386

// SP requires a special extra SIB byte. BP requires explicit disp,

387

// so add a byte for disp 0 which would normally be omitted.

388

return computeSize(entry, disp, false) + ((base == rSP) || (base == rBP && disp == 0) ? 1 : 0);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

389

}

390

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

391

return computeSize(entry, lir->operands[3], true);

392

case kThreadReg: // lir operands - 0: disp, 1: reg

393

return computeSize(entry, lir->operands[0], false);

394

case kRegReg:

395

return computeSize(entry, 0, false);

jeffhao

2012-07-11 16:08:43 -0700

[diff] [blame]

396

case kRegRegStore:

397

return computeSize(entry, 0, false);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

398

case kRegMem: { // lir operands - 0: reg, 1: base, 2: disp

399

int base = lir->operands[1];

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

400

int disp = lir->operands[2];

401

// SP requires a special extra SIB byte. BP requires explicit disp,

402

// so add a byte for disp 0 which would normally be omitted.

403

return computeSize(entry, disp, false) + ((base == rSP) || (base == rBP && disp == 0) ? 1 : 0);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

404

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

405

case kRegArray: { // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

406

int base = lir->operands[1];

407

int disp = lir->operands[4];

408

// BP requires explicit disp, so add a byte for disp 0 which would normally be omitted.

409

return computeSize(entry, disp, true) + ((base == rBP && disp == 0) ? 1 : 0);

410

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

411

case kRegThread: // lir operands - 0: reg, 1: disp

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

412

return computeSize(entry, 0x12345678, false); // displacement size is always 32bit

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

413

case kRegImm: { // lir operands - 0: reg, 1: immediate

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

414

size_t size = computeSize(entry, 0, false);

415

if (entry->skeleton.ax_opcode == 0) {

416

return size;

417

} else {

418

// AX opcodes don't require the modrm byte.

419

int reg = lir->operands[0];

420

return size - (reg == rAX ? 1 : 0);

421

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

422

}

423

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

424

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

425

return computeSize(entry, lir->operands[1], false);

426

case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

427

return computeSize(entry, lir->operands[3], true);

428

case kThreadImm: // lir operands - 0: disp, 1: imm

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

429

return computeSize(entry, 0x12345678, false); // displacement size is always 32bit

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

430

case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

431

return computeSize(entry, 0, false);

432

case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

433

CHECK_NE(lir->operands[1], static_cast<int>(rSP)); // TODO: add extra SIB byte

434

return computeSize(entry, lir->operands[2], false);

435

case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

436

return computeSize(entry, lir->operands[4], true);

437

case kMovRegImm: // lir operands - 0: reg, 1: immediate

438

return 1 + entry->skeleton.immediate_bytes;

439

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

440

// Shift by immediate one has a shorter opcode.

441

return computeSize(entry, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

442

case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

443

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

444

// Shift by immediate one has a shorter opcode.

445

return computeSize(entry, lir->operands[1], false) - (lir->operands[2] == 1 ? 1 : 0);

446

case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

447

// Shift by immediate one has a shorter opcode.

448

return computeSize(entry, lir->operands[3], true) - (lir->operands[4] == 1 ? 1 : 0);

449

case kShiftRegCl:

450

return computeSize(entry, 0, false);

451

case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

452

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

453

return computeSize(entry, lir->operands[1], false);

454

case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

455

return computeSize(entry, lir->operands[3], true);

456

case kRegCond: // lir operands - 0: reg, 1: cond

457

return computeSize(entry, 0, false);

458

case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

459

CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte

460

return computeSize(entry, lir->operands[1], false);

461

case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

462

return computeSize(entry, lir->operands[3], true);

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

463

case kJcc:

464

if (lir->opcode == kX86Jcc8) {

465

return 2; // opcode + rel8

466

} else {

467

DCHECK(lir->opcode == kX86Jcc32);

468

return 6; // 2 byte opcode + rel32

469

}

470

case kJmp:

471

if (lir->opcode == kX86Jmp8) {

472

return 2; // opcode + rel8

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

473

} else if (lir->opcode == kX86Jmp32) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

474

return 5; // opcode + rel32

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

475

} else {

476

DCHECK(lir->opcode == kX86JmpR);

477

return 2; // opcode + modrm

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

478

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

479

case kCall:

Elliott Hughes

b25c3f6

2012-03-26 16:35:06 -0700

[diff] [blame]

480

switch (lir->opcode) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

481

case kX86CallR: return 2; // opcode modrm

482

case kX86CallM: // lir operands - 0: base, 1: disp

483

return computeSize(entry, lir->operands[1], false);

484

case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

485

return computeSize(entry, lir->operands[3], true);

Ian Rogers

6cbb2bd

2012-03-16 13:45:30 -0700

[diff] [blame]

486

case kX86CallT: // lir operands - 0: disp

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

487

return computeSize(entry, 0x12345678, false); // displacement size is always 32bit

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

default:

break;

}

break;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

492

case kPcRel:

493

if (entry->opcode == kX86PcRelLoadRA) {

494

// lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

495

return computeSize(entry, 0x12345678, true);

496

} else {

497

DCHECK(entry->opcode == kX86PcRelAdr);

498

return 5; // opcode with reg + 4 byte immediate

499

}

500

case kMacro:

501

DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));

502

return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +

503

computeSize(&EncodingMap[kX86Sub32RI], 0, false) -

504

(lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

Ian Rogers

2012-03-06 10:18:10 -0800

[diff] [blame]

509

return 0;

510

}

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

511

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

512

static uint8_t modrmForDisp(int base, int disp) {

513

// BP requires an explicit disp, so do not omit it in the 0 case

514

if (disp == 0 && base != rBP) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

515

return 0;

516

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

523

static void emitDisp(CompilationUnit* cUnit, int base, int disp) {

524

// BP requires an explicit disp, so do not omit it in the 0 case

525

if (disp == 0 && base != rBP) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

526

return;

527

} else if (IS_SIMM8(disp)) {

528

cUnit->codeBuffer.push_back(disp & 0xFF);

529

} else {

530

cUnit->codeBuffer.push_back(disp & 0xFF);

531

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

532

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

533

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

}

}

static void emitOpReg(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg) {

538

if (entry->skeleton.prefix1 != 0) {

539

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

540

if (entry->skeleton.prefix2 != 0) {

541

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

542

}

543

} else {

544

DCHECK_EQ(0, entry->skeleton.prefix2);

545

}

546

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

547

if (entry->skeleton.opcode == 0x0F) {

548

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

549

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

550

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

551

} else {

552

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

553

}

554

} else {

555

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

556

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

557

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

558

if (FPREG(reg)) {

559

reg = reg & FP_REG_MASK;

560

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

561

if (reg >= 4) {

562

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg

563

<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);

564

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

565

DCHECK_LT(reg, 8);

566

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

567

cUnit->codeBuffer.push_back(modrm);

568

DCHECK_EQ(0, entry->skeleton.ax_opcode);

569

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

570

}

571

572

static void emitOpMem(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t base, int disp) {

573

if (entry->skeleton.prefix1 != 0) {

574

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

575

if (entry->skeleton.prefix2 != 0) {

576

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

577

}

578

} else {

579

DCHECK_EQ(0, entry->skeleton.prefix2);

580

}

581

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

582

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

583

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

584

DCHECK_LT(entry->skeleton.modrm_opcode, 8);

585

DCHECK_LT(base, 8);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

586

uint8_t modrm = (modrmForDisp(base, disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

587

cUnit->codeBuffer.push_back(modrm);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

588

emitDisp(cUnit, base, disp);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

589

DCHECK_EQ(0, entry->skeleton.ax_opcode);

590

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

591

}

592

593

static void emitMemReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

594

uint8_t base, int disp, uint8_t reg) {

595

if (entry->skeleton.prefix1 != 0) {

596

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

597

if (entry->skeleton.prefix2 != 0) {

598

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

599

}

600

} else {

601

DCHECK_EQ(0, entry->skeleton.prefix2);

602

}

603

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

604

if (entry->skeleton.opcode == 0x0F) {

605

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

606

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

607

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

608

} else {

609

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

610

}

611

} else {

612

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

613

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

614

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

615

if (FPREG(reg)) {

616

reg = reg & FP_REG_MASK;

617

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

618

if (reg >= 4) {

619

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg

620

<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);

621

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

622

DCHECK_LT(reg, 8);

623

DCHECK_LT(base, 8);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

624

uint8_t modrm = (modrmForDisp(base, disp) << 6) | (reg << 3) | base;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

625

cUnit->codeBuffer.push_back(modrm);

626

if (base == rSP) {

627

// Special SIB for SP base

628

cUnit->codeBuffer.push_back(0 << 6 | (rSP << 3) | rSP);

629

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

630

emitDisp(cUnit, base, disp);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

631

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

632

DCHECK_EQ(0, entry->skeleton.ax_opcode);

633

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

634

}

635

636

static void emitRegMem(CompilationUnit* cUnit, const X86EncodingMap* entry,

637

uint8_t reg, uint8_t base, int disp) {

638

// Opcode will flip operands.

639

emitMemReg(cUnit, entry, base, disp, reg);

640

}

641

642

static void emitRegArray(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg,

643

uint8_t base, uint8_t index, int scale, int disp) {

644

if (entry->skeleton.prefix1 != 0) {

645

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

646

if (entry->skeleton.prefix2 != 0) {

647

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

648

}

649

} else {

650

DCHECK_EQ(0, entry->skeleton.prefix2);

651

}

652

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

653

if (entry->skeleton.opcode == 0x0F) {

654

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

655

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

656

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

657

} else {

658

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

659

}

660

} else {

661

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

662

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

663

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

664

if (FPREG(reg)) {

665

reg = reg & FP_REG_MASK;

666

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

667

DCHECK_LT(reg, 8);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

668

uint8_t modrm = (modrmForDisp(base, disp) << 6) | (reg << 3) | rSP;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

669

cUnit->codeBuffer.push_back(modrm);

DCHECK_LT(scale, 4);

DCHECK_LT(index, 8);

DCHECK_LT(base, 8);

uint8_t sib = (scale << 6) | (index << 3) | base;

674

cUnit->codeBuffer.push_back(sib);

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

675

emitDisp(cUnit, base, disp);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

676

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

677

DCHECK_EQ(0, entry->skeleton.ax_opcode);

678

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

679

}

680

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

681

static void emitArrayReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

682

uint8_t base, uint8_t index, int scale, int disp, uint8_t reg) {

683

// Opcode will flip operands.

684

emitRegArray(cUnit, entry, reg, base, index, scale, disp);

685

}

686

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

687

static void emitRegThread(CompilationUnit* cUnit, const X86EncodingMap* entry,

688

uint8_t reg, int disp) {

689

DCHECK_NE(entry->skeleton.prefix1, 0);

690

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

691

if (entry->skeleton.prefix2 != 0) {

692

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

693

}

694

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

695

if (entry->skeleton.opcode == 0x0F) {

696

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

697

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

698

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

699

} else {

700

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

701

}

702

} else {

703

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

704

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

705

}

706

if (FPREG(reg)) {

707

reg = reg & FP_REG_MASK;

708

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

709

if (reg >= 4) {

710

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg

711

<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);

712

}

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

713

DCHECK_LT(reg, 8);

714

uint8_t modrm = (0 << 6) | (reg << 3) | rBP;

715

cUnit->codeBuffer.push_back(modrm);

716

cUnit->codeBuffer.push_back(disp & 0xFF);

717

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

718

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

719

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

720

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

721

DCHECK_EQ(0, entry->skeleton.ax_opcode);

722

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

723

}

724

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

725

static void emitRegReg(CompilationUnit* cUnit, const X86EncodingMap* entry,

726

uint8_t reg1, uint8_t reg2) {

727

if (entry->skeleton.prefix1 != 0) {

728

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

729

if (entry->skeleton.prefix2 != 0) {

730

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

731

}

732

} else {

733

DCHECK_EQ(0, entry->skeleton.prefix2);

734

}

735

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

736

if (entry->skeleton.opcode == 0x0F) {

737

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

738

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

739

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

740

} else {

741

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

742

}

743

} else {

744

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

745

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

746

}

Ian Rogers

2012-03-13 18:45:39 -0700

[diff] [blame]

747

if (FPREG(reg1)) {

748

reg1 = reg1 & FP_REG_MASK;

749

}

750

if (FPREG(reg2)) {

751

reg2 = reg2 & FP_REG_MASK;

752

}

753

DCHECK_LT(reg1, 8);

754

DCHECK_LT(reg2, 8);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

755

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

756

cUnit->codeBuffer.push_back(modrm);

757

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

758

DCHECK_EQ(0, entry->skeleton.ax_opcode);

759

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

760

}

761

Elliott Hughes

225ae52

2012-04-16 20:21:45 -0700

[diff] [blame]

762

static void emitRegRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

763

uint8_t reg1, uint8_t reg2, int32_t imm) {

764

if (entry->skeleton.prefix1 != 0) {

765

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

766

if (entry->skeleton.prefix2 != 0) {

767

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

768

}

769

} else {

770

DCHECK_EQ(0, entry->skeleton.prefix2);

771

}

772

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

773

if (entry->skeleton.opcode == 0x0F) {

774

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

775

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

776

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

777

} else {

778

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

779

}

780

} else {

781

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

782

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

783

}

784

if (FPREG(reg1)) {

785

reg1 = reg1 & FP_REG_MASK;

786

}

787

if (FPREG(reg2)) {

788

reg2 = reg2 & FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

793

cUnit->codeBuffer.push_back(modrm);

794

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

795

DCHECK_EQ(0, entry->skeleton.ax_opcode);

796

switch (entry->skeleton.immediate_bytes) {

797

case 1:

798

DCHECK(IS_SIMM8(imm));

799

cUnit->codeBuffer.push_back(imm & 0xFF);

800

break;

801

case 2:

802

DCHECK(IS_SIMM16(imm));

803

cUnit->codeBuffer.push_back(imm & 0xFF);

804

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

805

break;

806

case 4:

807

cUnit->codeBuffer.push_back(imm & 0xFF);

808

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

809

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

810

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

811

break;

812

default:

813

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

814

<< ") for instruction: " << entry->name;

break;

}

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

819

static void emitRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

820

uint8_t reg, int imm) {

821

if (entry->skeleton.prefix1 != 0) {

822

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

823

if (entry->skeleton.prefix2 != 0) {

824

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

825

}

826

} else {

827

DCHECK_EQ(0, entry->skeleton.prefix2);

828

}

829

if (reg == rAX && entry->skeleton.ax_opcode != 0) {

830

cUnit->codeBuffer.push_back(entry->skeleton.ax_opcode);

831

} else {

832

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

833

if (entry->skeleton.opcode == 0x0F) {

834

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

835

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

836

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

837

} else {

838

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

839

}

840

} else {

841

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

842

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

843

}

jeffhao

2012-07-11 16:08:43 -0700

[diff] [blame]

844

if (FPREG(reg)) {

845

reg = reg & FP_REG_MASK;

846

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

847

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

848

cUnit->codeBuffer.push_back(modrm);

849

}

850

switch (entry->skeleton.immediate_bytes) {

851

case 1:

852

DCHECK(IS_SIMM8(imm));

853

cUnit->codeBuffer.push_back(imm & 0xFF);

854

break;

855

case 2:

856

DCHECK(IS_SIMM16(imm));

857

cUnit->codeBuffer.push_back(imm & 0xFF);

858

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

859

break;

860

case 4:

861

cUnit->codeBuffer.push_back(imm & 0xFF);

862

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

863

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

864

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

865

break;

866

default:

867

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

868

<< ") for instruction: " << entry->name;

break;

}

}

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

873

static void emitThreadImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

874

int disp, int imm) {

875

if (entry->skeleton.prefix1 != 0) {

876

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

877

if (entry->skeleton.prefix2 != 0) {

878

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

879

}

880

} else {

881

DCHECK_EQ(0, entry->skeleton.prefix2);

882

}

883

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

884

if (entry->skeleton.opcode == 0x0F) {

885

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

886

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

887

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

888

} else {

889

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

890

}

891

} else {

892

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

893

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

894

}

895

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

896

cUnit->codeBuffer.push_back(modrm);

897

cUnit->codeBuffer.push_back(disp & 0xFF);

898

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

899

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

900

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

901

switch (entry->skeleton.immediate_bytes) {

902

case 1:

903

DCHECK(IS_SIMM8(imm));

904

cUnit->codeBuffer.push_back(imm & 0xFF);

905

break;

906

case 2:

907

DCHECK(IS_SIMM16(imm));

908

cUnit->codeBuffer.push_back(imm & 0xFF);

909

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

910

break;

911

case 4:

912

cUnit->codeBuffer.push_back(imm & 0xFF);

913

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

914

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

915

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

916

break;

917

default:

918

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

919

<< ") for instruction: " << entry->name;

920

break;

921

}

922

DCHECK_EQ(entry->skeleton.ax_opcode, 0);

923

}

924

925

static void emitMovRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

926

uint8_t reg, int imm) {

927

DCHECK_LT(reg, 8);

928

cUnit->codeBuffer.push_back(0xB8 + reg);

929

cUnit->codeBuffer.push_back(imm & 0xFF);

930

cUnit->codeBuffer.push_back((imm >> 8) & 0xFF);

931

cUnit->codeBuffer.push_back((imm >> 16) & 0xFF);

932

cUnit->codeBuffer.push_back((imm >> 24) & 0xFF);

933

}

934

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

935

static void emitShiftRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

936

uint8_t reg, int imm) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

937

if (entry->skeleton.prefix1 != 0) {

938

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

939

if (entry->skeleton.prefix2 != 0) {

940

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

941

}

942

} else {

943

DCHECK_EQ(0, entry->skeleton.prefix2);

944

}

945

if (imm != 1) {

946

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

947

} else {

948

// Shorter encoding for 1 bit shift

949

cUnit->codeBuffer.push_back(entry->skeleton.ax_opcode);

950

}

951

if (entry->skeleton.opcode == 0x0F) {

952

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

953

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

954

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

955

} else {

956

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

957

}

958

} else {

959

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

960

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

961

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

962

if (reg >= 4) {

963

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg

964

<< " in " << PrettyMethod(cUnit->method_idx, *cUnit->dex_file);

965

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

966

DCHECK_LT(reg, 8);

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

967

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

968

cUnit->codeBuffer.push_back(modrm);

969

if (imm != 1) {

970

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

971

DCHECK(IS_SIMM8(imm));

972

cUnit->codeBuffer.push_back(imm & 0xFF);

}

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

976

static void emitShiftRegCl(CompilationUnit* cUnit, const X86EncodingMap* entry,

977

uint8_t reg, uint8_t cl) {

978

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

979

if (entry->skeleton.prefix1 != 0) {

980

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

981

if (entry->skeleton.prefix2 != 0) {

982

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

983

}

984

} else {

985

DCHECK_EQ(0, entry->skeleton.prefix2);

986

}

987

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

988

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

989

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

990

DCHECK_LT(reg, 8);

991

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

992

cUnit->codeBuffer.push_back(modrm);

993

DCHECK_EQ(0, entry->skeleton.ax_opcode);

994

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

995

}

996

997

static void emitRegCond(CompilationUnit* cUnit, const X86EncodingMap* entry,

998

uint8_t reg, uint8_t condition) {

999

if (entry->skeleton.prefix1 != 0) {

1000

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

1001

if (entry->skeleton.prefix2 != 0) {

1002

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1003

}

1004

} else {

1005

DCHECK_EQ(0, entry->skeleton.prefix2);

1006

}

1007

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1008

DCHECK_EQ(0x0F, entry->skeleton.opcode);

1009

cUnit->codeBuffer.push_back(0x0F);

1010

DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);

1011

cUnit->codeBuffer.push_back(0x90 | condition);

1012

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1013

DCHECK_LT(reg, 8);

1014

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

1015

cUnit->codeBuffer.push_back(modrm);

1016

DCHECK_EQ(entry->skeleton.immediate_bytes, 0);

1017

}

1018

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1019

static void emitJmp(CompilationUnit* cUnit, const X86EncodingMap* entry, int rel) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1020

if (entry->opcode == kX86Jmp8) {

1021

DCHECK(IS_SIMM8(rel));

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1022

cUnit->codeBuffer.push_back(0xEB);

1023

cUnit->codeBuffer.push_back(rel & 0xFF);

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1024

} else if (entry->opcode == kX86Jmp32) {

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1025

cUnit->codeBuffer.push_back(0xE9);

1026

cUnit->codeBuffer.push_back(rel & 0xFF);

1027

cUnit->codeBuffer.push_back((rel >> 8) & 0xFF);

1028

cUnit->codeBuffer.push_back((rel >> 16) & 0xFF);

1029

cUnit->codeBuffer.push_back((rel >> 24) & 0xFF);

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1030

} else {

1031

DCHECK(entry->opcode == kX86JmpR);

1032

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1033

uint8_t reg = static_cast<uint8_t>(rel);

1034

DCHECK_LT(reg, 8);

1035

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

1036

cUnit->codeBuffer.push_back(modrm);

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

}

}

static void emitJcc(CompilationUnit* cUnit, const X86EncodingMap* entry,

1041

int rel, uint8_t cc) {

1042

DCHECK_LT(cc, 16);

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1043

if (entry->opcode == kX86Jcc8) {

1044

DCHECK(IS_SIMM8(rel));

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1045

cUnit->codeBuffer.push_back(0x70 | cc);

1046

cUnit->codeBuffer.push_back(rel & 0xFF);

1047

} else {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1048

DCHECK(entry->opcode == kX86Jcc32);

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1049

cUnit->codeBuffer.push_back(0x0F);

1050

cUnit->codeBuffer.push_back(0x80 | cc);

1051

cUnit->codeBuffer.push_back(rel & 0xFF);

1052

cUnit->codeBuffer.push_back((rel >> 8) & 0xFF);

1053

cUnit->codeBuffer.push_back((rel >> 16) & 0xFF);

1054

cUnit->codeBuffer.push_back((rel >> 24) & 0xFF);

}

}

static void emitCallMem(CompilationUnit* cUnit, const X86EncodingMap* entry,

1059

uint8_t base, int disp) {

1060

if (entry->skeleton.prefix1 != 0) {

1061

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

1062

if (entry->skeleton.prefix2 != 0) {

1063

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1064

}

1065

} else {

1066

DCHECK_EQ(0, entry->skeleton.prefix2);

1067

}

1068

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1069

if (entry->skeleton.opcode == 0x0F) {

1070

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

1071

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

1072

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

1073

} else {

1074

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1075

}

1076

} else {

1077

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1078

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1079

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

1080

uint8_t modrm = (modrmForDisp(base, disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1081

cUnit->codeBuffer.push_back(modrm);

1082

if (base == rSP) {

1083

// Special SIB for SP base

1084

cUnit->codeBuffer.push_back(0 << 6 | (rSP << 3) | rSP);

1085

}

jeffhao

2012-07-13 17:25:52 -0700

[diff] [blame]

1086

emitDisp(cUnit, base, disp);

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1087

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1088

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1089

}

1090

1091

static void emitCallThread(CompilationUnit* cUnit, const X86EncodingMap* entry, int disp) {

1092

DCHECK_NE(entry->skeleton.prefix1, 0);

1093

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

1094

if (entry->skeleton.prefix2 != 0) {

1095

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1096

}

1097

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1098

if (entry->skeleton.opcode == 0x0F) {

1099

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

1100

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) {

1101

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

1102

} else {

1103

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1104

}

1105

} else {

1106

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1107

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1108

}

1109

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

1110

cUnit->codeBuffer.push_back(modrm);

1111

cUnit->codeBuffer.push_back(disp & 0xFF);

1112

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

1113

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

1114

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

1115

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1116

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1117

}

1118

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1119

static void emitPcRel(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg,

1120

int base_or_table, uint8_t index, int scale, int table_or_disp) {

1121

int disp;

1122

if (entry->opcode == kX86PcRelLoadRA) {

1123

SwitchTable *tabRec = (SwitchTable*)table_or_disp;

1124

disp = tabRec->offset;

1125

} else {

1126

DCHECK(entry->opcode == kX86PcRelAdr);

1127

FillArrayData *tabRec = (FillArrayData *)base_or_table;

1128

disp = tabRec->offset;

1129

}

1130

if (entry->skeleton.prefix1 != 0) {

1131

cUnit->codeBuffer.push_back(entry->skeleton.prefix1);

1132

if (entry->skeleton.prefix2 != 0) {

1133

cUnit->codeBuffer.push_back(entry->skeleton.prefix2);

1134

}

1135

} else {

1136

DCHECK_EQ(0, entry->skeleton.prefix2);

1137

}

1138

if (FPREG(reg)) {

1139

reg = reg & FP_REG_MASK;

1140

}

1141

DCHECK_LT(reg, 8);

1142

if (entry->opcode == kX86PcRelLoadRA) {

1143

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

1144

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1145

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1146

uint8_t modrm = (2 << 6) | (reg << 3) | rSP;

1147

cUnit->codeBuffer.push_back(modrm);

1148

DCHECK_LT(scale, 4);

1149

DCHECK_LT(index, 8);

1150

DCHECK_LT(base_or_table, 8);

1151

uint8_t base = static_cast<uint8_t>(base_or_table);

1152

uint8_t sib = (scale << 6) | (index << 3) | base;

1153

cUnit->codeBuffer.push_back(sib);

1154

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1155

} else {

1156

cUnit->codeBuffer.push_back(entry->skeleton.opcode + reg);

1157

}

1158

cUnit->codeBuffer.push_back(disp & 0xFF);

1159

cUnit->codeBuffer.push_back((disp >> 8) & 0xFF);

1160

cUnit->codeBuffer.push_back((disp >> 16) & 0xFF);

1161

cUnit->codeBuffer.push_back((disp >> 24) & 0xFF);

1162

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1163

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1164

}

1165

1166

static void emitMacro(CompilationUnit* cUnit, const X86EncodingMap* entry,

1167

uint8_t reg, int offset) {

1168

DCHECK(entry->opcode == kX86StartOfMethod) << entry->name;

1169

cUnit->codeBuffer.push_back(0xE8); // call +0

1170

cUnit->codeBuffer.push_back(0);

1171

cUnit->codeBuffer.push_back(0);

1172

cUnit->codeBuffer.push_back(0);

1173

cUnit->codeBuffer.push_back(0);

1174

1175

DCHECK_LT(reg, 8);

1176

cUnit->codeBuffer.push_back(0x58 + reg); // pop reg

1177

1178

emitRegImm(cUnit, &EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */);

1179

}

1180

Ian Rogers

6cbb2bd

2012-03-16 13:45:30 -0700

[diff] [blame]

1181

void emitUnimplemented(CompilationUnit* cUnit, const X86EncodingMap* entry, LIR* lir) {

Elliott Hughes

225ae52

2012-04-16 20:21:45 -0700

[diff] [blame]

1182

UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " " << buildInsnString(entry->fmt, lir, 0);

Ian Rogers

141b0c7

2012-03-15 18:18:52 -0700

[diff] [blame]

1183

for (int i = 0; i < oatGetInsnSize(lir); ++i) {

1184

cUnit->codeBuffer.push_back(0xCC); // push breakpoint instruction - int 3

}

}

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1188

/*

1189

* Assemble the LIR into binary instruction format. Note that we may

1190

* discover that pc-relative displacements may not fit the selected

1191

* instruction. In those cases we will try to substitute a new code

1192

* sequence or request that the trace be shortened and retried.

1193

*/

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1194

AssemblerStatus oatAssembleInstructions(CompilationUnit *cUnit, intptr_t startAddr) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1195

LIR *lir;

1196

AssemblerStatus res = kSuccess; // Assume success

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1197

Ian Rogers

141d622

2012-04-05 12:23:06 -0700

[diff] [blame]

1198

const bool kVerbosePcFixup = false;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1199

for (lir = (LIR *) cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {

1200

if (lir->opcode < 0) {

1201

continue;

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1202

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1203

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1204

if (lir->flags.isNop) {

continue;

}

if (lir->flags.pcRelFixup) {

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1209

switch (lir->opcode) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1210

case kX86Jcc8: {

1211

LIR *targetLIR = lir->target;

1212

DCHECK(targetLIR != NULL);

1213

int delta = 0;

1214

intptr_t pc;

1215

if (IS_SIMM8(lir->operands[0])) {

1216

pc = lir->offset + 2 /* opcode + rel8 */;

1217

} else {

1218

pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1219

}

1220

intptr_t target = targetLIR->offset;

1221

delta = target - pc;

1222

if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1223

if (kVerbosePcFixup) {

1224

LOG(INFO) << "Retry for JCC growth at " << lir->offset

1225

<< " delta: " << delta << " old delta: " << lir->operands[0];

1226

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1227

lir->opcode = kX86Jcc32;

buzbee

b046e16

2012-10-30 15:48:42 -0700

[diff] [blame]

1228

oatSetupResourceMasks(cUnit, lir);

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1229

res = kRetryAll;

1230

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1231

if (kVerbosePcFixup) {

1232

LOG(INFO) << "Source:";

1233

oatDumpLIRInsn(cUnit, lir, 0);

1234

LOG(INFO) << "Target:";

1235

oatDumpLIRInsn(cUnit, targetLIR, 0);

1236

LOG(INFO) << "Delta " << delta;

1237

}

1238

lir->operands[0] = delta;

break;

}

case kX86Jcc32: {

LIR *targetLIR = lir->target;

1243

DCHECK(targetLIR != NULL);

1244

intptr_t pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1245

intptr_t target = targetLIR->offset;

1246

int delta = target - pc;

1247

if (kVerbosePcFixup) {

1248

LOG(INFO) << "Source:";

1249

oatDumpLIRInsn(cUnit, lir, 0);

1250

LOG(INFO) << "Target:";

1251

oatDumpLIRInsn(cUnit, targetLIR, 0);

1252

LOG(INFO) << "Delta " << delta;

1253

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1254

lir->operands[0] = delta;

1255

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1256

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1257

case kX86Jmp8: {

1258

LIR *targetLIR = lir->target;

1259

DCHECK(targetLIR != NULL);

1260

int delta = 0;

1261

intptr_t pc;

1262

if (IS_SIMM8(lir->operands[0])) {

1263

pc = lir->offset + 2 /* opcode + rel8 */;

1264

} else {

1265

pc = lir->offset + 5 /* opcode + rel32 */;

1266

}

1267

intptr_t target = targetLIR->offset;

1268

delta = target - pc;

jeffhao

2012-06-28 11:29:57 -0700

[diff] [blame]

1269

if (!(cUnit->disableOpt & (1 << kSafeOptimizations)) && delta == 0) {

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1270

// Useless branch

1271

lir->flags.isNop = true;

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1272

if (kVerbosePcFixup) {

1273

LOG(INFO) << "Retry for useless branch at " << lir->offset;

1274

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1275

res = kRetryAll;

1276

} else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1277

if (kVerbosePcFixup) {

1278

LOG(INFO) << "Retry for JMP growth at " << lir->offset;

1279

}

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1280

lir->opcode = kX86Jmp32;

buzbee

b046e16

2012-10-30 15:48:42 -0700

[diff] [blame]

1281

oatSetupResourceMasks(cUnit, lir);

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1282

res = kRetryAll;

1283

}

1284

lir->operands[0] = delta;

1285

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1286

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1287

case kX86Jmp32: {

1288

LIR *targetLIR = lir->target;

1289

DCHECK(targetLIR != NULL);

1290

intptr_t pc = lir->offset + 5 /* opcode + rel32 */;

1291

intptr_t target = targetLIR->offset;

1292

int delta = target - pc;

1293

lir->operands[0] = delta;

1294

break;

1295

}

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1296

default:

1297

break;

1298

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

}

/*

* If one of the pc-relative instructions expanded we'll have

1303

* to make another pass. Don't bother to fully assemble the

1304

* instruction.

1305

*/

1306

if (res != kSuccess) {

1307

continue;

1308

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1309

CHECK_EQ(static_cast<size_t>(lir->offset), cUnit->codeBuffer.size());

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1310

const X86EncodingMap *entry = &EncodingMap[lir->opcode];

Ian Rogers

141b0c7

2012-03-15 18:18:52 -0700

[diff] [blame]

1311

size_t starting_cbuf_size = cUnit->codeBuffer.size();

Elliott Hughes

b25c3f6

2012-03-26 16:35:06 -0700

[diff] [blame]

1312

switch (entry->kind) {

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1313

case kData: // 4 bytes of data

1314

cUnit->codeBuffer.push_back(lir->operands[0]);

1315

break;

1316

case kNullary: // 1 byte of opcode

1317

DCHECK_EQ(0, entry->skeleton.prefix1);

1318

DCHECK_EQ(0, entry->skeleton.prefix2);

1319

cUnit->codeBuffer.push_back(entry->skeleton.opcode);

Ian Rogers

2012-03-21 20:40:33 -0700

[diff] [blame]

1320

if (entry->skeleton.extra_opcode1 != 0) {

1321

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1);

1322

if (entry->skeleton.extra_opcode2 != 0) {

1323

cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2);

1324

}

1325

} else {

1326

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1327

}

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1328

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1329

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1330

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1331

break;

1332

case kReg: // lir operands - 0: reg

1333

emitOpReg(cUnit, entry, lir->operands[0]);

1334

break;

1335

case kMem: // lir operands - 0: base, 1: disp

1336

emitOpMem(cUnit, entry, lir->operands[0], lir->operands[1]);

1337

break;

1338

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

1339

emitMemReg(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1340

break;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1341

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

1342

emitArrayReg(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

1343

lir->operands[3], lir->operands[4]);

1344

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1345

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

1346

emitRegMem(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1347

break;

1348

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

1349

emitRegArray(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

1350

lir->operands[3], lir->operands[4]);

1351

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1352

case kRegThread: // lir operands - 0: reg, 1: disp

1353

emitRegThread(cUnit, entry, lir->operands[0], lir->operands[1]);

1354

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1355

case kRegReg: // lir operands - 0: reg1, 1: reg2

1356

emitRegReg(cUnit, entry, lir->operands[0], lir->operands[1]);

1357

break;

jeffhao

2012-07-11 16:08:43 -0700

[diff] [blame]

1358

case kRegRegStore: // lir operands - 0: reg2, 1: reg1

1359

emitRegReg(cUnit, entry, lir->operands[1], lir->operands[0]);

1360

break;

Elliott Hughes

225ae52

2012-04-16 20:21:45 -0700

[diff] [blame]

1361

case kRegRegImm:

1362

emitRegRegImm(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1363

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1364

case kRegImm: // lir operands - 0: reg, 1: immediate

1365

emitRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1366

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1367

case kThreadImm: // lir operands - 0: disp, 1: immediate

1368

emitThreadImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1369

break;

1370

case kMovRegImm: // lir operands - 0: reg, 1: immediate

1371

emitMovRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1372

break;

Ian Rogers

2012-03-20 14:22:54 -0700

[diff] [blame]

1373

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

1374

emitShiftRegImm(cUnit, entry, lir->operands[0], lir->operands[1]);

1375

break;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1376

case kShiftRegCl: // lir operands - 0: reg, 1: cl

1377

emitShiftRegCl(cUnit, entry, lir->operands[0], lir->operands[1]);

1378

break;

1379

case kRegCond: // lir operands - 0: reg, 1: condition

1380

emitRegCond(cUnit, entry, lir->operands[0], lir->operands[1]);

1381

break;

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1382

case kJmp: // lir operands - 0: rel

1383

emitJmp(cUnit, entry, lir->operands[0]);

1384

break;

1385

case kJcc: // lir operands - 0: rel, 1: CC, target assigned

1386

emitJcc(cUnit, entry, lir->operands[0], lir->operands[1]);

1387

break;

1388

case kCall:

Elliott Hughes

b25c3f6

2012-03-26 16:35:06 -0700

[diff] [blame]

1389

switch (entry->opcode) {

Ian Rogers

2012-03-19 01:12:01 -0700

[diff] [blame]

1390

case kX86CallM: // lir operands - 0: base, 1: disp

1391

emitCallMem(cUnit, entry, lir->operands[0], lir->operands[1]);

1392

break;

1393

case kX86CallT: // lir operands - 0: disp

1394

emitCallThread(cUnit, entry, lir->operands[0]);

1395

break;

1396

default:

1397

emitUnimplemented(cUnit, entry, lir);

1398

break;

1399

}

1400

break;

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1401

case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

1402

emitPcRel(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2],

1403

lir->operands[3], lir->operands[4]);

1404

break;

1405

case kMacro:

1406

emitMacro(cUnit, entry, lir->operands[0], lir->offset);

1407

break;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1408

default:

Ian Rogers

6cbb2bd

2012-03-16 13:45:30 -0700

[diff] [blame]

1409

emitUnimplemented(cUnit, entry, lir);

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1410

break;

1411

}

Ian Rogers

2012-03-30 01:07:54 -0700

[diff] [blame]

1412

CHECK_EQ(static_cast<size_t>(oatGetInsnSize(lir)),

1413

cUnit->codeBuffer.size() - starting_cbuf_size)

1414

<< "Instruction size mismatch for entry: " << EncodingMap[lir->opcode].name;

Ian Rogers

2012-03-06 22:14:17 -0800

[diff] [blame]

1415

}

1416

return res;

buzbee

2012-03-05 11:19:57 -0800

[diff] [blame]

1417

}

1418

buzbee