Blame - compiler/dex/quick/x86/assemble_x86.cc - platform_art

2013-12-20 17:27:23 -0800

[diff] [blame]

180

{ kX86Cmov32RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, {0, 0, 0x0F, 0x40, 0, 0, 0, 0}, "Cmovcc32RR", "!2c !0r,!1r" },

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Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \

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{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \

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{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \

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{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \

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{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }

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SHIFT_ENCODING_MAP(Rol, 0x0),

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SHIFT_ENCODING_MAP(Ror, 0x1),

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SHIFT_ENCODING_MAP(Rcl, 0x2),

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SHIFT_ENCODING_MAP(Rcr, 0x3),

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SHIFT_ENCODING_MAP(Sal, 0x4),

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SHIFT_ENCODING_MAP(Shr, 0x5),

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SHIFT_ENCODING_MAP(Sar, 0x7),

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#undef SHIFT_ENCODING_MAP

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{ kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0}, "Cmc", "" },

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame^]

214

{ kX86Shld32RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1}, "Shld32", "!0r,!1r,!2d" },

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{ kX86Shrd32RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1}, "Shrd32", "!0r,!1r,!2d" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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{ kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" },

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{ kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" },

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{ kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" },

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{ kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" },

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{ kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" },

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{ kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" },

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{ kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0}, "Test32RR", "!0r,!1r" },

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#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \

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reg, reg_kind, reg_flags, \

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mem, mem_kind, mem_flags, \

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arr, arr_kind, arr_flags, imm, \

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b_flags, hw_flags, w_flags, \

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b_format, hw_format, w_format) \

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{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, #b_format "!0r" }, \

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{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, #b_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, #b_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, #hw_format "!0r" }, \

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{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, #hw_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, #hw_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, #w_format "!0r" }, \

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{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, #w_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, #w_format "[!0r+!1r<<!2d+!3d]" }

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UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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Mark Mendell

2bf31e6

2014-01-23 12:13:40 -0800

[diff] [blame]

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UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

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UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#undef UNARY_ENCODING_MAP

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Mark Mendell

2bf31e6

2014-01-23 12:13:40 -0800

[diff] [blame]

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{ kx86Cdq32Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { 0, 0, 0x99, 0, 0, 0, 0, 0 }, "Cdq", "" },

Vladimir Marko

a6fd8ba

2013-12-13 10:53:49 +0000

[diff] [blame]

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{ kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0 }, "Bswap32R", "!0r" },

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{ kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0 }, "Push32R", "!0r" },

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{ kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0 }, "Pop32R", "!0r" },

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

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Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \

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{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

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{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

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EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),

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{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

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{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),

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{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

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{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0),

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EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0),

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{ kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" },

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{ kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" },

Mark Mendell

bff1ef0

2013-12-13 13:47:34 -0800

[diff] [blame]

296

{ kX86SqrtsdRR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0xF2, 0, 0x0F, 0x51, 0, 0, 0, 0 }, "SqrtsdRR", "!0r,!1r" },

Vladimir Marko

12f9628

2013-12-16 14:44:03 +0000

[diff] [blame]

297

{ kX86FstpdM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0 }, "FstpdM", "[!0r,!1d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),

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{ kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" },

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{ kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" },

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{ kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

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{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

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{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

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// TODO: load/store?

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// Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.

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{ kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },

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EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES),

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EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES),

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{ kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" },

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{ kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" },

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{ kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

318

{ kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" },

319

{ kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Vladimir Marko

70b797d

2013-12-03 15:25:24 +0000

[diff] [blame]

320

{ kX86LockCmpxchg8bM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1d]" },

321

{ kX86LockCmpxchg8bA, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

322

323

EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),

324

EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),

325

EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),

326

EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),

327

#undef EXT_0F_ENCODING_MAP

328

329

{ kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },

330

{ kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },

331

{ kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },

332

{ kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },

333

{ kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" },

334

{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

335

{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

336

{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

337

{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

Brian Carlstrom

b1eba21

2013-07-17 18:07:19 -0700

[diff] [blame]

338

{ kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

339

340

{ kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" },

341

{ kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },

342

{ kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" },

343

};

344

345

static size_t ComputeSize(const X86EncodingMap* entry, int base, int displacement, bool has_sib) {

346

size_t size = 0;

347

if (entry->skeleton.prefix1 > 0) {

348

++size;

349

if (entry->skeleton.prefix2 > 0) {

++size;

}

}

++size; // opcode

if (entry->skeleton.opcode == 0x0F) {

355

++size;

356

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

if (has_sib || base == rX86_SP) {

362

// SP requires a SIB byte.

363

++size;

364

}

365

if (displacement != 0 || base == rBP) {

366

// BP requires an explicit displacement, even when it's 0.

367

if (entry->opcode != kX86Lea32RA) {

368

DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name;

369

}

370

size += IS_SIMM8(displacement) ? 1 : 4;

371

}

372

size += entry->skeleton.immediate_bytes;

return size;

}

int X86Mir2Lir::GetInsnSize(LIR* lir) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

377

DCHECK(!IsPseudoLirOp(lir->opcode));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

378

const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode];

379

switch (entry->kind) {

380

case kData:

381

return 4; // 4 bytes of data

382

case kNop:

383

return lir->operands[0]; // length of nop is sole operand

384

case kNullary:

385

return 1; // 1 byte of opcode

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

386

case kRegOpcode: // lir operands - 0: reg

387

return ComputeSize(entry, 0, 0, false) - 1; // substract 1 for modrm

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

388

case kReg: // lir operands - 0: reg

389

return ComputeSize(entry, 0, 0, false);

390

case kMem: // lir operands - 0: base, 1: disp

391

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

392

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

393

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

394

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

395

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

396

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

397

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

398

case kThreadReg: // lir operands - 0: disp, 1: reg

399

return ComputeSize(entry, 0, lir->operands[0], false);

400

case kRegReg:

401

return ComputeSize(entry, 0, 0, false);

402

case kRegRegStore:

403

return ComputeSize(entry, 0, 0, false);

404

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

405

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

406

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

407

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

408

case kRegThread: // lir operands - 0: reg, 1: disp

409

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

410

case kRegImm: { // lir operands - 0: reg, 1: immediate

411

size_t size = ComputeSize(entry, 0, 0, false);

412

if (entry->skeleton.ax_opcode == 0) {

413

return size;

414

} else {

415

// AX opcodes don't require the modrm byte.

416

int reg = lir->operands[0];

417

return size - (reg == rAX ? 1 : 0);

418

}

419

}

420

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

421

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

422

case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

423

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

424

case kThreadImm: // lir operands - 0: disp, 1: imm

425

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

426

case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame^]

427

case kRegRegImmRev:

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

428

return ComputeSize(entry, 0, 0, false);

429

case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

430

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

431

case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

432

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

433

case kMovRegImm: // lir operands - 0: reg, 1: immediate

434

return 1 + entry->skeleton.immediate_bytes;

435

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

436

// Shift by immediate one has a shorter opcode.

437

return ComputeSize(entry, 0, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

438

case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

439

// Shift by immediate one has a shorter opcode.

440

return ComputeSize(entry, lir->operands[0], lir->operands[1], false) -

441

(lir->operands[2] == 1 ? 1 : 0);

442

case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

443

// Shift by immediate one has a shorter opcode.

444

return ComputeSize(entry, lir->operands[0], lir->operands[3], true) -

445

(lir->operands[4] == 1 ? 1 : 0);

446

case kShiftRegCl:

447

return ComputeSize(entry, 0, 0, false);

448

case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

449

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

450

case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

451

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

452

case kRegCond: // lir operands - 0: reg, 1: cond

453

return ComputeSize(entry, 0, 0, false);

454

case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

455

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

456

case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

457

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

458

case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: cond

459

return ComputeSize(entry, 0, 0, false);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

460

case kJcc:

461

if (lir->opcode == kX86Jcc8) {

462

return 2; // opcode + rel8

463

} else {

464

DCHECK(lir->opcode == kX86Jcc32);

465

return 6; // 2 byte opcode + rel32

466

}

467

case kJmp:

468

if (lir->opcode == kX86Jmp8) {

469

return 2; // opcode + rel8

470

} else if (lir->opcode == kX86Jmp32) {

471

return 5; // opcode + rel32

472

} else {

473

DCHECK(lir->opcode == kX86JmpR);

474

return 2; // opcode + modrm

475

}

476

case kCall:

477

switch (lir->opcode) {

478

case kX86CallR: return 2; // opcode modrm

479

case kX86CallM: // lir operands - 0: base, 1: disp

480

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

481

case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

482

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

483

case kX86CallT: // lir operands - 0: disp

484

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

default:

break;

}

break;

case kPcRel:

if (entry->opcode == kX86PcRelLoadRA) {

491

// lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

492

return ComputeSize(entry, lir->operands[1], 0x12345678, true);

493

} else {

494

DCHECK(entry->opcode == kX86PcRelAdr);

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

495

return 5; // opcode with reg + 4 byte immediate

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

496

}

497

case kMacro:

498

DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));

499

return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +

500

ComputeSize(&X86Mir2Lir::EncodingMap[kX86Sub32RI], 0, 0, false) -

501

(lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

return 0;

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

509

void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry) {

510

if (entry->skeleton.prefix1 != 0) {

511

code_buffer_.push_back(entry->skeleton.prefix1);

512

if (entry->skeleton.prefix2 != 0) {

513

code_buffer_.push_back(entry->skeleton.prefix2);

514

}

515

} else {

516

DCHECK_EQ(0, entry->skeleton.prefix2);

}

}

void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) {

521

code_buffer_.push_back(entry->skeleton.opcode);

522

if (entry->skeleton.opcode == 0x0F) {

523

code_buffer_.push_back(entry->skeleton.extra_opcode1);

524

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

525

code_buffer_.push_back(entry->skeleton.extra_opcode2);

526

} else {

527

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

528

}

529

} else {

530

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

531

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

}

}

void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry) {

EmitPrefix(entry);

EmitOpcode(entry);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

540

static uint8_t ModrmForDisp(int base, int disp) {

541

// BP requires an explicit disp, so do not omit it in the 0 case

542

if (disp == 0 && base != rBP) {

543

return 0;

544

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

551

void X86Mir2Lir::EmitDisp(uint8_t base, int disp) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

552

// BP requires an explicit disp, so do not omit it in the 0 case

553

if (disp == 0 && base != rBP) {

554

return;

555

} else if (IS_SIMM8(disp)) {

556

code_buffer_.push_back(disp & 0xFF);

557

} else {

558

code_buffer_.push_back(disp & 0xFF);

559

code_buffer_.push_back((disp >> 8) & 0xFF);

560

code_buffer_.push_back((disp >> 16) & 0xFF);

561

code_buffer_.push_back((disp >> 24) & 0xFF);

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

565

void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp) {

566

DCHECK_LT(reg_or_opcode, 8);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

567

DCHECK_LT(base, 8);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

568

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | base;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

569

code_buffer_.push_back(modrm);

570

if (base == rX86_SP) {

571

// Special SIB for SP base

572

code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);

573

}

574

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

575

}

576

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

577

void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index,

578

int scale, int disp) {

579

DCHECK_LT(reg_or_opcode, 8);

580

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | rX86_SP;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

581

code_buffer_.push_back(modrm);

DCHECK_LT(scale, 4);

DCHECK_LT(index, 8);

DCHECK_LT(base, 8);

uint8_t sib = (scale << 6) | (index << 3) | base;

586

code_buffer_.push_back(sib);

587

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

588

}

589

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

590

void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int imm) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

591

switch (entry->skeleton.immediate_bytes) {

592

case 1:

593

DCHECK(IS_SIMM8(imm));

594

code_buffer_.push_back(imm & 0xFF);

595

break;

596

case 2:

597

DCHECK(IS_SIMM16(imm));

598

code_buffer_.push_back(imm & 0xFF);

599

code_buffer_.push_back((imm >> 8) & 0xFF);

600

break;

601

case 4:

602

code_buffer_.push_back(imm & 0xFF);

603

code_buffer_.push_back((imm >> 8) & 0xFF);

604

code_buffer_.push_back((imm >> 16) & 0xFF);

605

code_buffer_.push_back((imm >> 24) & 0xFF);

606

break;

607

default:

608

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

609

<< ") for instruction: " << entry->name;

break;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

614

void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg) {

615

EmitPrefixAndOpcode(entry);

616

// There's no 3-byte instruction with +rd

617

DCHECK(entry->skeleton.opcode != 0x0F ||

618

(entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A));

619

DCHECK(!X86_FPREG(reg));

620

DCHECK_LT(reg, 8);

621

code_buffer_.back() += reg;

622

DCHECK_EQ(0, entry->skeleton.ax_opcode);

623

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

624

}

625

626

void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) {

627

EmitPrefixAndOpcode(entry);

628

if (X86_FPREG(reg)) {

629

reg = reg & X86_FP_REG_MASK;

630

}

631

if (reg >= 4) {

632

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

633

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

634

}

635

DCHECK_LT(reg, 8);

636

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

637

code_buffer_.push_back(modrm);

638

DCHECK_EQ(0, entry->skeleton.ax_opcode);

639

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

640

}

641

642

void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) {

643

EmitPrefix(entry);

644

code_buffer_.push_back(entry->skeleton.opcode);

645

DCHECK_NE(0x0F, entry->skeleton.opcode);

646

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

647

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

648

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

649

DCHECK_EQ(0, entry->skeleton.ax_opcode);

650

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

651

}

652

653

void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index,

654

int scale, int disp) {

655

EmitPrefixAndOpcode(entry);

656

EmitModrmSibDisp(entry->skeleton.modrm_opcode, base, index, scale, disp);

657

DCHECK_EQ(0, entry->skeleton.ax_opcode);

658

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

659

}

660

661

void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry,

662

uint8_t base, int disp, uint8_t reg) {

663

EmitPrefixAndOpcode(entry);

664

if (X86_FPREG(reg)) {

665

reg = reg & X86_FP_REG_MASK;

666

}

667

if (reg >= 4) {

668

DCHECK(strchr(entry->name, '8') == NULL ||

669

entry->opcode == kX86Movzx8RM || entry->opcode == kX86Movsx8RM)

670

<< entry->name << " " << static_cast<int>(reg)

671

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

672

}

673

EmitModrmDisp(reg, base, disp);

674

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

675

DCHECK_EQ(0, entry->skeleton.ax_opcode);

676

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

677

}

678

679

void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry,

680

uint8_t reg, uint8_t base, int disp) {

681

// Opcode will flip operands.

682

EmitMemReg(entry, base, disp, reg);

683

}

684

685

void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index,

686

int scale, int disp) {

687

EmitPrefixAndOpcode(entry);

688

if (X86_FPREG(reg)) {

689

reg = reg & X86_FP_REG_MASK;

690

}

691

EmitModrmSibDisp(reg, base, index, scale, disp);

692

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

693

DCHECK_EQ(0, entry->skeleton.ax_opcode);

694

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

695

}

696

697

void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp,

698

uint8_t reg) {

699

// Opcode will flip operands.

700

EmitRegArray(entry, reg, base, index, scale, disp);

701

}

702

703

void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) {

704

DCHECK_NE(entry->skeleton.prefix1, 0);

705

EmitPrefixAndOpcode(entry);

706

if (X86_FPREG(reg)) {

707

reg = reg & X86_FP_REG_MASK;

708

}

709

if (reg >= 4) {

710

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

711

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

712

}

713

DCHECK_LT(reg, 8);

714

uint8_t modrm = (0 << 6) | (reg << 3) | rBP;

715

code_buffer_.push_back(modrm);

716

code_buffer_.push_back(disp & 0xFF);

717

code_buffer_.push_back((disp >> 8) & 0xFF);

718

code_buffer_.push_back((disp >> 16) & 0xFF);

719

code_buffer_.push_back((disp >> 24) & 0xFF);

720

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

721

DCHECK_EQ(0, entry->skeleton.ax_opcode);

722

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

723

}

724

725

void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) {

726

EmitPrefixAndOpcode(entry);

727

if (X86_FPREG(reg1)) {

728

reg1 = reg1 & X86_FP_REG_MASK;

729

}

730

if (X86_FPREG(reg2)) {

731

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

736

code_buffer_.push_back(modrm);

737

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

738

DCHECK_EQ(0, entry->skeleton.ax_opcode);

739

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

740

}

741

742

void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry,

743

uint8_t reg1, uint8_t reg2, int32_t imm) {

744

EmitPrefixAndOpcode(entry);

745

if (X86_FPREG(reg1)) {

746

reg1 = reg1 & X86_FP_REG_MASK;

747

}

748

if (X86_FPREG(reg2)) {

749

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

754

code_buffer_.push_back(modrm);

755

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

756

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame^]

760

void X86Mir2Lir::EmitRegRegImmRev(const X86EncodingMap* entry,

761

uint8_t reg1, uint8_t reg2, int32_t imm) {

762

EmitRegRegImm(entry, reg2, reg1, imm);

763

}

764

765

void X86Mir2Lir::EmitRegMemImm(const X86EncodingMap* entry,

766

uint8_t reg, uint8_t base, int disp, int32_t imm) {

767

EmitPrefixAndOpcode(entry);

768

DCHECK(!X86_FPREG(reg));

769

DCHECK_LT(reg, 8);

770

EmitModrmDisp(reg, base, disp);

771

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

772

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

776

void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

777

if (entry->skeleton.prefix1 != 0) {

778

code_buffer_.push_back(entry->skeleton.prefix1);

779

if (entry->skeleton.prefix2 != 0) {

780

code_buffer_.push_back(entry->skeleton.prefix2);

781

}

782

} else {

783

DCHECK_EQ(0, entry->skeleton.prefix2);

784

}

785

if (reg == rAX && entry->skeleton.ax_opcode != 0) {

786

code_buffer_.push_back(entry->skeleton.ax_opcode);

787

} else {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

788

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

789

if (X86_FPREG(reg)) {

790

reg = reg & X86_FP_REG_MASK;

791

}

792

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

793

code_buffer_.push_back(modrm);

794

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

795

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

796

}

797

Mark Mendell

343adb5

2013-12-18 06:02:17 -0800

[diff] [blame]

798

void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm) {

799

EmitPrefixAndOpcode(entry);

800

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

801

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

805

void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

806

EmitPrefixAndOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

807

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

808

code_buffer_.push_back(modrm);

809

code_buffer_.push_back(disp & 0xFF);

810

code_buffer_.push_back((disp >> 8) & 0xFF);

811

code_buffer_.push_back((disp >> 16) & 0xFF);

812

code_buffer_.push_back((disp >> 24) & 0xFF);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

813

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

814

DCHECK_EQ(entry->skeleton.ax_opcode, 0);

815

}

816

817

void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

818

DCHECK_LT(reg, 8);

819

code_buffer_.push_back(0xB8 + reg);

820

code_buffer_.push_back(imm & 0xFF);

821

code_buffer_.push_back((imm >> 8) & 0xFF);

822

code_buffer_.push_back((imm >> 16) & 0xFF);

823

code_buffer_.push_back((imm >> 24) & 0xFF);

824

}

825

826

void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

827

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

828

if (imm != 1) {

829

code_buffer_.push_back(entry->skeleton.opcode);

830

} else {

831

// Shorter encoding for 1 bit shift

832

code_buffer_.push_back(entry->skeleton.ax_opcode);

833

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

834

DCHECK_NE(0x0F, entry->skeleton.opcode);

835

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

836

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

837

if (reg >= 4) {

838

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

839

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

840

}

841

DCHECK_LT(reg, 8);

842

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

843

code_buffer_.push_back(modrm);

844

if (imm != 1) {

845

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

846

DCHECK(IS_SIMM8(imm));

847

code_buffer_.push_back(imm & 0xFF);

}

}

void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl) {

852

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

853

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

854

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

855

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

856

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

857

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

858

DCHECK_LT(reg, 8);

859

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

860

code_buffer_.push_back(modrm);

861

DCHECK_EQ(0, entry->skeleton.ax_opcode);

862

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

863

}

864

865

void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) {

866

if (entry->skeleton.prefix1 != 0) {

867

code_buffer_.push_back(entry->skeleton.prefix1);

868

if (entry->skeleton.prefix2 != 0) {

869

code_buffer_.push_back(entry->skeleton.prefix2);

870

}

871

} else {

872

DCHECK_EQ(0, entry->skeleton.prefix2);

873

}

874

DCHECK_EQ(0, entry->skeleton.ax_opcode);

875

DCHECK_EQ(0x0F, entry->skeleton.opcode);

876

code_buffer_.push_back(0x0F);

877

DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);

878

code_buffer_.push_back(0x90 | condition);

879

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

880

DCHECK_LT(reg, 8);

881

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

882

code_buffer_.push_back(modrm);

883

DCHECK_EQ(entry->skeleton.immediate_bytes, 0);

884

}

885

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

886

void X86Mir2Lir::EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, uint8_t condition) {

887

// Generate prefix and opcode without the condition

888

EmitPrefixAndOpcode(entry);

889

890

// Now add the condition. The last byte of opcode is the one that receives it.

891

DCHECK_LE(condition, 0xF);

892

code_buffer_.back() += condition;

893

894

// Not expecting to have to encode immediate or do anything special for ModR/M since there are two registers.

895

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

896

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

897

898

// Check that registers requested for encoding are sane.

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

// For register to register encoding, the mod is 3.

903

const uint8_t mod = (3 << 6);

904

905

// Encode the ModR/M byte now.

906

const uint8_t modrm = mod | (reg1 << 3) | reg2;

907

code_buffer_.push_back(modrm);

908

}

909

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

910

void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int rel) {

911

if (entry->opcode == kX86Jmp8) {

912

DCHECK(IS_SIMM8(rel));

913

code_buffer_.push_back(0xEB);

914

code_buffer_.push_back(rel & 0xFF);

915

} else if (entry->opcode == kX86Jmp32) {

916

code_buffer_.push_back(0xE9);

917

code_buffer_.push_back(rel & 0xFF);

918

code_buffer_.push_back((rel >> 8) & 0xFF);

919

code_buffer_.push_back((rel >> 16) & 0xFF);

920

code_buffer_.push_back((rel >> 24) & 0xFF);

921

} else {

922

DCHECK(entry->opcode == kX86JmpR);

923

code_buffer_.push_back(entry->skeleton.opcode);

924

uint8_t reg = static_cast<uint8_t>(rel);

925

DCHECK_LT(reg, 8);

926

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

927

code_buffer_.push_back(modrm);

}

}

void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc) {

932

DCHECK_LT(cc, 16);

933

if (entry->opcode == kX86Jcc8) {

934

DCHECK(IS_SIMM8(rel));

935

code_buffer_.push_back(0x70 | cc);

936

code_buffer_.push_back(rel & 0xFF);

937

} else {

938

DCHECK(entry->opcode == kX86Jcc32);

939

code_buffer_.push_back(0x0F);

940

code_buffer_.push_back(0x80 | cc);

941

code_buffer_.push_back(rel & 0xFF);

942

code_buffer_.push_back((rel >> 8) & 0xFF);

943

code_buffer_.push_back((rel >> 16) & 0xFF);

944

code_buffer_.push_back((rel >> 24) & 0xFF);

}

}

void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

949

EmitPrefixAndOpcode(entry);

950

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

951

DCHECK_EQ(0, entry->skeleton.ax_opcode);

952

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

953

}

954

955

void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int disp) {

956

DCHECK_NE(entry->skeleton.prefix1, 0);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

957

EmitPrefixAndOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

958

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

959

code_buffer_.push_back(modrm);

960

code_buffer_.push_back(disp & 0xFF);

961

code_buffer_.push_back((disp >> 8) & 0xFF);

962

code_buffer_.push_back((disp >> 16) & 0xFF);

963

code_buffer_.push_back((disp >> 24) & 0xFF);

964

DCHECK_EQ(0, entry->skeleton.ax_opcode);

965

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

966

}

967

968

void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, uint8_t reg,

969

int base_or_table, uint8_t index, int scale, int table_or_disp) {

970

int disp;

971

if (entry->opcode == kX86PcRelLoadRA) {

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

972

Mir2Lir::EmbeddedData *tab_rec =

973

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

974

disp = tab_rec->offset;

975

} else {

976

DCHECK(entry->opcode == kX86PcRelAdr);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

977

Mir2Lir::EmbeddedData *tab_rec =

978

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(base_or_table));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

979

disp = tab_rec->offset;

980

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

981

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

982

if (X86_FPREG(reg)) {

983

reg = reg & X86_FP_REG_MASK;

984

}

985

DCHECK_LT(reg, 8);

986

if (entry->opcode == kX86PcRelLoadRA) {

987

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

988

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

989

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

990

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

991

uint8_t modrm = (2 << 6) | (reg << 3) | rX86_SP;

992

code_buffer_.push_back(modrm);

993

DCHECK_LT(scale, 4);

994

DCHECK_LT(index, 8);

995

DCHECK_LT(base_or_table, 8);

996

uint8_t base = static_cast<uint8_t>(base_or_table);

997

uint8_t sib = (scale << 6) | (index << 3) | base;

998

code_buffer_.push_back(sib);

999

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1000

} else {

1001

code_buffer_.push_back(entry->skeleton.opcode + reg);

1002

}

1003

code_buffer_.push_back(disp & 0xFF);

1004

code_buffer_.push_back((disp >> 8) & 0xFF);

1005

code_buffer_.push_back((disp >> 16) & 0xFF);

1006

code_buffer_.push_back((disp >> 24) & 0xFF);

1007

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1008

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1009

}

1010

1011

void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset) {

1012

DCHECK(entry->opcode == kX86StartOfMethod) << entry->name;

1013

code_buffer_.push_back(0xE8); // call +0

1014

code_buffer_.push_back(0);

1015

code_buffer_.push_back(0);

1016

code_buffer_.push_back(0);

1017

code_buffer_.push_back(0);

1018

1019

DCHECK_LT(reg, 8);

1020

code_buffer_.push_back(0x58 + reg); // pop reg

1021

1022

EmitRegImm(&X86Mir2Lir::EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */);

1023

}

1024

1025

void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) {

1026

UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " "

1027

<< BuildInsnString(entry->fmt, lir, 0);

1028

for (int i = 0; i < GetInsnSize(lir); ++i) {

1029

code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3

}

}

/*

* Assemble the LIR into binary instruction format. Note that we may

1035

* discover that pc-relative displacements may not fit the selected

1036

* instruction. In those cases we will try to substitute a new code

1037

* sequence or request that the trace be shortened and retried.

1038

*/

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1039

AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1040

LIR *lir;

1041

AssemblerStatus res = kSuccess; // Assume success

1042

1043

const bool kVerbosePcFixup = false;

1044

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1045

if (IsPseudoLirOp(lir->opcode)) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

continue;

}

if (lir->flags.is_nop) {

continue;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1053

if (lir->flags.fixup != kFixupNone) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1054

switch (lir->opcode) {

1055

case kX86Jcc8: {

1056

LIR *target_lir = lir->target;

1057

DCHECK(target_lir != NULL);

1058

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1059

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1060

if (IS_SIMM8(lir->operands[0])) {

1061

pc = lir->offset + 2 /* opcode + rel8 */;

1062

} else {

1063

pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1064

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1065

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1066

delta = target - pc;

1067

if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1068

if (kVerbosePcFixup) {

1069

LOG(INFO) << "Retry for JCC growth at " << lir->offset

1070

<< " delta: " << delta << " old delta: " << lir->operands[0];

1071

}

1072

lir->opcode = kX86Jcc32;

1073

SetupResourceMasks(lir);

1074

res = kRetryAll;

1075

}

1076

if (kVerbosePcFixup) {

1077

LOG(INFO) << "Source:";

1078

DumpLIRInsn(lir, 0);

1079

LOG(INFO) << "Target:";

1080

DumpLIRInsn(target_lir, 0);

1081

LOG(INFO) << "Delta " << delta;

1082

}

1083

lir->operands[0] = delta;

break;

}

case kX86Jcc32: {

LIR *target_lir = lir->target;

1088

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1089

CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1090

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1091

int delta = target - pc;

1092

if (kVerbosePcFixup) {

1093

LOG(INFO) << "Source:";

1094

DumpLIRInsn(lir, 0);

1095

LOG(INFO) << "Target:";

1096

DumpLIRInsn(target_lir, 0);

1097

LOG(INFO) << "Delta " << delta;

1098

}

1099

lir->operands[0] = delta;

break;

}

case kX86Jmp8: {

LIR *target_lir = lir->target;

1104

DCHECK(target_lir != NULL);

1105

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1106

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1107

if (IS_SIMM8(lir->operands[0])) {

1108

pc = lir->offset + 2 /* opcode + rel8 */;

1109

} else {

1110

pc = lir->offset + 5 /* opcode + rel32 */;

1111

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1112

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1113

delta = target - pc;

1114

if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) {

1115

// Useless branch

buzbee

252254b

2013-09-08 16:20:53 -0700

[diff] [blame]

1116

NopLIR(lir);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1117

if (kVerbosePcFixup) {

1118

LOG(INFO) << "Retry for useless branch at " << lir->offset;

1119

}

1120

res = kRetryAll;

1121

} else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1122

if (kVerbosePcFixup) {

1123

LOG(INFO) << "Retry for JMP growth at " << lir->offset;

1124

}

1125

lir->opcode = kX86Jmp32;

1126

SetupResourceMasks(lir);

1127

res = kRetryAll;

1128

}

1129

lir->operands[0] = delta;

break;

}

case kX86Jmp32: {

LIR *target_lir = lir->target;

1134

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1135

CodeOffset pc = lir->offset + 5 /* opcode + rel32 */;

1136

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1137

int delta = target - pc;

1138

lir->operands[0] = delta;

break;

}

default:

break;

}

}

/*

* If one of the pc-relative instructions expanded we'll have

1148

* to make another pass. Don't bother to fully assemble the

1149

* instruction.

1150

*/

1151

if (res != kSuccess) {

1152

continue;

1153

}

1154

CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size());

1155

const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode];

1156

size_t starting_cbuf_size = code_buffer_.size();

1157

switch (entry->kind) {

1158

case kData: // 4 bytes of data

1159

code_buffer_.push_back(lir->operands[0]);

1160

break;

1161

case kNullary: // 1 byte of opcode

1162

DCHECK_EQ(0, entry->skeleton.prefix1);

1163

DCHECK_EQ(0, entry->skeleton.prefix2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1164

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1165

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1166

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1167

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1168

break;

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

1169

case kRegOpcode: // lir operands - 0: reg

1170

EmitOpRegOpcode(entry, lir->operands[0]);

1171

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1172

case kReg: // lir operands - 0: reg

1173

EmitOpReg(entry, lir->operands[0]);

1174

break;

1175

case kMem: // lir operands - 0: base, 1: disp

1176

EmitOpMem(entry, lir->operands[0], lir->operands[1]);

1177

break;

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1178

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

1179

EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]);

1180

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1181

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

1182

EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1183

break;

Mark Mendell

343adb5

2013-12-18 06:02:17 -0800

[diff] [blame]

1184

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

1185

EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1186

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1187

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

1188

EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1189

lir->operands[3], lir->operands[4]);

1190

break;

1191

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

1192

EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1193

break;

1194

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

1195

EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1196

lir->operands[3], lir->operands[4]);

1197

break;

1198

case kRegThread: // lir operands - 0: reg, 1: disp

1199

EmitRegThread(entry, lir->operands[0], lir->operands[1]);

1200

break;

1201

case kRegReg: // lir operands - 0: reg1, 1: reg2

1202

EmitRegReg(entry, lir->operands[0], lir->operands[1]);

1203

break;

1204

case kRegRegStore: // lir operands - 0: reg2, 1: reg1

1205

EmitRegReg(entry, lir->operands[1], lir->operands[0]);

1206

break;

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame^]

1207

case kRegRegImmRev:

1208

EmitRegRegImmRev(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1209

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1210

case kRegRegImm:

1211

EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1212

break;

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame^]

1213

case kRegMemImm:

1214

EmitRegMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1215

lir->operands[3]);

1216

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1217

case kRegImm: // lir operands - 0: reg, 1: immediate

1218

EmitRegImm(entry, lir->operands[0], lir->operands[1]);

1219

break;

1220

case kThreadImm: // lir operands - 0: disp, 1: immediate

1221

EmitThreadImm(entry, lir->operands[0], lir->operands[1]);

1222

break;

1223

case kMovRegImm: // lir operands - 0: reg, 1: immediate

1224

EmitMovRegImm(entry, lir->operands[0], lir->operands[1]);

1225

break;

1226

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

1227

EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]);

1228

break;

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

1229

case kShiftRegCl: // lir operands - 0: reg, 1: cl

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1230

EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]);

1231

break;

1232

case kRegCond: // lir operands - 0: reg, 1: condition

1233

EmitRegCond(entry, lir->operands[0], lir->operands[1]);

1234

break;

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

1235

case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: condition

1236

EmitRegRegCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1237

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1238

case kJmp: // lir operands - 0: rel

1239

EmitJmp(entry, lir->operands[0]);

1240

break;

1241

case kJcc: // lir operands - 0: rel, 1: CC, target assigned

1242

EmitJcc(entry, lir->operands[0], lir->operands[1]);

1243

break;

1244

case kCall:

1245

switch (entry->opcode) {

1246

case kX86CallM: // lir operands - 0: base, 1: disp

1247

EmitCallMem(entry, lir->operands[0], lir->operands[1]);

1248

break;

1249

case kX86CallT: // lir operands - 0: disp

1250

EmitCallThread(entry, lir->operands[0]);

1251

break;

1252

default:

1253

EmitUnimplemented(entry, lir);

break;

}

break;

case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

1258

EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1259

lir->operands[3], lir->operands[4]);

1260

break;

1261

case kMacro:

1262

EmitMacro(entry, lir->operands[0], lir->offset);

1263

break;

1264

default:

1265

EmitUnimplemented(entry, lir);

1266

break;

1267

}

1268

CHECK_EQ(static_cast<size_t>(GetInsnSize(lir)),

1269

code_buffer_.size() - starting_cbuf_size)

1270

<< "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name;

}

return res;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1275

// LIR offset assignment.

1276

// TODO: consolidate w/ Arm assembly mechanism.

1277

int X86Mir2Lir::AssignInsnOffsets() {

LIR* lir;

int offset = 0;

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

1282

lir->offset = offset;

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1283

if (LIKELY(!IsPseudoLirOp(lir->opcode))) {

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1284

if (!lir->flags.is_nop) {

1285

offset += lir->flags.size;

1286

}

1287

} else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) {

1288

if (offset & 0x2) {

1289

offset += 2;

1290

lir->operands[0] = 1;

1291

} else {

1292

lir->operands[0] = 0;

1293

}

1294

}

1295

/* Pseudo opcodes don't consume space */

}

return offset;

}

/*

* Walk the compilation unit and assign offsets to instructions

1302

* and literals and compute the total size of the compiled unit.

1303

* TODO: consolidate w/ Arm assembly mechanism.

1304

*/

1305

void X86Mir2Lir::AssignOffsets() {

1306

int offset = AssignInsnOffsets();

1307

1308

/* Const values have to be word aligned */

1309

offset = (offset + 3) & ~3;

1310

1311

/* Set up offsets for literals */

1312

data_offset_ = offset;

1313

1314

offset = AssignLiteralOffset(offset);

1315

1316

offset = AssignSwitchTablesOffset(offset);

1317

1318

offset = AssignFillArrayDataOffset(offset);

1319

1320

total_size_ = offset;

}

/*

* Go over each instruction in the list and calculate the offset from the top

1325

* before sending them off to the assembler. If out-of-range branch distance is

1326

* seen rearrange the instructions a bit to correct it.

1327

* TODO: consolidate w/ Arm assembly mechanism.

1328

*/

1329

void X86Mir2Lir::AssembleLIR() {

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1330

cu_->NewTimingSplit("Assemble");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1331

AssignOffsets();

1332

int assembler_retries = 0;

1333

/*

1334

* Assemble here. Note that we generate code with optimistic assumptions

1335

* and if found now to work, we'll have to redo the sequence and retry.

*/

while (true) {

AssemblerStatus res = AssembleInstructions(0);

1340

if (res == kSuccess) {

break;

} else {

assembler_retries++;

if (assembler_retries > MAX_ASSEMBLER_RETRIES) {

1345

CodegenDump();

1346

LOG(FATAL) << "Assembler error - too many retries";

1347

}

1348

// Redo offsets and try again

1349

AssignOffsets();

1350

code_buffer_.clear();

}

}

// Install literals

InstallLiteralPools();

1356

1357

// Install switch tables

1358

InstallSwitchTables();

1359

1360

// Install fill array data

1361

InstallFillArrayData();

1362

1363

// Create the mapping table and native offset to reference map.

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1364

cu_->NewTimingSplit("PcMappingTable");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1365

CreateMappingTables();

1366

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1367

cu_->NewTimingSplit("GcMap");

buzbee