Blame - compiler/dex/quick/x86/assemble_x86.cc - platform_art

2013-07-12 13:46:57 -0700

[diff] [blame]

251

#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \

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{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

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{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

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EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),

257

{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

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{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),

261

{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

262

{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

263

264

EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),

266

EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),

267

EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),

269

EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES),

272

EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0),

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EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0),

278

EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0),

279

EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0),

280

EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),

281

EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0),

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{ kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" },

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{ kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" },

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EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),

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{ kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" },

292

{ kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" },

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{ kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },

294

295

{ kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

296

{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

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{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

298

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// TODO: load/store?

300

// Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.

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{ kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },

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EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES),

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EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES),

305

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{ kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" },

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{ kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" },

308

{ kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

309

{ kX86LockCmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "!0r,!1r" },

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{ kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" },

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{ kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

312

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EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),

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EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),

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EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),

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EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),

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#undef EXT_0F_ENCODING_MAP

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{ kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },

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{ kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },

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{ kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },

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{ kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },

323

{ kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" },

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{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

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{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

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{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

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{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

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b1eba21

2013-07-17 18:07:19 -0700

[diff] [blame]

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{ kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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{ kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" },

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{ kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },

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{ kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" },

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};

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static size_t ComputeSize(const X86EncodingMap* entry, int base, int displacement, bool has_sib) {

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size_t size = 0;

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if (entry->skeleton.prefix1 > 0) {

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++size;

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if (entry->skeleton.prefix2 > 0) {

++size;

}

}

++size; // opcode

if (entry->skeleton.opcode == 0x0F) {

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++size;

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if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

if (has_sib || base == rX86_SP) {

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// SP requires a SIB byte.

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++size;

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}

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if (displacement != 0 || base == rBP) {

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// BP requires an explicit displacement, even when it's 0.

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if (entry->opcode != kX86Lea32RA) {

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DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name;

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}

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size += IS_SIMM8(displacement) ? 1 : 4;

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}

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size += entry->skeleton.immediate_bytes;

return size;

}

int X86Mir2Lir::GetInsnSize(LIR* lir) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

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DCHECK(!IsPseudoLirOp(lir->opcode));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode];

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switch (entry->kind) {

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case kData:

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return 4; // 4 bytes of data

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case kNop:

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return lir->operands[0]; // length of nop is sole operand

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case kNullary:

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return 1; // 1 byte of opcode

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

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case kRegOpcode: // lir operands - 0: reg

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return ComputeSize(entry, 0, 0, false) - 1; // substract 1 for modrm

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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case kReg: // lir operands - 0: reg

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return ComputeSize(entry, 0, 0, false);

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case kMem: // lir operands - 0: base, 1: disp

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return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

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case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

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return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

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case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

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return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

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case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

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return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

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case kThreadReg: // lir operands - 0: disp, 1: reg

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return ComputeSize(entry, 0, lir->operands[0], false);

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case kRegReg:

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return ComputeSize(entry, 0, 0, false);

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case kRegRegStore:

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return ComputeSize(entry, 0, 0, false);

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case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

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return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

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case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

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return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

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case kRegThread: // lir operands - 0: reg, 1: disp

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return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

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case kRegImm: { // lir operands - 0: reg, 1: immediate

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size_t size = ComputeSize(entry, 0, 0, false);

402

if (entry->skeleton.ax_opcode == 0) {

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return size;

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} else {

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// AX opcodes don't require the modrm byte.

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int reg = lir->operands[0];

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return size - (reg == rAX ? 1 : 0);

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}

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}

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case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

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return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

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case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

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return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

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case kThreadImm: // lir operands - 0: disp, 1: imm

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return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

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case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

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return ComputeSize(entry, 0, 0, false);

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case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

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return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

420

case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

421

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

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case kMovRegImm: // lir operands - 0: reg, 1: immediate

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return 1 + entry->skeleton.immediate_bytes;

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case kShiftRegImm: // lir operands - 0: reg, 1: immediate

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// Shift by immediate one has a shorter opcode.

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return ComputeSize(entry, 0, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

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case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

428

// Shift by immediate one has a shorter opcode.

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return ComputeSize(entry, lir->operands[0], lir->operands[1], false) -

430

(lir->operands[2] == 1 ? 1 : 0);

431

case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

432

// Shift by immediate one has a shorter opcode.

433

return ComputeSize(entry, lir->operands[0], lir->operands[3], true) -

434

(lir->operands[4] == 1 ? 1 : 0);

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case kShiftRegCl:

436

return ComputeSize(entry, 0, 0, false);

437

case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

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return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

439

case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

440

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

441

case kRegCond: // lir operands - 0: reg, 1: cond

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return ComputeSize(entry, 0, 0, false);

443

case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

444

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

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case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

446

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

447

case kJcc:

448

if (lir->opcode == kX86Jcc8) {

449

return 2; // opcode + rel8

450

} else {

451

DCHECK(lir->opcode == kX86Jcc32);

452

return 6; // 2 byte opcode + rel32

453

}

454

case kJmp:

455

if (lir->opcode == kX86Jmp8) {

456

return 2; // opcode + rel8

457

} else if (lir->opcode == kX86Jmp32) {

458

return 5; // opcode + rel32

459

} else {

460

DCHECK(lir->opcode == kX86JmpR);

461

return 2; // opcode + modrm

462

}

463

case kCall:

464

switch (lir->opcode) {

465

case kX86CallR: return 2; // opcode modrm

466

case kX86CallM: // lir operands - 0: base, 1: disp

467

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

468

case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

469

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

470

case kX86CallT: // lir operands - 0: disp

471

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

default:

break;

}

break;

case kPcRel:

if (entry->opcode == kX86PcRelLoadRA) {

478

// lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

479

return ComputeSize(entry, lir->operands[1], 0x12345678, true);

480

} else {

481

DCHECK(entry->opcode == kX86PcRelAdr);

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

482

return 5; // opcode with reg + 4 byte immediate

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

483

}

484

case kMacro:

485

DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));

486

return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +

487

ComputeSize(&X86Mir2Lir::EncodingMap[kX86Sub32RI], 0, 0, false) -

488

(lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

return 0;

}

static uint8_t ModrmForDisp(int base, int disp) {

497

// BP requires an explicit disp, so do not omit it in the 0 case

498

if (disp == 0 && base != rBP) {

499

return 0;

500

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

void X86Mir2Lir::EmitDisp(int base, int disp) {

508

// BP requires an explicit disp, so do not omit it in the 0 case

509

if (disp == 0 && base != rBP) {

510

return;

511

} else if (IS_SIMM8(disp)) {

512

code_buffer_.push_back(disp & 0xFF);

513

} else {

514

code_buffer_.push_back(disp & 0xFF);

515

code_buffer_.push_back((disp >> 8) & 0xFF);

516

code_buffer_.push_back((disp >> 16) & 0xFF);

517

code_buffer_.push_back((disp >> 24) & 0xFF);

}

}

Vladimir Marko

2013-10-24 15:08:57 +0100

[diff] [blame]

521

void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg) {

522

if (entry->skeleton.prefix1 != 0) {

523

code_buffer_.push_back(entry->skeleton.prefix1);

524

if (entry->skeleton.prefix2 != 0) {

525

code_buffer_.push_back(entry->skeleton.prefix2);

526

}

527

} else {

528

DCHECK_EQ(0, entry->skeleton.prefix2);

529

}

530

code_buffer_.push_back(entry->skeleton.opcode);

531

if (entry->skeleton.opcode == 0x0F) {

532

code_buffer_.push_back(entry->skeleton.extra_opcode1);

533

// There's no 3-byte instruction with +rd

534

DCHECK_NE(0x38, entry->skeleton.extra_opcode1);

535

DCHECK_NE(0x3A, entry->skeleton.extra_opcode1);

536

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

537

} else {

538

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

539

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

540

}

541

DCHECK(!X86_FPREG(reg));

542

DCHECK_LT(reg, 8);

543

code_buffer_.back() += reg;

544

DCHECK_EQ(0, entry->skeleton.ax_opcode);

545

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

546

}

547

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

548

void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) {

549

if (entry->skeleton.prefix1 != 0) {

550

code_buffer_.push_back(entry->skeleton.prefix1);

551

if (entry->skeleton.prefix2 != 0) {

552

code_buffer_.push_back(entry->skeleton.prefix2);

553

}

554

} else {

555

DCHECK_EQ(0, entry->skeleton.prefix2);

556

}

557

code_buffer_.push_back(entry->skeleton.opcode);

558

if (entry->skeleton.opcode == 0x0F) {

559

code_buffer_.push_back(entry->skeleton.extra_opcode1);

Vladimir Marko

2013-10-24 14:52:37 +0100

[diff] [blame]

560

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

561

code_buffer_.push_back(entry->skeleton.extra_opcode2);

562

} else {

563

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

564

}

565

} else {

566

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

567

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

568

}

569

if (X86_FPREG(reg)) {

570

reg = reg & X86_FP_REG_MASK;

571

}

572

if (reg >= 4) {

573

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

574

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

575

}

576

DCHECK_LT(reg, 8);

577

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

578

code_buffer_.push_back(modrm);

579

DCHECK_EQ(0, entry->skeleton.ax_opcode);

580

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

581

}

582

583

void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) {

584

if (entry->skeleton.prefix1 != 0) {

585

code_buffer_.push_back(entry->skeleton.prefix1);

586

if (entry->skeleton.prefix2 != 0) {

587

code_buffer_.push_back(entry->skeleton.prefix2);

588

}

589

} else {

590

DCHECK_EQ(0, entry->skeleton.prefix2);

591

}

592

code_buffer_.push_back(entry->skeleton.opcode);

593

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

594

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

595

DCHECK_LT(entry->skeleton.modrm_opcode, 8);

596

DCHECK_LT(base, 8);

597

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;

598

code_buffer_.push_back(modrm);

599

EmitDisp(base, disp);

600

DCHECK_EQ(0, entry->skeleton.ax_opcode);

601

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

602

}

603

604

void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry,

605

uint8_t base, int disp, uint8_t reg) {

606

if (entry->skeleton.prefix1 != 0) {

607

code_buffer_.push_back(entry->skeleton.prefix1);

608

if (entry->skeleton.prefix2 != 0) {

609

code_buffer_.push_back(entry->skeleton.prefix2);

610

}

611

} else {

612

DCHECK_EQ(0, entry->skeleton.prefix2);

613

}

614

code_buffer_.push_back(entry->skeleton.opcode);

615

if (entry->skeleton.opcode == 0x0F) {

616

code_buffer_.push_back(entry->skeleton.extra_opcode1);

Vladimir Marko

2013-10-24 14:52:37 +0100

[diff] [blame]

617

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

618

code_buffer_.push_back(entry->skeleton.extra_opcode2);

619

} else {

620

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

621

}

622

} else {

623

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

624

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

625

}

626

if (X86_FPREG(reg)) {

627

reg = reg & X86_FP_REG_MASK;

628

}

629

if (reg >= 4) {

Vladimir Marko

17088bb

2013-10-28 13:55:34 +0000

[diff] [blame]

630

DCHECK(strchr(entry->name, '8') == NULL ||

631

entry->opcode == kX86Movzx8RM || entry->opcode == kX86Movsx8RM)

632

<< entry->name << " " << static_cast<int>(reg)

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

633

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

}

DCHECK_LT(reg, 8);

DCHECK_LT(base, 8);

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg << 3) | base;

638

code_buffer_.push_back(modrm);

639

if (base == rX86_SP) {

640

// Special SIB for SP base

641

code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);

642

}

643

EmitDisp(base, disp);

644

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

645

DCHECK_EQ(0, entry->skeleton.ax_opcode);

646

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

647

}

648

649

void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry,

650

uint8_t reg, uint8_t base, int disp) {

651

// Opcode will flip operands.

652

EmitMemReg(entry, base, disp, reg);

653

}

654

655

void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index,

656

int scale, int disp) {

657

if (entry->skeleton.prefix1 != 0) {

658

code_buffer_.push_back(entry->skeleton.prefix1);

659

if (entry->skeleton.prefix2 != 0) {

660

code_buffer_.push_back(entry->skeleton.prefix2);

661

}

662

} else {

663

DCHECK_EQ(0, entry->skeleton.prefix2);

664

}

665

code_buffer_.push_back(entry->skeleton.opcode);

666

if (entry->skeleton.opcode == 0x0F) {

667

code_buffer_.push_back(entry->skeleton.extra_opcode1);

Vladimir Marko

2013-10-24 14:52:37 +0100

[diff] [blame]

668

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

669

code_buffer_.push_back(entry->skeleton.extra_opcode2);

670

} else {

671

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

672

}

673

} else {

674

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

675

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

676

}

677

if (X86_FPREG(reg)) {

678

reg = reg & X86_FP_REG_MASK;

679

}

680

DCHECK_LT(reg, 8);

681

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg << 3) | rX86_SP;

682

code_buffer_.push_back(modrm);

DCHECK_LT(scale, 4);

DCHECK_LT(index, 8);

DCHECK_LT(base, 8);

uint8_t sib = (scale << 6) | (index << 3) | base;

687

code_buffer_.push_back(sib);

688

EmitDisp(base, disp);

689

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

690

DCHECK_EQ(0, entry->skeleton.ax_opcode);

691

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

692

}

693

694

void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp,

695

uint8_t reg) {

696

// Opcode will flip operands.

697

EmitRegArray(entry, reg, base, index, scale, disp);

698

}

699

700

void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) {

701

DCHECK_NE(entry->skeleton.prefix1, 0);

702

code_buffer_.push_back(entry->skeleton.prefix1);

703

if (entry->skeleton.prefix2 != 0) {

704

code_buffer_.push_back(entry->skeleton.prefix2);

705

}

706

code_buffer_.push_back(entry->skeleton.opcode);

707

if (entry->skeleton.opcode == 0x0F) {

708

code_buffer_.push_back(entry->skeleton.extra_opcode1);

Vladimir Marko

2013-10-24 14:52:37 +0100

[diff] [blame]

709

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

710

code_buffer_.push_back(entry->skeleton.extra_opcode2);

711

} else {

712

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

713

}

714

} else {

715

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

716

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

717

}

718

if (X86_FPREG(reg)) {

719

reg = reg & X86_FP_REG_MASK;

720

}

721

if (reg >= 4) {

722

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

723

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

724

}

725

DCHECK_LT(reg, 8);

726

uint8_t modrm = (0 << 6) | (reg << 3) | rBP;

727

code_buffer_.push_back(modrm);

728

code_buffer_.push_back(disp & 0xFF);

729

code_buffer_.push_back((disp >> 8) & 0xFF);

730

code_buffer_.push_back((disp >> 16) & 0xFF);

731

code_buffer_.push_back((disp >> 24) & 0xFF);

732

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

733

DCHECK_EQ(0, entry->skeleton.ax_opcode);

734

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

735

}

736

737

void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) {

738

if (entry->skeleton.prefix1 != 0) {

739

code_buffer_.push_back(entry->skeleton.prefix1);

740

if (entry->skeleton.prefix2 != 0) {

741

code_buffer_.push_back(entry->skeleton.prefix2);

742

}

743

} else {

744

DCHECK_EQ(0, entry->skeleton.prefix2);

745

}

746

code_buffer_.push_back(entry->skeleton.opcode);

747

if (entry->skeleton.opcode == 0x0F) {

748

code_buffer_.push_back(entry->skeleton.extra_opcode1);

Vladimir Marko

2013-10-24 14:52:37 +0100

[diff] [blame]

749

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

750

code_buffer_.push_back(entry->skeleton.extra_opcode2);

751

} else {

752

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

753

}

754

} else {

755

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

756

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

757

}

758

if (X86_FPREG(reg1)) {

759

reg1 = reg1 & X86_FP_REG_MASK;

760

}

761

if (X86_FPREG(reg2)) {

762

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

767

code_buffer_.push_back(modrm);

768

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

769

DCHECK_EQ(0, entry->skeleton.ax_opcode);

770

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

771

}

772

773

void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry,

774

uint8_t reg1, uint8_t reg2, int32_t imm) {

775

if (entry->skeleton.prefix1 != 0) {

776

code_buffer_.push_back(entry->skeleton.prefix1);

777

if (entry->skeleton.prefix2 != 0) {

778

code_buffer_.push_back(entry->skeleton.prefix2);

779

}

780

} else {

781

DCHECK_EQ(0, entry->skeleton.prefix2);

782

}

783

code_buffer_.push_back(entry->skeleton.opcode);

784

if (entry->skeleton.opcode == 0x0F) {

785

code_buffer_.push_back(entry->skeleton.extra_opcode1);

Vladimir Marko

2013-10-24 14:52:37 +0100

[diff] [blame]

786

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

787

code_buffer_.push_back(entry->skeleton.extra_opcode2);

788

} else {

789

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

790

}

791

} else {

792

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

793

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

794

}

795

if (X86_FPREG(reg1)) {

796

reg1 = reg1 & X86_FP_REG_MASK;

797

}

798

if (X86_FPREG(reg2)) {

799

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

804

code_buffer_.push_back(modrm);

805

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

806

DCHECK_EQ(0, entry->skeleton.ax_opcode);

807

switch (entry->skeleton.immediate_bytes) {

808

case 1:

809

DCHECK(IS_SIMM8(imm));

810

code_buffer_.push_back(imm & 0xFF);

811

break;

812

case 2:

813

DCHECK(IS_SIMM16(imm));

814

code_buffer_.push_back(imm & 0xFF);

815

code_buffer_.push_back((imm >> 8) & 0xFF);

816

break;

817

case 4:

818

code_buffer_.push_back(imm & 0xFF);

819

code_buffer_.push_back((imm >> 8) & 0xFF);

820

code_buffer_.push_back((imm >> 16) & 0xFF);

821

code_buffer_.push_back((imm >> 24) & 0xFF);

822

break;

823

default:

824

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

825

<< ") for instruction: " << entry->name;

break;

}

}

void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

831

if (entry->skeleton.prefix1 != 0) {

832

code_buffer_.push_back(entry->skeleton.prefix1);

833

if (entry->skeleton.prefix2 != 0) {

834

code_buffer_.push_back(entry->skeleton.prefix2);

835

}

836

} else {

837

DCHECK_EQ(0, entry->skeleton.prefix2);

838

}

839

if (reg == rAX && entry->skeleton.ax_opcode != 0) {

840

code_buffer_.push_back(entry->skeleton.ax_opcode);

841

} else {

842

code_buffer_.push_back(entry->skeleton.opcode);

843

if (entry->skeleton.opcode == 0x0F) {

844

code_buffer_.push_back(entry->skeleton.extra_opcode1);

Vladimir Marko

2013-10-24 14:52:37 +0100

[diff] [blame]

845

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

846

code_buffer_.push_back(entry->skeleton.extra_opcode2);

847

} else {

848

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

849

}

850

} else {

851

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

852

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

853

}

854

if (X86_FPREG(reg)) {

855

reg = reg & X86_FP_REG_MASK;

856

}

857

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

858

code_buffer_.push_back(modrm);

859

}

860

switch (entry->skeleton.immediate_bytes) {

861

case 1:

862

DCHECK(IS_SIMM8(imm));

863

code_buffer_.push_back(imm & 0xFF);

864

break;

865

case 2:

866

DCHECK(IS_SIMM16(imm));

867

code_buffer_.push_back(imm & 0xFF);

868

code_buffer_.push_back((imm >> 8) & 0xFF);

869

break;

870

case 4:

871

code_buffer_.push_back(imm & 0xFF);

872

code_buffer_.push_back((imm >> 8) & 0xFF);

873

code_buffer_.push_back((imm >> 16) & 0xFF);

874

code_buffer_.push_back((imm >> 24) & 0xFF);

875

break;

876

default:

877

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

878

<< ") for instruction: " << entry->name;

break;

}

}

void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) {

884

if (entry->skeleton.prefix1 != 0) {

885

code_buffer_.push_back(entry->skeleton.prefix1);

886

if (entry->skeleton.prefix2 != 0) {

887

code_buffer_.push_back(entry->skeleton.prefix2);

888

}

889

} else {

890

DCHECK_EQ(0, entry->skeleton.prefix2);

891

}

892

code_buffer_.push_back(entry->skeleton.opcode);

893

if (entry->skeleton.opcode == 0x0F) {

894

code_buffer_.push_back(entry->skeleton.extra_opcode1);

Vladimir Marko

2013-10-24 14:52:37 +0100

[diff] [blame]

895

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

896

code_buffer_.push_back(entry->skeleton.extra_opcode2);

897

} else {

898

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

899

}

900

} else {

901

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

902

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

903

}

904

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

905

code_buffer_.push_back(modrm);

906

code_buffer_.push_back(disp & 0xFF);

907

code_buffer_.push_back((disp >> 8) & 0xFF);

908

code_buffer_.push_back((disp >> 16) & 0xFF);

909

code_buffer_.push_back((disp >> 24) & 0xFF);

910

switch (entry->skeleton.immediate_bytes) {

911

case 1:

912

DCHECK(IS_SIMM8(imm));

913

code_buffer_.push_back(imm & 0xFF);

914

break;

915

case 2:

916

DCHECK(IS_SIMM16(imm));

917

code_buffer_.push_back(imm & 0xFF);

918

code_buffer_.push_back((imm >> 8) & 0xFF);

919

break;

920

case 4:

921

code_buffer_.push_back(imm & 0xFF);

922

code_buffer_.push_back((imm >> 8) & 0xFF);

923

code_buffer_.push_back((imm >> 16) & 0xFF);

924

code_buffer_.push_back((imm >> 24) & 0xFF);

925

break;

926

default:

927

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

928

<< ") for instruction: " << entry->name;

929

break;

930

}

931

DCHECK_EQ(entry->skeleton.ax_opcode, 0);

932

}

933

934

void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

935

DCHECK_LT(reg, 8);

936

code_buffer_.push_back(0xB8 + reg);

937

code_buffer_.push_back(imm & 0xFF);

938

code_buffer_.push_back((imm >> 8) & 0xFF);

939

code_buffer_.push_back((imm >> 16) & 0xFF);

940

code_buffer_.push_back((imm >> 24) & 0xFF);

941

}

942

943

void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

944

if (entry->skeleton.prefix1 != 0) {

945

code_buffer_.push_back(entry->skeleton.prefix1);

946

if (entry->skeleton.prefix2 != 0) {

947

code_buffer_.push_back(entry->skeleton.prefix2);

948

}

949

} else {

950

DCHECK_EQ(0, entry->skeleton.prefix2);

951

}

952

if (imm != 1) {

953

code_buffer_.push_back(entry->skeleton.opcode);

954

} else {

955

// Shorter encoding for 1 bit shift

956

code_buffer_.push_back(entry->skeleton.ax_opcode);

957

}

958

if (entry->skeleton.opcode == 0x0F) {

959

code_buffer_.push_back(entry->skeleton.extra_opcode1);

Vladimir Marko

2013-10-24 14:52:37 +0100

[diff] [blame]

960

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

961

code_buffer_.push_back(entry->skeleton.extra_opcode2);

962

} else {

963

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

964

}

965

} else {

966

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

967

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

968

}

969

if (reg >= 4) {

970

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

971

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

972

}

973

DCHECK_LT(reg, 8);

974

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

975

code_buffer_.push_back(modrm);

976

if (imm != 1) {

977

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

978

DCHECK(IS_SIMM8(imm));

979

code_buffer_.push_back(imm & 0xFF);

}

}

void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl) {

984

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

985

if (entry->skeleton.prefix1 != 0) {

986

code_buffer_.push_back(entry->skeleton.prefix1);

987

if (entry->skeleton.prefix2 != 0) {

988

code_buffer_.push_back(entry->skeleton.prefix2);

989

}

990

} else {

991

DCHECK_EQ(0, entry->skeleton.prefix2);

992

}

993

code_buffer_.push_back(entry->skeleton.opcode);

994

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

995

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

996

DCHECK_LT(reg, 8);

997

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

998

code_buffer_.push_back(modrm);

999

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1000

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1001

}

1002

1003

void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) {

1004

if (entry->skeleton.prefix1 != 0) {

1005

code_buffer_.push_back(entry->skeleton.prefix1);

1006

if (entry->skeleton.prefix2 != 0) {

1007

code_buffer_.push_back(entry->skeleton.prefix2);

1008

}

1009

} else {

1010

DCHECK_EQ(0, entry->skeleton.prefix2);

1011

}

1012

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1013

DCHECK_EQ(0x0F, entry->skeleton.opcode);

1014

code_buffer_.push_back(0x0F);

1015

DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);

1016

code_buffer_.push_back(0x90 | condition);

1017

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1018

DCHECK_LT(reg, 8);

1019

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

1020

code_buffer_.push_back(modrm);

1021

DCHECK_EQ(entry->skeleton.immediate_bytes, 0);

1022

}

1023

1024

void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int rel) {

1025

if (entry->opcode == kX86Jmp8) {

1026

DCHECK(IS_SIMM8(rel));

1027

code_buffer_.push_back(0xEB);

1028

code_buffer_.push_back(rel & 0xFF);

1029

} else if (entry->opcode == kX86Jmp32) {

1030

code_buffer_.push_back(0xE9);

1031

code_buffer_.push_back(rel & 0xFF);

1032

code_buffer_.push_back((rel >> 8) & 0xFF);

1033

code_buffer_.push_back((rel >> 16) & 0xFF);

1034

code_buffer_.push_back((rel >> 24) & 0xFF);

1035

} else {

1036

DCHECK(entry->opcode == kX86JmpR);

1037

code_buffer_.push_back(entry->skeleton.opcode);

1038

uint8_t reg = static_cast<uint8_t>(rel);

1039

DCHECK_LT(reg, 8);

1040

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

1041

code_buffer_.push_back(modrm);

}

}

void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc) {

1046

DCHECK_LT(cc, 16);

1047

if (entry->opcode == kX86Jcc8) {

1048

DCHECK(IS_SIMM8(rel));

1049

code_buffer_.push_back(0x70 | cc);

1050

code_buffer_.push_back(rel & 0xFF);

1051

} else {

1052

DCHECK(entry->opcode == kX86Jcc32);

1053

code_buffer_.push_back(0x0F);

1054

code_buffer_.push_back(0x80 | cc);

1055

code_buffer_.push_back(rel & 0xFF);

1056

code_buffer_.push_back((rel >> 8) & 0xFF);

1057

code_buffer_.push_back((rel >> 16) & 0xFF);

1058

code_buffer_.push_back((rel >> 24) & 0xFF);

}

}

void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) {

1063

if (entry->skeleton.prefix1 != 0) {

1064

code_buffer_.push_back(entry->skeleton.prefix1);

1065

if (entry->skeleton.prefix2 != 0) {

1066

code_buffer_.push_back(entry->skeleton.prefix2);

1067

}

1068

} else {

1069

DCHECK_EQ(0, entry->skeleton.prefix2);

1070

}

1071

code_buffer_.push_back(entry->skeleton.opcode);

1072

if (entry->skeleton.opcode == 0x0F) {

1073

code_buffer_.push_back(entry->skeleton.extra_opcode1);

Vladimir Marko

2013-10-24 14:52:37 +0100

[diff] [blame]

1074

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1075

code_buffer_.push_back(entry->skeleton.extra_opcode2);

1076

} else {

1077

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1078

}

1079

} else {

1080

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1081

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1082

}

1083

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;

1084

code_buffer_.push_back(modrm);

1085

if (base == rX86_SP) {

1086

// Special SIB for SP base

1087

code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);

1088

}

1089

EmitDisp(base, disp);

1090

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1091

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1092

}

1093

1094

void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int disp) {

1095

DCHECK_NE(entry->skeleton.prefix1, 0);

1096

code_buffer_.push_back(entry->skeleton.prefix1);

1097

if (entry->skeleton.prefix2 != 0) {

1098

code_buffer_.push_back(entry->skeleton.prefix2);

1099

}

1100

code_buffer_.push_back(entry->skeleton.opcode);

1101

if (entry->skeleton.opcode == 0x0F) {

1102

code_buffer_.push_back(entry->skeleton.extra_opcode1);

Vladimir Marko

2013-10-24 14:52:37 +0100

[diff] [blame]

1103

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1104

code_buffer_.push_back(entry->skeleton.extra_opcode2);

1105

} else {

1106

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1107

}

1108

} else {

1109

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1110

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1111

}

1112

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

1113

code_buffer_.push_back(modrm);

1114

code_buffer_.push_back(disp & 0xFF);

1115

code_buffer_.push_back((disp >> 8) & 0xFF);

1116

code_buffer_.push_back((disp >> 16) & 0xFF);

1117

code_buffer_.push_back((disp >> 24) & 0xFF);

1118

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1119

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1120

}

1121

1122

void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, uint8_t reg,

1123

int base_or_table, uint8_t index, int scale, int table_or_disp) {

1124

int disp;

1125

if (entry->opcode == kX86PcRelLoadRA) {

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1126

Mir2Lir::EmbeddedData *tab_rec =

1127

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1128

disp = tab_rec->offset;

1129

} else {

1130

DCHECK(entry->opcode == kX86PcRelAdr);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1131

Mir2Lir::EmbeddedData *tab_rec =

1132

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(base_or_table));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1133

disp = tab_rec->offset;

1134

}

1135

if (entry->skeleton.prefix1 != 0) {

1136

code_buffer_.push_back(entry->skeleton.prefix1);

1137

if (entry->skeleton.prefix2 != 0) {

1138

code_buffer_.push_back(entry->skeleton.prefix2);

1139

}

1140

} else {

1141

DCHECK_EQ(0, entry->skeleton.prefix2);

1142

}

1143

if (X86_FPREG(reg)) {

1144

reg = reg & X86_FP_REG_MASK;

1145

}

1146

DCHECK_LT(reg, 8);

1147

if (entry->opcode == kX86PcRelLoadRA) {

1148

code_buffer_.push_back(entry->skeleton.opcode);

1149

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1150

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1151

uint8_t modrm = (2 << 6) | (reg << 3) | rX86_SP;

1152

code_buffer_.push_back(modrm);

1153

DCHECK_LT(scale, 4);

1154

DCHECK_LT(index, 8);

1155

DCHECK_LT(base_or_table, 8);

1156

uint8_t base = static_cast<uint8_t>(base_or_table);

1157

uint8_t sib = (scale << 6) | (index << 3) | base;

1158

code_buffer_.push_back(sib);

1159

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1160

} else {

1161

code_buffer_.push_back(entry->skeleton.opcode + reg);

1162

}

1163

code_buffer_.push_back(disp & 0xFF);

1164

code_buffer_.push_back((disp >> 8) & 0xFF);

1165

code_buffer_.push_back((disp >> 16) & 0xFF);

1166

code_buffer_.push_back((disp >> 24) & 0xFF);

1167

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1168

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1169

}

1170

1171

void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset) {

1172

DCHECK(entry->opcode == kX86StartOfMethod) << entry->name;

1173

code_buffer_.push_back(0xE8); // call +0

1174

code_buffer_.push_back(0);

1175

code_buffer_.push_back(0);

1176

code_buffer_.push_back(0);

1177

code_buffer_.push_back(0);

1178

1179

DCHECK_LT(reg, 8);

1180

code_buffer_.push_back(0x58 + reg); // pop reg

1181

1182

EmitRegImm(&X86Mir2Lir::EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */);

1183

}

1184

1185

void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) {

1186

UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " "

1187

<< BuildInsnString(entry->fmt, lir, 0);

1188

for (int i = 0; i < GetInsnSize(lir); ++i) {

1189

code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3

}

}

/*

* Assemble the LIR into binary instruction format. Note that we may

1195

* discover that pc-relative displacements may not fit the selected

1196

* instruction. In those cases we will try to substitute a new code

1197

* sequence or request that the trace be shortened and retried.

1198

*/

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1199

AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1200

LIR *lir;

1201

AssemblerStatus res = kSuccess; // Assume success

1202

1203

const bool kVerbosePcFixup = false;

1204

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1205

if (IsPseudoLirOp(lir->opcode)) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

continue;

}

if (lir->flags.is_nop) {

continue;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1213

if (lir->flags.fixup != kFixupNone) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1214

switch (lir->opcode) {

1215

case kX86Jcc8: {

1216

LIR *target_lir = lir->target;

1217

DCHECK(target_lir != NULL);

1218

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1219

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1220

if (IS_SIMM8(lir->operands[0])) {

1221

pc = lir->offset + 2 /* opcode + rel8 */;

1222

} else {

1223

pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1224

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1225

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1226

delta = target - pc;

1227

if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1228

if (kVerbosePcFixup) {

1229

LOG(INFO) << "Retry for JCC growth at " << lir->offset

1230

<< " delta: " << delta << " old delta: " << lir->operands[0];

1231

}

1232

lir->opcode = kX86Jcc32;

1233

SetupResourceMasks(lir);

1234

res = kRetryAll;

1235

}

1236

if (kVerbosePcFixup) {

1237

LOG(INFO) << "Source:";

1238

DumpLIRInsn(lir, 0);

1239

LOG(INFO) << "Target:";

1240

DumpLIRInsn(target_lir, 0);

1241

LOG(INFO) << "Delta " << delta;

1242

}

1243

lir->operands[0] = delta;

break;

}

case kX86Jcc32: {

LIR *target_lir = lir->target;

1248

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1249

CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1250

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1251

int delta = target - pc;

1252

if (kVerbosePcFixup) {

1253

LOG(INFO) << "Source:";

1254

DumpLIRInsn(lir, 0);

1255

LOG(INFO) << "Target:";

1256

DumpLIRInsn(target_lir, 0);

1257

LOG(INFO) << "Delta " << delta;

1258

}

1259

lir->operands[0] = delta;

break;

}

case kX86Jmp8: {

LIR *target_lir = lir->target;

1264

DCHECK(target_lir != NULL);

1265

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1266

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1267

if (IS_SIMM8(lir->operands[0])) {

1268

pc = lir->offset + 2 /* opcode + rel8 */;

1269

} else {

1270

pc = lir->offset + 5 /* opcode + rel32 */;

1271

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1272

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1273

delta = target - pc;

1274

if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) {

1275

// Useless branch

buzbee

252254b

2013-09-08 16:20:53 -0700

[diff] [blame]

1276

NopLIR(lir);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1277

if (kVerbosePcFixup) {

1278

LOG(INFO) << "Retry for useless branch at " << lir->offset;

1279

}

1280

res = kRetryAll;

1281

} else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1282

if (kVerbosePcFixup) {

1283

LOG(INFO) << "Retry for JMP growth at " << lir->offset;

1284

}

1285

lir->opcode = kX86Jmp32;

1286

SetupResourceMasks(lir);

1287

res = kRetryAll;

1288

}

1289

lir->operands[0] = delta;

break;

}

case kX86Jmp32: {

LIR *target_lir = lir->target;

1294

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1295

CodeOffset pc = lir->offset + 5 /* opcode + rel32 */;

1296

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1297

int delta = target - pc;

1298

lir->operands[0] = delta;

break;

}

default:

break;

}

}

/*

* If one of the pc-relative instructions expanded we'll have

1308

* to make another pass. Don't bother to fully assemble the

1309

* instruction.

1310

*/

1311

if (res != kSuccess) {

1312

continue;

1313

}

1314

CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size());

1315

const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode];

1316

size_t starting_cbuf_size = code_buffer_.size();

1317

switch (entry->kind) {

1318

case kData: // 4 bytes of data

1319

code_buffer_.push_back(lir->operands[0]);

1320

break;

1321

case kNullary: // 1 byte of opcode

1322

DCHECK_EQ(0, entry->skeleton.prefix1);

1323

DCHECK_EQ(0, entry->skeleton.prefix2);

1324

code_buffer_.push_back(entry->skeleton.opcode);

1325

if (entry->skeleton.extra_opcode1 != 0) {

1326

code_buffer_.push_back(entry->skeleton.extra_opcode1);

1327

if (entry->skeleton.extra_opcode2 != 0) {

1328

code_buffer_.push_back(entry->skeleton.extra_opcode2);

1329

}

1330

} else {

1331

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1332

}

1333

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1334

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1335

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1336

break;

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

1337

case kRegOpcode: // lir operands - 0: reg

1338

EmitOpRegOpcode(entry, lir->operands[0]);

1339

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1340

case kReg: // lir operands - 0: reg

1341

EmitOpReg(entry, lir->operands[0]);

1342

break;

1343

case kMem: // lir operands - 0: base, 1: disp

1344

EmitOpMem(entry, lir->operands[0], lir->operands[1]);

1345

break;

1346

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

1347

EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1348

break;

1349

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

1350

EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1351

lir->operands[3], lir->operands[4]);

1352

break;

1353

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

1354

EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1355

break;

1356

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

1357

EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1358

lir->operands[3], lir->operands[4]);

1359

break;

1360

case kRegThread: // lir operands - 0: reg, 1: disp

1361

EmitRegThread(entry, lir->operands[0], lir->operands[1]);

1362

break;

1363

case kRegReg: // lir operands - 0: reg1, 1: reg2

1364

EmitRegReg(entry, lir->operands[0], lir->operands[1]);

1365

break;

1366

case kRegRegStore: // lir operands - 0: reg2, 1: reg1

1367

EmitRegReg(entry, lir->operands[1], lir->operands[0]);

1368

break;

1369

case kRegRegImm:

1370

EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1371

break;

1372

case kRegImm: // lir operands - 0: reg, 1: immediate

1373

EmitRegImm(entry, lir->operands[0], lir->operands[1]);

1374

break;

1375

case kThreadImm: // lir operands - 0: disp, 1: immediate

1376

EmitThreadImm(entry, lir->operands[0], lir->operands[1]);

1377

break;

1378

case kMovRegImm: // lir operands - 0: reg, 1: immediate

1379

EmitMovRegImm(entry, lir->operands[0], lir->operands[1]);

1380

break;

1381

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

1382

EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]);

1383

break;

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

1384

case kShiftRegCl: // lir operands - 0: reg, 1: cl

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1385

EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]);

1386

break;

1387

case kRegCond: // lir operands - 0: reg, 1: condition

1388

EmitRegCond(entry, lir->operands[0], lir->operands[1]);

1389

break;

1390

case kJmp: // lir operands - 0: rel

1391

EmitJmp(entry, lir->operands[0]);

1392

break;

1393

case kJcc: // lir operands - 0: rel, 1: CC, target assigned

1394

EmitJcc(entry, lir->operands[0], lir->operands[1]);

1395

break;

1396

case kCall:

1397

switch (entry->opcode) {

1398

case kX86CallM: // lir operands - 0: base, 1: disp

1399

EmitCallMem(entry, lir->operands[0], lir->operands[1]);

1400

break;

1401

case kX86CallT: // lir operands - 0: disp

1402

EmitCallThread(entry, lir->operands[0]);

1403

break;

1404

default:

1405

EmitUnimplemented(entry, lir);

break;

}

break;

case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

1410

EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1411

lir->operands[3], lir->operands[4]);

1412

break;

1413

case kMacro:

1414

EmitMacro(entry, lir->operands[0], lir->offset);

1415

break;

1416

default:

1417

EmitUnimplemented(entry, lir);

1418

break;

1419

}

1420

CHECK_EQ(static_cast<size_t>(GetInsnSize(lir)),

1421

code_buffer_.size() - starting_cbuf_size)

1422

<< "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name;

}

return res;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1427

// LIR offset assignment.

1428

// TODO: consolidate w/ Arm assembly mechanism.

1429

int X86Mir2Lir::AssignInsnOffsets() {

LIR* lir;

int offset = 0;

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

1434

lir->offset = offset;

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1435

if (LIKELY(!IsPseudoLirOp(lir->opcode))) {

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1436

if (!lir->flags.is_nop) {

1437

offset += lir->flags.size;

1438

}

1439

} else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) {

1440

if (offset & 0x2) {

1441

offset += 2;

1442

lir->operands[0] = 1;

1443

} else {

1444

lir->operands[0] = 0;

1445

}

1446

}

1447

/* Pseudo opcodes don't consume space */

}

return offset;

}

/*

* Walk the compilation unit and assign offsets to instructions

1454

* and literals and compute the total size of the compiled unit.

1455

* TODO: consolidate w/ Arm assembly mechanism.

1456

*/

1457

void X86Mir2Lir::AssignOffsets() {

1458

int offset = AssignInsnOffsets();

1459

1460

/* Const values have to be word aligned */

1461

offset = (offset + 3) & ~3;

1462

1463

/* Set up offsets for literals */

1464

data_offset_ = offset;

1465

1466

offset = AssignLiteralOffset(offset);

1467

1468

offset = AssignSwitchTablesOffset(offset);

1469

1470

offset = AssignFillArrayDataOffset(offset);

1471

1472

total_size_ = offset;

}

/*

* Go over each instruction in the list and calculate the offset from the top

1477

* before sending them off to the assembler. If out-of-range branch distance is

1478

* seen rearrange the instructions a bit to correct it.

1479

* TODO: consolidate w/ Arm assembly mechanism.

1480

*/

1481

void X86Mir2Lir::AssembleLIR() {

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1482

cu_->NewTimingSplit("Assemble");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1483

AssignOffsets();

1484

int assembler_retries = 0;

1485

/*

1486

* Assemble here. Note that we generate code with optimistic assumptions

1487

* and if found now to work, we'll have to redo the sequence and retry.

*/

while (true) {

AssemblerStatus res = AssembleInstructions(0);

1492

if (res == kSuccess) {

break;

} else {

assembler_retries++;

if (assembler_retries > MAX_ASSEMBLER_RETRIES) {

1497

CodegenDump();

1498

LOG(FATAL) << "Assembler error - too many retries";

1499

}

1500

// Redo offsets and try again

1501

AssignOffsets();

1502

code_buffer_.clear();

}

}

buzbee

2013-08-23 14:27:06 -0700

[diff] [blame]

1506

cu_->NewTimingSplit("LiteralData");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1507

// Install literals

1508

InstallLiteralPools();

1509

1510

// Install switch tables

1511

InstallSwitchTables();

1512

1513

// Install fill array data

1514

InstallFillArrayData();

1515

1516

// Create the mapping table and native offset to reference map.

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1517

cu_->NewTimingSplit("PcMappingTable");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1518

CreateMappingTables();

1519

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1520

cu_->NewTimingSplit("GcMap");

buzbee