Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 1 | /* |
Arun Kumar K.R | 6c85f05 | 2014-01-21 21:47:41 -0800 | [diff] [blame] | 2 | * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved. |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 3 | |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are |
| 6 | * met: |
| 7 | * * Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * * Redistributions in binary form must reproduce the above |
| 10 | * copyright notice, this list of conditions and the following |
| 11 | * disclaimer in the documentation and/or other materials provided |
| 12 | * with the distribution. |
Duy Truong | 73d36df | 2013-02-09 20:33:23 -0800 | [diff] [blame] | 13 | * * Neither the name of The Linux Foundation nor the names of its |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 14 | * contributors may be used to endorse or promote products derived |
| 15 | * from this software without specific prior written permission. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 21 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 24 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 25 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 26 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 27 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <cutils/log.h> |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 31 | #include <fcntl.h> |
Naomi Luis | 01f5c8e | 2013-02-11 12:46:24 -0800 | [diff] [blame] | 32 | #include <dlfcn.h> |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 33 | #include "gralloc_priv.h" |
| 34 | #include "alloc_controller.h" |
| 35 | #include "memalloc.h" |
| 36 | #include "ionalloc.h" |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 37 | #include "gr.h" |
Naseer Ahmed | a87da60 | 2012-07-01 23:54:19 -0700 | [diff] [blame] | 38 | #include "comptype.h" |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 39 | #include "mdp_version.h" |
Kaushik Kanetkar | 071aca6 | 2015-01-22 23:16:26 -0700 | [diff] [blame] | 40 | #include <qdMetaData.h> |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 41 | |
Sushil Chauhan | c6bd6d9 | 2012-12-12 12:33:01 -0800 | [diff] [blame] | 42 | #ifdef VENUS_COLOR_FORMAT |
| 43 | #include <media/msm_media_info.h> |
| 44 | #else |
| 45 | #define VENUS_Y_STRIDE(args...) 0 |
| 46 | #define VENUS_Y_SCANLINES(args...) 0 |
| 47 | #define VENUS_BUFFER_SIZE(args...) 0 |
| 48 | #endif |
| 49 | |
Naseer Ahmed | 63326f4 | 2013-12-18 02:45:48 -0500 | [diff] [blame] | 50 | #define ASTC_BLOCK_SIZE 16 |
Naseer Ahmed | 63326f4 | 2013-12-18 02:45:48 -0500 | [diff] [blame] | 51 | |
Shalaj Jain | 1f9725a | 2015-03-04 17:53:49 -0800 | [diff] [blame^] | 52 | #ifdef ION_FLAG_CP_PIXEL |
| 53 | #define CP_HEAP_ID ION_SECURE_HEAP_ID |
| 54 | #else |
| 55 | #define ION_FLAG_CP_PIXEL 0 |
| 56 | #define CP_HEAP_ID ION_CP_MM_HEAP_ID |
| 57 | #endif |
| 58 | |
| 59 | #ifndef ION_FLAG_ALLOW_NON_CONTIG |
| 60 | #define ION_FLAG_ALLOW_NON_CONTIG 0 |
| 61 | #endif |
| 62 | |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 63 | using namespace gralloc; |
Naseer Ahmed | a87da60 | 2012-07-01 23:54:19 -0700 | [diff] [blame] | 64 | using namespace qdutils; |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 65 | |
Naomi Luis | a44100c | 2013-02-08 12:42:03 -0800 | [diff] [blame] | 66 | ANDROID_SINGLETON_STATIC_INSTANCE(AdrenoMemInfo); |
| 67 | |
Sushil Chauhan | 65e2630 | 2015-01-14 10:48:57 -0800 | [diff] [blame] | 68 | static void getUBwcWidthAndHeight(int, int, int, int&, int&); |
| 69 | static unsigned int getUBwcSize(int, int, int, const int, const int); |
| 70 | |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 71 | //Common functions |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 72 | |
Saurabh Shah | 1adcafe | 2014-12-19 10:05:41 -0800 | [diff] [blame] | 73 | /* The default policy is to return cached buffers unless the client explicity |
| 74 | * sets the PRIVATE_UNCACHED flag or indicates that the buffer will be rarely |
| 75 | * read or written in software. Any combination with a _RARELY_ flag will be |
| 76 | * treated as uncached. */ |
| 77 | static bool useUncached(const int& usage) { |
| 78 | if((usage & GRALLOC_USAGE_PRIVATE_UNCACHED) or |
| 79 | ((usage & GRALLOC_USAGE_SW_WRITE_MASK) == |
| 80 | GRALLOC_USAGE_SW_WRITE_RARELY) or |
| 81 | ((usage & GRALLOC_USAGE_SW_READ_MASK) == |
| 82 | GRALLOC_USAGE_SW_READ_RARELY)) |
| 83 | return true; |
| 84 | |
| 85 | return false; |
| 86 | } |
| 87 | |
Naomi Luis | a44100c | 2013-02-08 12:42:03 -0800 | [diff] [blame] | 88 | //-------------- AdrenoMemInfo-----------------------// |
Naomi Luis | 01f5c8e | 2013-02-11 12:46:24 -0800 | [diff] [blame] | 89 | AdrenoMemInfo::AdrenoMemInfo() |
| 90 | { |
Ramkumar Radhakrishnan | 473f408 | 2013-11-04 14:29:18 -0800 | [diff] [blame] | 91 | LINK_adreno_compute_aligned_width_and_height = NULL; |
| 92 | LINK_adreno_compute_padding = NULL; |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 93 | LINK_adreno_isMacroTilingSupportedByGpu = NULL; |
Jeykumar Sankaran | 2ba2051 | 2014-02-27 15:21:42 -0800 | [diff] [blame] | 94 | LINK_adreno_compute_compressedfmt_aligned_width_and_height = NULL; |
Sushil Chauhan | 082acd6 | 2015-01-14 16:49:29 -0800 | [diff] [blame] | 95 | LINK_adreno_isUBWCSupportedByGpu = NULL; |
Ramkumar Radhakrishnan | 473f408 | 2013-11-04 14:29:18 -0800 | [diff] [blame] | 96 | |
Naomi Luis | 01f5c8e | 2013-02-11 12:46:24 -0800 | [diff] [blame] | 97 | libadreno_utils = ::dlopen("libadreno_utils.so", RTLD_NOW); |
| 98 | if (libadreno_utils) { |
Ramkumar Radhakrishnan | 473f408 | 2013-11-04 14:29:18 -0800 | [diff] [blame] | 99 | *(void **)&LINK_adreno_compute_aligned_width_and_height = |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 100 | ::dlsym(libadreno_utils, "compute_aligned_width_and_height"); |
| 101 | *(void **)&LINK_adreno_compute_padding = |
| 102 | ::dlsym(libadreno_utils, "compute_surface_padding"); |
| 103 | *(void **)&LINK_adreno_isMacroTilingSupportedByGpu = |
| 104 | ::dlsym(libadreno_utils, "isMacroTilingSupportedByGpu"); |
Jeykumar Sankaran | 2ba2051 | 2014-02-27 15:21:42 -0800 | [diff] [blame] | 105 | *(void **)&LINK_adreno_compute_compressedfmt_aligned_width_and_height = |
| 106 | ::dlsym(libadreno_utils, |
| 107 | "compute_compressedfmt_aligned_width_and_height"); |
Sushil Chauhan | 082acd6 | 2015-01-14 16:49:29 -0800 | [diff] [blame] | 108 | *(void **)&LINK_adreno_isUBWCSupportedByGpu = |
| 109 | ::dlsym(libadreno_utils, "isUBWCSupportedByGpu"); |
Naomi Luis | 01f5c8e | 2013-02-11 12:46:24 -0800 | [diff] [blame] | 110 | } |
| 111 | } |
| 112 | |
| 113 | AdrenoMemInfo::~AdrenoMemInfo() |
| 114 | { |
| 115 | if (libadreno_utils) { |
| 116 | ::dlclose(libadreno_utils); |
| 117 | } |
| 118 | } |
| 119 | |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 120 | int AdrenoMemInfo::isMacroTilingSupportedByGPU() |
| 121 | { |
| 122 | if ((libadreno_utils)) { |
| 123 | if(LINK_adreno_isMacroTilingSupportedByGpu) { |
| 124 | return LINK_adreno_isMacroTilingSupportedByGpu(); |
| 125 | } |
| 126 | } |
| 127 | return 0; |
| 128 | } |
| 129 | |
| 130 | |
Ramkumar Radhakrishnan | 473f408 | 2013-11-04 14:29:18 -0800 | [diff] [blame] | 131 | void AdrenoMemInfo::getAlignedWidthAndHeight(int width, int height, int format, |
Sushil Chauhan | 65e2630 | 2015-01-14 10:48:57 -0800 | [diff] [blame] | 132 | int usage, int& aligned_w, int& aligned_h) |
Naomi Luis | a44100c | 2013-02-08 12:42:03 -0800 | [diff] [blame] | 133 | { |
Sushil Chauhan | 65e2630 | 2015-01-14 10:48:57 -0800 | [diff] [blame] | 134 | |
Naomi Luis | 01f5c8e | 2013-02-11 12:46:24 -0800 | [diff] [blame] | 135 | // Currently surface padding is only computed for RGB* surfaces. |
Jesse Hall | fbe96d2 | 2013-09-20 01:39:43 -0700 | [diff] [blame] | 136 | if (format <= HAL_PIXEL_FORMAT_sRGB_X_8888) { |
Sushil Chauhan | 65e2630 | 2015-01-14 10:48:57 -0800 | [diff] [blame] | 137 | int tileEnabled = isMacroTileEnabled(format, usage); |
| 138 | AdrenoMemInfo::getInstance().getGpuAlignedWidthHeight(width, |
| 139 | height, format, tileEnabled, aligned_w, aligned_h); |
| 140 | return; |
Naomi Luis | a44100c | 2013-02-08 12:42:03 -0800 | [diff] [blame] | 141 | } |
Sushil Chauhan | 65e2630 | 2015-01-14 10:48:57 -0800 | [diff] [blame] | 142 | |
| 143 | if (isUBwcEnabled(format, usage)) { |
| 144 | getUBwcWidthAndHeight(width, height, format, aligned_w, aligned_h); |
| 145 | return; |
| 146 | } |
| 147 | |
| 148 | aligned_w = width; |
| 149 | aligned_h = height; |
| 150 | switch (format) |
| 151 | { |
| 152 | case HAL_PIXEL_FORMAT_YCrCb_420_SP: |
| 153 | case HAL_PIXEL_FORMAT_YCrCb_420_SP_ADRENO: |
| 154 | case HAL_PIXEL_FORMAT_RAW_SENSOR: |
| 155 | aligned_w = ALIGN(width, 32); |
| 156 | break; |
| 157 | case HAL_PIXEL_FORMAT_YCbCr_420_SP_TILED: |
| 158 | aligned_w = ALIGN(width, 128); |
| 159 | break; |
| 160 | case HAL_PIXEL_FORMAT_YCbCr_420_SP: |
| 161 | case HAL_PIXEL_FORMAT_YV12: |
| 162 | case HAL_PIXEL_FORMAT_YCbCr_422_SP: |
| 163 | case HAL_PIXEL_FORMAT_YCrCb_422_SP: |
| 164 | case HAL_PIXEL_FORMAT_YCbCr_422_I: |
| 165 | case HAL_PIXEL_FORMAT_YCrCb_422_I: |
| 166 | aligned_w = ALIGN(width, 16); |
| 167 | break; |
| 168 | case HAL_PIXEL_FORMAT_YCbCr_420_SP_VENUS: |
| 169 | case HAL_PIXEL_FORMAT_NV12_ENCODEABLE: |
| 170 | aligned_w = VENUS_Y_STRIDE(COLOR_FMT_NV12, width); |
| 171 | aligned_h = VENUS_Y_SCANLINES(COLOR_FMT_NV12, height); |
| 172 | break; |
| 173 | case HAL_PIXEL_FORMAT_BLOB: |
| 174 | break; |
| 175 | case HAL_PIXEL_FORMAT_NV21_ZSL: |
| 176 | aligned_w = ALIGN(width, 64); |
| 177 | aligned_h = ALIGN(height, 64); |
| 178 | break; |
| 179 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_4x4_KHR: |
| 180 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4_KHR: |
| 181 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_5x4_KHR: |
| 182 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4_KHR: |
| 183 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_5x5_KHR: |
| 184 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5_KHR: |
| 185 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_6x5_KHR: |
| 186 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5_KHR: |
| 187 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_6x6_KHR: |
| 188 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6_KHR: |
| 189 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_8x5_KHR: |
| 190 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_8x5_KHR: |
| 191 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_8x6_KHR: |
| 192 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_8x6_KHR: |
| 193 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_8x8_KHR: |
| 194 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_8x8_KHR: |
| 195 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_10x5_KHR: |
| 196 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_10x5_KHR: |
| 197 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_10x6_KHR: |
| 198 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_10x6_KHR: |
| 199 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_10x8_KHR: |
| 200 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_10x8_KHR: |
| 201 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_10x10_KHR: |
| 202 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_10x10_KHR: |
| 203 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_12x10_KHR: |
| 204 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_12x10_KHR: |
| 205 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_12x12_KHR: |
| 206 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_12x12_KHR: |
| 207 | if(LINK_adreno_compute_compressedfmt_aligned_width_and_height) { |
| 208 | int bytesPerPixel = 0; |
| 209 | int raster_mode = 0; //Adreno unknown raster mode. |
| 210 | int padding_threshold = 512; //Threshold for padding |
| 211 | //surfaces. |
| 212 | |
| 213 | LINK_adreno_compute_compressedfmt_aligned_width_and_height( |
| 214 | width, height, format, 0,raster_mode, padding_threshold, |
| 215 | &aligned_w, &aligned_h, &bytesPerPixel); |
| 216 | } else { |
| 217 | ALOGW("%s: Warning!! Symbols" \ |
| 218 | " compute_compressedfmt_aligned_width_and_height" \ |
| 219 | " not found", __FUNCTION__); |
| 220 | } |
| 221 | break; |
| 222 | default: break; |
| 223 | } |
| 224 | } |
| 225 | |
| 226 | void AdrenoMemInfo::getGpuAlignedWidthHeight(int width, int height, int format, |
| 227 | int tile_enabled, int& aligned_w, int& aligned_h) |
| 228 | { |
| 229 | aligned_w = ALIGN(width, 32); |
| 230 | aligned_h = ALIGN(height, 32); |
| 231 | |
| 232 | // Don't add any additional padding if debug.gralloc.map_fb_memory |
| 233 | // is enabled |
| 234 | char property[PROPERTY_VALUE_MAX]; |
| 235 | if((property_get("debug.gralloc.map_fb_memory", property, NULL) > 0) && |
| 236 | (!strncmp(property, "1", PROPERTY_VALUE_MAX ) || |
| 237 | (!strncasecmp(property,"true", PROPERTY_VALUE_MAX )))) { |
| 238 | return; |
| 239 | } |
| 240 | |
| 241 | int bpp = 4; |
| 242 | switch(format) |
| 243 | { |
| 244 | case HAL_PIXEL_FORMAT_RGB_888: |
| 245 | bpp = 3; |
| 246 | break; |
| 247 | case HAL_PIXEL_FORMAT_RGB_565: |
| 248 | case HAL_PIXEL_FORMAT_RGBA_5551: |
| 249 | case HAL_PIXEL_FORMAT_RGBA_4444: |
| 250 | bpp = 2; |
| 251 | break; |
| 252 | default: break; |
| 253 | } |
| 254 | |
| 255 | if (libadreno_utils) { |
| 256 | int raster_mode = 0; // Adreno unknown raster mode. |
| 257 | int padding_threshold = 512; // Threshold for padding surfaces. |
| 258 | // the function below computes aligned width and aligned height |
| 259 | // based on linear or macro tile mode selected. |
| 260 | if(LINK_adreno_compute_aligned_width_and_height) { |
| 261 | LINK_adreno_compute_aligned_width_and_height(width, |
| 262 | height, bpp, tile_enabled, |
| 263 | raster_mode, padding_threshold, |
| 264 | &aligned_w, &aligned_h); |
| 265 | |
| 266 | } else if(LINK_adreno_compute_padding) { |
| 267 | int surface_tile_height = 1; // Linear surface |
| 268 | aligned_w = LINK_adreno_compute_padding(width, bpp, |
| 269 | surface_tile_height, raster_mode, |
| 270 | padding_threshold); |
| 271 | ALOGW("%s: Warning!! Old GFX API is used to calculate stride", |
| 272 | __FUNCTION__); |
| 273 | } else { |
| 274 | ALOGW("%s: Warning!! Symbols compute_surface_padding and " \ |
| 275 | "compute_aligned_width_and_height not found", __FUNCTION__); |
| 276 | } |
| 277 | } |
| 278 | } |
| 279 | |
| 280 | int AdrenoMemInfo::isUBWCSupportedByGPU(int format) |
| 281 | { |
Sushil Chauhan | 082acd6 | 2015-01-14 16:49:29 -0800 | [diff] [blame] | 282 | if (libadreno_utils) { |
| 283 | if (LINK_adreno_isUBWCSupportedByGpu) { |
| 284 | ADRENOPIXELFORMAT gpu_format = getGpuPixelFormat(format); |
| 285 | return LINK_adreno_isUBWCSupportedByGpu(gpu_format); |
| 286 | } |
| 287 | } |
Sushil Chauhan | 65e2630 | 2015-01-14 10:48:57 -0800 | [diff] [blame] | 288 | return 0; |
Naomi Luis | a44100c | 2013-02-08 12:42:03 -0800 | [diff] [blame] | 289 | } |
| 290 | |
Sushil Chauhan | 082acd6 | 2015-01-14 16:49:29 -0800 | [diff] [blame] | 291 | ADRENOPIXELFORMAT AdrenoMemInfo::getGpuPixelFormat(int hal_format) |
| 292 | { |
| 293 | switch (hal_format) { |
| 294 | case HAL_PIXEL_FORMAT_RGBA_8888: |
| 295 | return ADRENO_PIXELFORMAT_R8G8B8A8; |
| 296 | case HAL_PIXEL_FORMAT_RGB_565: |
| 297 | return ADRENO_PIXELFORMAT_B5G6R5; |
| 298 | case HAL_PIXEL_FORMAT_sRGB_A_8888: |
| 299 | return ADRENO_PIXELFORMAT_R8G8B8A8_SRGB; |
| 300 | case HAL_PIXEL_FORMAT_NV12_ENCODEABLE: |
Sushil Chauhan | a9d4700 | 2015-02-18 14:55:03 -0800 | [diff] [blame] | 301 | return ADRENO_PIXELFORMAT_NV12; |
Sushil Chauhan | 082acd6 | 2015-01-14 16:49:29 -0800 | [diff] [blame] | 302 | case HAL_PIXEL_FORMAT_YCbCr_420_SP_VENUS: |
| 303 | case HAL_PIXEL_FORMAT_YCbCr_420_SP_VENUS_UBWC: |
Sushil Chauhan | a9d4700 | 2015-02-18 14:55:03 -0800 | [diff] [blame] | 304 | return ADRENO_PIXELFORMAT_NV12_EXT; |
Sushil Chauhan | 082acd6 | 2015-01-14 16:49:29 -0800 | [diff] [blame] | 305 | default: |
| 306 | ALOGE("%s: No map for format: 0x%x", __FUNCTION__, hal_format); |
| 307 | break; |
| 308 | } |
| 309 | return ADRENO_PIXELFORMAT_UNKNOWN; |
| 310 | } |
| 311 | |
Naomi Luis | a44100c | 2013-02-08 12:42:03 -0800 | [diff] [blame] | 312 | //-------------- IAllocController-----------------------// |
Naseer Ahmed | 01d3fd3 | 2012-07-14 21:08:13 -0700 | [diff] [blame] | 313 | IAllocController* IAllocController::sController = NULL; |
| 314 | IAllocController* IAllocController::getInstance(void) |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 315 | { |
| 316 | if(sController == NULL) { |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 317 | sController = new IonController(); |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 318 | } |
| 319 | return sController; |
| 320 | } |
| 321 | |
| 322 | |
| 323 | //-------------- IonController-----------------------// |
| 324 | IonController::IonController() |
| 325 | { |
Praveena Pachipulusu | 2005e8f | 2014-05-07 20:01:54 +0530 | [diff] [blame] | 326 | allocateIonMem(); |
| 327 | } |
| 328 | |
| 329 | void IonController::allocateIonMem() |
| 330 | { |
| 331 | mIonAlloc = new IonAlloc(); |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 332 | } |
| 333 | |
Naseer Ahmed | 01d3fd3 | 2012-07-14 21:08:13 -0700 | [diff] [blame] | 334 | int IonController::allocate(alloc_data& data, int usage) |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 335 | { |
| 336 | int ionFlags = 0; |
Naseer Ahmed | 8d0d72a | 2014-12-19 16:25:09 -0500 | [diff] [blame] | 337 | int ionHeapId = 0; |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 338 | int ret; |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 339 | |
| 340 | data.uncached = useUncached(usage); |
Naseer Ahmed | 29a2681 | 2012-06-14 00:56:20 -0700 | [diff] [blame] | 341 | data.allocType = 0; |
| 342 | |
Prabhanjan Kandula | 92896b8 | 2013-05-07 19:58:24 +0530 | [diff] [blame] | 343 | if(usage & GRALLOC_USAGE_PROTECTED) { |
Prabhanjan Kandula | e8f4bec | 2013-10-24 16:32:51 +0530 | [diff] [blame] | 344 | if (usage & GRALLOC_USAGE_PRIVATE_MM_HEAP) { |
Shalaj Jain | 1f9725a | 2015-03-04 17:53:49 -0800 | [diff] [blame^] | 345 | ionHeapId = ION_HEAP(CP_HEAP_ID); |
Naseer Ahmed | c5e6fb0 | 2013-03-07 13:42:20 -0500 | [diff] [blame] | 346 | ionFlags |= ION_SECURE; |
Shalaj Jain | 1f9725a | 2015-03-04 17:53:49 -0800 | [diff] [blame^] | 347 | if (usage & GRALLOC_USAGE_PRIVATE_SECURE_DISPLAY) { |
| 348 | /* |
| 349 | * There is currently no flag in ION for Secure Display |
| 350 | * VM. Please add it here once available. |
| 351 | * |
| 352 | ionFlags |= <Ion flag for Secure Display>; |
| 353 | */ |
| 354 | } else { |
| 355 | ionFlags |= ION_FLAG_CP_PIXEL; |
| 356 | } |
| 357 | |
Shalaj Jain | 13cdf81 | 2014-12-02 16:20:54 -0800 | [diff] [blame] | 358 | if (!(usage & GRALLOC_USAGE_PRIVATE_SECURE_DISPLAY)) { |
| 359 | ionFlags |= ION_FLAG_ALLOW_NON_CONTIG; |
| 360 | } |
Prabhanjan Kandula | 92896b8 | 2013-05-07 19:58:24 +0530 | [diff] [blame] | 361 | } else { |
| 362 | // for targets/OEMs which do not need HW level protection |
Naseer Ahmed | 8d0d72a | 2014-12-19 16:25:09 -0500 | [diff] [blame] | 363 | // do not set ion secure flag & MM heap. Fallback to system heap. |
| 364 | ionHeapId |= ION_HEAP(ION_SYSTEM_HEAP_ID); |
Justin Philip | d616660 | 2014-08-12 13:42:21 +0530 | [diff] [blame] | 365 | data.allocType |= private_handle_t::PRIV_FLAGS_PROTECTED_BUFFER; |
Naseer Ahmed | c5e6fb0 | 2013-03-07 13:42:20 -0500 | [diff] [blame] | 366 | } |
Prabhanjan Kandula | 92896b8 | 2013-05-07 19:58:24 +0530 | [diff] [blame] | 367 | } else if(usage & GRALLOC_USAGE_PRIVATE_MM_HEAP) { |
| 368 | //MM Heap is exclusively a secure heap. |
| 369 | //If it is used for non secure cases, fallback to IOMMU heap |
| 370 | ALOGW("GRALLOC_USAGE_PRIVATE_MM_HEAP \ |
| 371 | cannot be used as an insecure heap!\ |
Naseer Ahmed | 8d0d72a | 2014-12-19 16:25:09 -0500 | [diff] [blame] | 372 | trying to use system heap instead !!"); |
| 373 | ionHeapId |= ION_HEAP(ION_SYSTEM_HEAP_ID); |
Naseer Ahmed | c5e6fb0 | 2013-03-07 13:42:20 -0500 | [diff] [blame] | 374 | } |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 375 | |
Arun Kumar K.R | ff78b89 | 2013-05-24 12:37:51 -0700 | [diff] [blame] | 376 | if(usage & GRALLOC_USAGE_PRIVATE_CAMERA_HEAP) |
Naseer Ahmed | 8d0d72a | 2014-12-19 16:25:09 -0500 | [diff] [blame] | 377 | ionHeapId |= ION_HEAP(ION_CAMERA_HEAP_ID); |
Arun Kumar K.R | ff78b89 | 2013-05-24 12:37:51 -0700 | [diff] [blame] | 378 | |
Arun Kumar K.R | 0daaa99 | 2013-03-12 15:08:29 -0700 | [diff] [blame] | 379 | if(usage & GRALLOC_USAGE_PRIVATE_ADSP_HEAP) |
Naseer Ahmed | 8d0d72a | 2014-12-19 16:25:09 -0500 | [diff] [blame] | 380 | ionHeapId |= ION_HEAP(ION_ADSP_HEAP_ID); |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 381 | |
Prabhanjan Kandula | 92896b8 | 2013-05-07 19:58:24 +0530 | [diff] [blame] | 382 | if(ionFlags & ION_SECURE) |
Naseer Ahmed | c5e6fb0 | 2013-03-07 13:42:20 -0500 | [diff] [blame] | 383 | data.allocType |= private_handle_t::PRIV_FLAGS_SECURE_BUFFER; |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 384 | |
Naseer Ahmed | 8d0d72a | 2014-12-19 16:25:09 -0500 | [diff] [blame] | 385 | // if no ion heap flags are set, default to system heap |
| 386 | if(!ionHeapId) |
| 387 | ionHeapId = ION_HEAP(ION_SYSTEM_HEAP_ID); |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 388 | |
Naseer Ahmed | 8d0d72a | 2014-12-19 16:25:09 -0500 | [diff] [blame] | 389 | //At this point we should have the right heap set, there is no fallback |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 390 | data.flags = ionFlags; |
Naseer Ahmed | 8d0d72a | 2014-12-19 16:25:09 -0500 | [diff] [blame] | 391 | data.heapId = ionHeapId; |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 392 | ret = mIonAlloc->alloc_buffer(data); |
Naseer Ahmed | 29a2681 | 2012-06-14 00:56:20 -0700 | [diff] [blame] | 393 | |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 394 | if(ret >= 0 ) { |
Naseer Ahmed | 29a2681 | 2012-06-14 00:56:20 -0700 | [diff] [blame] | 395 | data.allocType |= private_handle_t::PRIV_FLAGS_USES_ION; |
Naseer Ahmed | 8d0d72a | 2014-12-19 16:25:09 -0500 | [diff] [blame] | 396 | } else { |
| 397 | ALOGE("%s: Failed to allocate buffer - heap: 0x%x flags: 0x%x", |
| 398 | __FUNCTION__, ionHeapId, ionFlags); |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 399 | } |
| 400 | |
| 401 | return ret; |
| 402 | } |
| 403 | |
Naseer Ahmed | 01d3fd3 | 2012-07-14 21:08:13 -0700 | [diff] [blame] | 404 | IMemAlloc* IonController::getAllocator(int flags) |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 405 | { |
Naseer Ahmed | b16edac | 2012-07-15 23:56:21 -0700 | [diff] [blame] | 406 | IMemAlloc* memalloc = NULL; |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 407 | if (flags & private_handle_t::PRIV_FLAGS_USES_ION) { |
| 408 | memalloc = mIonAlloc; |
| 409 | } else { |
| 410 | ALOGE("%s: Invalid flags passed: 0x%x", __FUNCTION__, flags); |
| 411 | } |
| 412 | |
| 413 | return memalloc; |
| 414 | } |
| 415 | |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 416 | bool isMacroTileEnabled(int format, int usage) |
| 417 | { |
| 418 | bool tileEnabled = false; |
| 419 | |
| 420 | // Check whether GPU & MDSS supports MacroTiling feature |
| 421 | if(AdrenoMemInfo::getInstance().isMacroTilingSupportedByGPU() && |
| 422 | qdutils::MDPVersion::getInstance().supportsMacroTile()) |
| 423 | { |
| 424 | // check the format |
| 425 | switch(format) |
| 426 | { |
| 427 | case HAL_PIXEL_FORMAT_RGBA_8888: |
| 428 | case HAL_PIXEL_FORMAT_RGBX_8888: |
| 429 | case HAL_PIXEL_FORMAT_BGRA_8888: |
Manoj Kumar AVM | 5a5529b | 2014-02-24 18:16:37 -0800 | [diff] [blame] | 430 | case HAL_PIXEL_FORMAT_RGB_565: |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 431 | { |
| 432 | tileEnabled = true; |
| 433 | // check the usage flags |
| 434 | if (usage & (GRALLOC_USAGE_SW_READ_MASK | |
| 435 | GRALLOC_USAGE_SW_WRITE_MASK)) { |
| 436 | // Application intends to use CPU for rendering |
| 437 | tileEnabled = false; |
| 438 | } |
| 439 | break; |
| 440 | } |
| 441 | default: |
| 442 | break; |
| 443 | } |
| 444 | } |
| 445 | return tileEnabled; |
| 446 | } |
| 447 | |
| 448 | // helper function |
Sushil Chauhan | 65e2630 | 2015-01-14 10:48:57 -0800 | [diff] [blame] | 449 | unsigned int getSize(int format, int width, int height, int usage, |
| 450 | const int alignedw, const int alignedh) { |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 451 | |
Sushil Chauhan | 65e2630 | 2015-01-14 10:48:57 -0800 | [diff] [blame] | 452 | if (isUBwcEnabled(format, usage)) { |
| 453 | return getUBwcSize(width, height, format, alignedw, alignedh); |
| 454 | } |
| 455 | |
| 456 | unsigned int size = 0; |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 457 | switch (format) { |
| 458 | case HAL_PIXEL_FORMAT_RGBA_8888: |
| 459 | case HAL_PIXEL_FORMAT_RGBX_8888: |
| 460 | case HAL_PIXEL_FORMAT_BGRA_8888: |
Naseer Ahmed | 82fc4b7 | 2013-09-20 01:31:37 -0700 | [diff] [blame] | 461 | case HAL_PIXEL_FORMAT_sRGB_A_8888: |
Jesse Hall | fbe96d2 | 2013-09-20 01:39:43 -0700 | [diff] [blame] | 462 | case HAL_PIXEL_FORMAT_sRGB_X_8888: |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 463 | size = alignedw * alignedh * 4; |
| 464 | break; |
| 465 | case HAL_PIXEL_FORMAT_RGB_888: |
| 466 | size = alignedw * alignedh * 3; |
| 467 | break; |
| 468 | case HAL_PIXEL_FORMAT_RGB_565: |
Ramkumar Radhakrishnan | 9643952 | 2014-10-09 13:37:52 -0700 | [diff] [blame] | 469 | case HAL_PIXEL_FORMAT_RGBA_5551: |
| 470 | case HAL_PIXEL_FORMAT_RGBA_4444: |
Naseer Ahmed | 7669dae | 2013-04-17 20:23:53 -0400 | [diff] [blame] | 471 | case HAL_PIXEL_FORMAT_RAW_SENSOR: |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 472 | size = alignedw * alignedh * 2; |
| 473 | break; |
| 474 | |
| 475 | // adreno formats |
| 476 | case HAL_PIXEL_FORMAT_YCrCb_420_SP_ADRENO: // NV21 |
| 477 | size = ALIGN(alignedw*alignedh, 4096); |
| 478 | size += ALIGN(2 * ALIGN(width/2, 32) * ALIGN(height/2, 32), 4096); |
| 479 | break; |
| 480 | case HAL_PIXEL_FORMAT_YCbCr_420_SP_TILED: // NV12 |
| 481 | // The chroma plane is subsampled, |
| 482 | // but the pitch in bytes is unchanged |
| 483 | // The GPU needs 4K alignment, but the video decoder needs 8K |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 484 | size = ALIGN( alignedw * alignedh, 8192); |
| 485 | size += ALIGN( alignedw * ALIGN(height/2, 32), 8192); |
| 486 | break; |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 487 | case HAL_PIXEL_FORMAT_YV12: |
| 488 | if ((format == HAL_PIXEL_FORMAT_YV12) && ((width&1) || (height&1))) { |
| 489 | ALOGE("w or h is odd for the YV12 format"); |
Saurabh Shah | d0b0d8f | 2014-01-31 11:45:56 -0800 | [diff] [blame] | 490 | return 0; |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 491 | } |
Naseer Ahmed | ce0c950 | 2013-08-15 13:07:24 -0400 | [diff] [blame] | 492 | size = alignedw*alignedh + |
Naseer Ahmed | 29a2681 | 2012-06-14 00:56:20 -0700 | [diff] [blame] | 493 | (ALIGN(alignedw/2, 16) * (alignedh/2))*2; |
Saurabh Shah | 8f0ea6f | 2014-05-19 16:48:53 -0700 | [diff] [blame] | 494 | size = ALIGN(size, (unsigned int)4096); |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 495 | break; |
Ramkumar Radhakrishnan | 73f952a | 2013-03-05 14:14:24 -0800 | [diff] [blame] | 496 | case HAL_PIXEL_FORMAT_YCbCr_420_SP: |
| 497 | case HAL_PIXEL_FORMAT_YCrCb_420_SP: |
Naseer Ahmed | 2c21529 | 2013-09-18 23:47:42 -0400 | [diff] [blame] | 498 | size = ALIGN((alignedw*alignedh) + (alignedw* alignedh)/2 + 1, 4096); |
Ramkumar Radhakrishnan | 73f952a | 2013-03-05 14:14:24 -0800 | [diff] [blame] | 499 | break; |
Naseer Ahmed | 29a2681 | 2012-06-14 00:56:20 -0700 | [diff] [blame] | 500 | case HAL_PIXEL_FORMAT_YCbCr_422_SP: |
| 501 | case HAL_PIXEL_FORMAT_YCrCb_422_SP: |
Ramkumar Radhakrishnan | b52399c | 2013-08-06 20:17:29 -0700 | [diff] [blame] | 502 | case HAL_PIXEL_FORMAT_YCbCr_422_I: |
| 503 | case HAL_PIXEL_FORMAT_YCrCb_422_I: |
Naseer Ahmed | 29a2681 | 2012-06-14 00:56:20 -0700 | [diff] [blame] | 504 | if(width & 1) { |
| 505 | ALOGE("width is odd for the YUV422_SP format"); |
Saurabh Shah | d0b0d8f | 2014-01-31 11:45:56 -0800 | [diff] [blame] | 506 | return 0; |
Naseer Ahmed | 29a2681 | 2012-06-14 00:56:20 -0700 | [diff] [blame] | 507 | } |
Naseer Ahmed | 29a2681 | 2012-06-14 00:56:20 -0700 | [diff] [blame] | 508 | size = ALIGN(alignedw * alignedh * 2, 4096); |
| 509 | break; |
Sushil Chauhan | c5e6148 | 2012-08-22 17:13:32 -0700 | [diff] [blame] | 510 | case HAL_PIXEL_FORMAT_YCbCr_420_SP_VENUS: |
Naseer Ahmed | ce0c950 | 2013-08-15 13:07:24 -0400 | [diff] [blame] | 511 | case HAL_PIXEL_FORMAT_NV12_ENCODEABLE: |
Sushil Chauhan | e8a0179 | 2012-11-01 16:25:45 -0700 | [diff] [blame] | 512 | size = VENUS_BUFFER_SIZE(COLOR_FMT_NV12, width, height); |
Sushil Chauhan | c5e6148 | 2012-08-22 17:13:32 -0700 | [diff] [blame] | 513 | break; |
Naseer Ahmed | 7669dae | 2013-04-17 20:23:53 -0400 | [diff] [blame] | 514 | case HAL_PIXEL_FORMAT_BLOB: |
| 515 | if(height != 1) { |
| 516 | ALOGE("%s: Buffers with format HAL_PIXEL_FORMAT_BLOB \ |
| 517 | must have height==1 ", __FUNCTION__); |
Saurabh Shah | d0b0d8f | 2014-01-31 11:45:56 -0800 | [diff] [blame] | 518 | return 0; |
Naseer Ahmed | 7669dae | 2013-04-17 20:23:53 -0400 | [diff] [blame] | 519 | } |
Naseer Ahmed | 7669dae | 2013-04-17 20:23:53 -0400 | [diff] [blame] | 520 | size = width; |
| 521 | break; |
Ramkumar Radhakrishnan | ff51102 | 2013-07-23 16:12:08 -0700 | [diff] [blame] | 522 | case HAL_PIXEL_FORMAT_NV21_ZSL: |
Ramkumar Radhakrishnan | ff51102 | 2013-07-23 16:12:08 -0700 | [diff] [blame] | 523 | size = ALIGN((alignedw*alignedh) + (alignedw* alignedh)/2, 4096); |
| 524 | break; |
Naseer Ahmed | 63326f4 | 2013-12-18 02:45:48 -0500 | [diff] [blame] | 525 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_4x4_KHR: |
| 526 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_5x4_KHR: |
| 527 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_5x5_KHR: |
| 528 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_6x5_KHR: |
| 529 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_6x6_KHR: |
| 530 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_8x5_KHR: |
| 531 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_8x6_KHR: |
| 532 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_8x8_KHR: |
| 533 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_10x5_KHR: |
| 534 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_10x6_KHR: |
| 535 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_10x8_KHR: |
| 536 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_10x10_KHR: |
| 537 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_12x10_KHR: |
| 538 | case HAL_PIXEL_FORMAT_COMPRESSED_RGBA_ASTC_12x12_KHR: |
| 539 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4_KHR: |
| 540 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4_KHR: |
| 541 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5_KHR: |
| 542 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5_KHR: |
| 543 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6_KHR: |
| 544 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_8x5_KHR: |
| 545 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_8x6_KHR: |
| 546 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_8x8_KHR: |
| 547 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_10x5_KHR: |
| 548 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_10x6_KHR: |
| 549 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_10x8_KHR: |
| 550 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_10x10_KHR: |
| 551 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_12x10_KHR: |
Jeykumar Sankaran | 8f4585f | 2014-02-05 15:23:40 -0800 | [diff] [blame] | 552 | case HAL_PIXEL_FORMAT_COMPRESSED_SRGB8_ALPHA8_ASTC_12x12_KHR: |
Naseer Ahmed | 63326f4 | 2013-12-18 02:45:48 -0500 | [diff] [blame] | 553 | size = alignedw * alignedh * ASTC_BLOCK_SIZE; |
| 554 | break; |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 555 | default: |
Sushil Chauhan | 65e2630 | 2015-01-14 10:48:57 -0800 | [diff] [blame] | 556 | ALOGE("Unrecognized pixel format: 0x%x", __FUNCTION__, format); |
Saurabh Shah | d0b0d8f | 2014-01-31 11:45:56 -0800 | [diff] [blame] | 557 | return 0; |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 558 | } |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 559 | return size; |
| 560 | } |
| 561 | |
Saurabh Shah | 8f0ea6f | 2014-05-19 16:48:53 -0700 | [diff] [blame] | 562 | unsigned int getBufferSizeAndDimensions(int width, int height, int format, |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 563 | int& alignedw, int &alignedh) |
| 564 | { |
Saurabh Shah | 8f0ea6f | 2014-05-19 16:48:53 -0700 | [diff] [blame] | 565 | unsigned int size; |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 566 | |
| 567 | AdrenoMemInfo::getInstance().getAlignedWidthAndHeight(width, |
| 568 | height, |
| 569 | format, |
Sushil Chauhan | 65e2630 | 2015-01-14 10:48:57 -0800 | [diff] [blame] | 570 | 0, |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 571 | alignedw, |
| 572 | alignedh); |
| 573 | |
Sushil Chauhan | 65e2630 | 2015-01-14 10:48:57 -0800 | [diff] [blame] | 574 | size = getSize(format, width, height, 0 /* usage */, alignedw, alignedh); |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 575 | |
| 576 | return size; |
| 577 | } |
| 578 | |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 579 | |
Saurabh Shah | 8f0ea6f | 2014-05-19 16:48:53 -0700 | [diff] [blame] | 580 | unsigned int getBufferSizeAndDimensions(int width, int height, int format, |
| 581 | int usage, int& alignedw, int &alignedh) |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 582 | { |
Saurabh Shah | 8f0ea6f | 2014-05-19 16:48:53 -0700 | [diff] [blame] | 583 | unsigned int size; |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 584 | |
| 585 | AdrenoMemInfo::getInstance().getAlignedWidthAndHeight(width, |
| 586 | height, |
| 587 | format, |
Sushil Chauhan | 65e2630 | 2015-01-14 10:48:57 -0800 | [diff] [blame] | 588 | usage, |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 589 | alignedw, |
| 590 | alignedh); |
| 591 | |
Sushil Chauhan | 65e2630 | 2015-01-14 10:48:57 -0800 | [diff] [blame] | 592 | size = getSize(format, width, height, usage, alignedw, alignedh); |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 593 | |
| 594 | return size; |
| 595 | } |
| 596 | |
| 597 | |
| 598 | void getBufferAttributes(int width, int height, int format, int usage, |
Saurabh Shah | 8f0ea6f | 2014-05-19 16:48:53 -0700 | [diff] [blame] | 599 | int& alignedw, int &alignedh, int& tileEnabled, unsigned int& size) |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 600 | { |
| 601 | tileEnabled = isMacroTileEnabled(format, usage); |
| 602 | |
| 603 | AdrenoMemInfo::getInstance().getAlignedWidthAndHeight(width, |
| 604 | height, |
| 605 | format, |
Sushil Chauhan | 65e2630 | 2015-01-14 10:48:57 -0800 | [diff] [blame] | 606 | usage, |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 607 | alignedw, |
| 608 | alignedh); |
Sushil Chauhan | 65e2630 | 2015-01-14 10:48:57 -0800 | [diff] [blame] | 609 | size = getSize(format, width, height, usage, alignedw, alignedh); |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 610 | } |
| 611 | |
Naseer Ahmed | b29fdfd | 2014-04-08 20:23:47 -0400 | [diff] [blame] | 612 | int getYUVPlaneInfo(private_handle_t* hnd, struct android_ycbcr* ycbcr) |
| 613 | { |
| 614 | int err = 0; |
Kaushik Kanetkar | 071aca6 | 2015-01-22 23:16:26 -0700 | [diff] [blame] | 615 | int width = hnd->width; |
| 616 | int height = hnd->height; |
Saurabh Shah | 8f0ea6f | 2014-05-19 16:48:53 -0700 | [diff] [blame] | 617 | unsigned int ystride, cstride; |
Sushil Chauhan | 4686c97 | 2015-02-20 15:44:52 -0800 | [diff] [blame] | 618 | unsigned int alignment = 4096; |
Kaushik Kanetkar | 071aca6 | 2015-01-22 23:16:26 -0700 | [diff] [blame] | 619 | |
Naseer Ahmed | b29fdfd | 2014-04-08 20:23:47 -0400 | [diff] [blame] | 620 | memset(ycbcr->reserved, 0, sizeof(ycbcr->reserved)); |
| 621 | |
Kaushik Kanetkar | 071aca6 | 2015-01-22 23:16:26 -0700 | [diff] [blame] | 622 | // Check metadata if the geometry has been updated. |
| 623 | MetaData_t *metadata = (MetaData_t *)hnd->base_metadata; |
| 624 | if(metadata && metadata->operation & UPDATE_BUFFER_GEOMETRY) { |
| 625 | AdrenoMemInfo::getInstance().getAlignedWidthAndHeight(metadata->bufferDim.sliceWidth, |
| 626 | metadata->bufferDim.sliceHeight, hnd->format, 0, width, height); |
| 627 | } |
| 628 | |
Naseer Ahmed | b29fdfd | 2014-04-08 20:23:47 -0400 | [diff] [blame] | 629 | // Get the chroma offsets from the handle width/height. We take advantage |
| 630 | // of the fact the width _is_ the stride |
| 631 | switch (hnd->format) { |
| 632 | //Semiplanar |
| 633 | case HAL_PIXEL_FORMAT_YCbCr_420_SP: |
| 634 | case HAL_PIXEL_FORMAT_YCbCr_422_SP: |
| 635 | case HAL_PIXEL_FORMAT_YCbCr_420_SP_VENUS: |
| 636 | case HAL_PIXEL_FORMAT_NV12_ENCODEABLE: //Same as YCbCr_420_SP_VENUS |
Kaushik Kanetkar | 071aca6 | 2015-01-22 23:16:26 -0700 | [diff] [blame] | 637 | ystride = cstride = width; |
Naseer Ahmed | b29fdfd | 2014-04-08 20:23:47 -0400 | [diff] [blame] | 638 | ycbcr->y = (void*)hnd->base; |
Kaushik Kanetkar | 071aca6 | 2015-01-22 23:16:26 -0700 | [diff] [blame] | 639 | ycbcr->cb = (void*)(hnd->base + ystride * height); |
| 640 | ycbcr->cr = (void*)(hnd->base + ystride * height + 1); |
Naseer Ahmed | b29fdfd | 2014-04-08 20:23:47 -0400 | [diff] [blame] | 641 | ycbcr->ystride = ystride; |
| 642 | ycbcr->cstride = cstride; |
| 643 | ycbcr->chroma_step = 2; |
| 644 | break; |
| 645 | |
Sushil Chauhan | 4686c97 | 2015-02-20 15:44:52 -0800 | [diff] [blame] | 646 | case HAL_PIXEL_FORMAT_YCbCr_420_SP_VENUS_UBWC: |
| 647 | // NV12_UBWC buffer has these 4 planes in the following sequence: |
| 648 | // Y_Meta_Plane, Y_Plane, UV_Meta_Plane, UV_Plane |
| 649 | unsigned int y_meta_stride, y_meta_height, y_meta_size; |
| 650 | unsigned int y_stride, y_height, y_size; |
| 651 | unsigned int c_meta_stride, c_meta_height, c_meta_size; |
| 652 | |
| 653 | y_meta_stride = VENUS_Y_META_STRIDE(COLOR_FMT_NV12_UBWC, width); |
| 654 | y_meta_height = VENUS_Y_META_SCANLINES(COLOR_FMT_NV12_UBWC, height); |
| 655 | y_meta_size = ALIGN((y_meta_stride * y_meta_height), alignment); |
| 656 | |
| 657 | y_stride = VENUS_Y_STRIDE(COLOR_FMT_NV12_UBWC, width); |
| 658 | y_height = VENUS_Y_SCANLINES(COLOR_FMT_NV12_UBWC, height); |
| 659 | y_size = ALIGN((y_stride * y_height), alignment); |
| 660 | |
| 661 | c_meta_stride = VENUS_UV_META_STRIDE(COLOR_FMT_NV12_UBWC, width); |
| 662 | c_meta_height = VENUS_UV_META_SCANLINES(COLOR_FMT_NV12_UBWC, height); |
| 663 | c_meta_size = ALIGN((c_meta_stride * c_meta_height), alignment); |
| 664 | |
| 665 | ycbcr->y = (void*)(hnd->base + y_meta_size); |
| 666 | ycbcr->cb = (void*)(hnd->base + y_meta_size + y_size + c_meta_size); |
| 667 | ycbcr->cr = (void*)(hnd->base + y_meta_size + y_size + |
| 668 | c_meta_size + 1); |
| 669 | ycbcr->ystride = y_stride; |
| 670 | ycbcr->cstride = VENUS_UV_STRIDE(COLOR_FMT_NV12_UBWC, width); |
| 671 | ycbcr->chroma_step = 2; |
| 672 | break; |
| 673 | |
Naseer Ahmed | b29fdfd | 2014-04-08 20:23:47 -0400 | [diff] [blame] | 674 | case HAL_PIXEL_FORMAT_YCrCb_420_SP: |
| 675 | case HAL_PIXEL_FORMAT_YCrCb_422_SP: |
| 676 | case HAL_PIXEL_FORMAT_YCrCb_420_SP_ADRENO: |
| 677 | case HAL_PIXEL_FORMAT_NV21_ZSL: |
| 678 | case HAL_PIXEL_FORMAT_RAW_SENSOR: |
Kaushik Kanetkar | 071aca6 | 2015-01-22 23:16:26 -0700 | [diff] [blame] | 679 | ystride = cstride = width; |
Naseer Ahmed | b29fdfd | 2014-04-08 20:23:47 -0400 | [diff] [blame] | 680 | ycbcr->y = (void*)hnd->base; |
Kaushik Kanetkar | 071aca6 | 2015-01-22 23:16:26 -0700 | [diff] [blame] | 681 | ycbcr->cr = (void*)(hnd->base + ystride * height); |
| 682 | ycbcr->cb = (void*)(hnd->base + ystride * height + 1); |
Naseer Ahmed | b29fdfd | 2014-04-08 20:23:47 -0400 | [diff] [blame] | 683 | ycbcr->ystride = ystride; |
| 684 | ycbcr->cstride = cstride; |
| 685 | ycbcr->chroma_step = 2; |
| 686 | break; |
| 687 | |
| 688 | //Planar |
| 689 | case HAL_PIXEL_FORMAT_YV12: |
Kaushik Kanetkar | 071aca6 | 2015-01-22 23:16:26 -0700 | [diff] [blame] | 690 | ystride = width; |
| 691 | cstride = ALIGN(width/2, 16); |
Naseer Ahmed | b29fdfd | 2014-04-08 20:23:47 -0400 | [diff] [blame] | 692 | ycbcr->y = (void*)hnd->base; |
Kaushik Kanetkar | 071aca6 | 2015-01-22 23:16:26 -0700 | [diff] [blame] | 693 | ycbcr->cr = (void*)(hnd->base + ystride * height); |
| 694 | ycbcr->cb = (void*)(hnd->base + ystride * height + |
| 695 | cstride * height/2); |
Naseer Ahmed | b29fdfd | 2014-04-08 20:23:47 -0400 | [diff] [blame] | 696 | ycbcr->ystride = ystride; |
| 697 | ycbcr->cstride = cstride; |
| 698 | ycbcr->chroma_step = 1; |
Naseer Ahmed | b29fdfd | 2014-04-08 20:23:47 -0400 | [diff] [blame] | 699 | break; |
| 700 | //Unsupported formats |
| 701 | case HAL_PIXEL_FORMAT_YCbCr_422_I: |
| 702 | case HAL_PIXEL_FORMAT_YCrCb_422_I: |
| 703 | case HAL_PIXEL_FORMAT_YCbCr_420_SP_TILED: |
| 704 | default: |
| 705 | ALOGD("%s: Invalid format passed: 0x%x", __FUNCTION__, |
| 706 | hnd->format); |
| 707 | err = -EINVAL; |
| 708 | } |
| 709 | return err; |
| 710 | |
| 711 | } |
| 712 | |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 713 | |
| 714 | |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 715 | // Allocate buffer from width, height and format into a |
| 716 | // private_handle_t. It is the responsibility of the caller |
| 717 | // to free the buffer using the free_buffer function |
| 718 | int alloc_buffer(private_handle_t **pHnd, int w, int h, int format, int usage) |
| 719 | { |
Naseer Ahmed | 29a2681 | 2012-06-14 00:56:20 -0700 | [diff] [blame] | 720 | alloc_data data; |
| 721 | int alignedw, alignedh; |
Naseer Ahmed | 01d3fd3 | 2012-07-14 21:08:13 -0700 | [diff] [blame] | 722 | gralloc::IAllocController* sAlloc = |
| 723 | gralloc::IAllocController::getInstance(); |
Naseer Ahmed | 29a2681 | 2012-06-14 00:56:20 -0700 | [diff] [blame] | 724 | data.base = 0; |
| 725 | data.fd = -1; |
| 726 | data.offset = 0; |
Manoj Kumar AVM | 8a22081 | 2013-10-10 11:46:06 -0700 | [diff] [blame] | 727 | data.size = getBufferSizeAndDimensions(w, h, format, usage, alignedw, |
| 728 | alignedh); |
| 729 | |
Naseer Ahmed | 29a2681 | 2012-06-14 00:56:20 -0700 | [diff] [blame] | 730 | data.align = getpagesize(); |
| 731 | data.uncached = useUncached(usage); |
| 732 | int allocFlags = usage; |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 733 | |
Naseer Ahmed | 01d3fd3 | 2012-07-14 21:08:13 -0700 | [diff] [blame] | 734 | int err = sAlloc->allocate(data, allocFlags); |
Naseer Ahmed | 29a2681 | 2012-06-14 00:56:20 -0700 | [diff] [blame] | 735 | if (0 != err) { |
| 736 | ALOGE("%s: allocate failed", __FUNCTION__); |
| 737 | return -ENOMEM; |
| 738 | } |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 739 | |
Naseer Ahmed | 29a2681 | 2012-06-14 00:56:20 -0700 | [diff] [blame] | 740 | private_handle_t* hnd = new private_handle_t(data.fd, data.size, |
Naseer Ahmed | 01d3fd3 | 2012-07-14 21:08:13 -0700 | [diff] [blame] | 741 | data.allocType, 0, format, |
| 742 | alignedw, alignedh); |
Saurabh Shah | 8f0ea6f | 2014-05-19 16:48:53 -0700 | [diff] [blame] | 743 | hnd->base = (uint64_t) data.base; |
Naseer Ahmed | 29a2681 | 2012-06-14 00:56:20 -0700 | [diff] [blame] | 744 | hnd->offset = data.offset; |
| 745 | hnd->gpuaddr = 0; |
| 746 | *pHnd = hnd; |
| 747 | return 0; |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 748 | } |
| 749 | |
| 750 | void free_buffer(private_handle_t *hnd) |
| 751 | { |
Naseer Ahmed | 01d3fd3 | 2012-07-14 21:08:13 -0700 | [diff] [blame] | 752 | gralloc::IAllocController* sAlloc = |
| 753 | gralloc::IAllocController::getInstance(); |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 754 | if (hnd && hnd->fd > 0) { |
Naseer Ahmed | 01d3fd3 | 2012-07-14 21:08:13 -0700 | [diff] [blame] | 755 | IMemAlloc* memalloc = sAlloc->getAllocator(hnd->flags); |
Iliyan Malchev | 202a77d | 2012-06-11 14:41:12 -0700 | [diff] [blame] | 756 | memalloc->free_buffer((void*)hnd->base, hnd->size, hnd->offset, hnd->fd); |
| 757 | } |
| 758 | if(hnd) |
| 759 | delete hnd; |
| 760 | |
| 761 | } |
Sushil Chauhan | 65e2630 | 2015-01-14 10:48:57 -0800 | [diff] [blame] | 762 | |
| 763 | // UBWC helper functions |
| 764 | static bool isUBwcFormat(int format) |
| 765 | { |
| 766 | // Explicitly defined UBWC formats |
| 767 | switch(format) |
| 768 | { |
| 769 | case HAL_PIXEL_FORMAT_YCbCr_420_SP_VENUS_UBWC: |
| 770 | return true; |
| 771 | default: |
| 772 | return false; |
| 773 | } |
| 774 | } |
| 775 | |
| 776 | static bool isUBwcSupported(int format) |
| 777 | { |
| 778 | // Existing HAL formats with UBWC support |
| 779 | switch(format) |
| 780 | { |
| 781 | case HAL_PIXEL_FORMAT_RGB_565: |
| 782 | case HAL_PIXEL_FORMAT_RGBA_8888: |
| 783 | case HAL_PIXEL_FORMAT_sRGB_A_8888: |
| 784 | case HAL_PIXEL_FORMAT_NV12_ENCODEABLE: |
| 785 | case HAL_PIXEL_FORMAT_YCbCr_420_SP_VENUS: |
| 786 | return true; |
| 787 | default: |
| 788 | return false; |
| 789 | } |
| 790 | } |
| 791 | |
| 792 | bool isUBwcEnabled(int format, int usage) |
| 793 | { |
Sushil Chauhan | 81594f6 | 2015-01-26 16:00:51 -0800 | [diff] [blame] | 794 | // Allow UBWC, if client is using an explicitly defined UBWC pixel format. |
| 795 | if (isUBwcFormat(format)) |
| 796 | return true; |
| 797 | |
| 798 | // Allow UBWC, if client sets UBWC gralloc usage flag & GPU supports format. |
| 799 | if ((usage & GRALLOC_USAGE_PRIVATE_ALLOC_UBWC) && isUBwcSupported(format) && |
| 800 | AdrenoMemInfo::getInstance().isUBWCSupportedByGPU(format)) { |
| 801 | // Allow UBWC, only if CPU usage flags are not set |
| 802 | if (!(usage & (GRALLOC_USAGE_SW_READ_MASK | |
Sushil Chauhan | 65e2630 | 2015-01-14 10:48:57 -0800 | [diff] [blame] | 803 | GRALLOC_USAGE_SW_WRITE_MASK))) { |
| 804 | return true; |
| 805 | } |
| 806 | } |
| 807 | return false; |
| 808 | } |
| 809 | |
| 810 | static void getUBwcWidthAndHeight(int width, int height, int format, |
| 811 | int& aligned_w, int& aligned_h) |
| 812 | { |
| 813 | switch (format) |
| 814 | { |
| 815 | case HAL_PIXEL_FORMAT_NV12_ENCODEABLE: |
| 816 | case HAL_PIXEL_FORMAT_YCbCr_420_SP_VENUS: |
| 817 | case HAL_PIXEL_FORMAT_YCbCr_420_SP_VENUS_UBWC: |
| 818 | aligned_w = VENUS_Y_STRIDE(COLOR_FMT_NV12_UBWC, width); |
| 819 | aligned_h = VENUS_Y_SCANLINES(COLOR_FMT_NV12_UBWC, height); |
| 820 | break; |
| 821 | default: |
| 822 | ALOGE("%s: Unsupported pixel format: 0x%x", __FUNCTION__, format); |
| 823 | aligned_w = 0; |
| 824 | aligned_h = 0; |
| 825 | break; |
| 826 | } |
| 827 | } |
| 828 | |
| 829 | static void getUBwcBlockSize(int bpp, int& block_width, int& block_height) |
| 830 | { |
| 831 | block_width = 0; |
| 832 | block_height = 0; |
| 833 | |
| 834 | switch(bpp) |
| 835 | { |
| 836 | case 2: |
| 837 | case 4: |
| 838 | block_width = 16; |
| 839 | block_height = 4; |
| 840 | break; |
| 841 | case 8: |
| 842 | block_width = 8; |
| 843 | block_height = 4; |
| 844 | break; |
| 845 | case 16: |
| 846 | block_width = 4; |
| 847 | block_height = 4; |
| 848 | break; |
| 849 | default: |
| 850 | ALOGE("%s: Unsupported bpp: %d", __FUNCTION__, bpp); |
| 851 | break; |
| 852 | } |
| 853 | } |
| 854 | |
| 855 | static unsigned int getUBwcMetaBufferSize(int width, int height, int bpp) |
| 856 | { |
| 857 | unsigned int size = 0; |
| 858 | int meta_width, meta_height; |
| 859 | int block_width, block_height; |
| 860 | |
| 861 | getUBwcBlockSize(bpp, block_width, block_height); |
| 862 | |
| 863 | if (!block_width || !block_height) { |
| 864 | ALOGE("%s: Unsupported bpp: %d", __FUNCTION__, bpp); |
| 865 | return size; |
| 866 | } |
| 867 | |
| 868 | // Align meta buffer height to 16 blocks |
| 869 | meta_height = ALIGN(((height + block_height - 1) / block_height), 16); |
| 870 | |
| 871 | // Align meta buffer width to 64 blocks |
| 872 | meta_width = ALIGN(((width + block_width - 1) / block_width), 64); |
| 873 | |
| 874 | // Align meta buffer size to 4K |
| 875 | size = ((meta_width * meta_height), 4096); |
| 876 | return size; |
| 877 | } |
| 878 | |
| 879 | static unsigned int getUBwcSize(int width, int height, int format, |
| 880 | const int alignedw, const int alignedh) { |
| 881 | |
| 882 | unsigned int size = 0; |
| 883 | switch (format) { |
| 884 | case HAL_PIXEL_FORMAT_RGB_565: |
| 885 | size = alignedw * alignedh * 2; |
| 886 | size += getUBwcMetaBufferSize(width, height, 2); |
| 887 | break; |
| 888 | case HAL_PIXEL_FORMAT_RGBA_8888: |
| 889 | case HAL_PIXEL_FORMAT_sRGB_A_8888: |
| 890 | size = alignedw * alignedh * 4; |
| 891 | size += getUBwcMetaBufferSize(width, height, 4); |
| 892 | break; |
| 893 | case HAL_PIXEL_FORMAT_NV12_ENCODEABLE: |
| 894 | case HAL_PIXEL_FORMAT_YCbCr_420_SP_VENUS: |
| 895 | case HAL_PIXEL_FORMAT_YCbCr_420_SP_VENUS_UBWC: |
| 896 | size = VENUS_BUFFER_SIZE(COLOR_FMT_NV12_UBWC, width, height); |
| 897 | break; |
| 898 | default: |
| 899 | ALOGE("%s: Unsupported pixel format: 0x%x", __FUNCTION__, format); |
| 900 | break; |
| 901 | } |
| 902 | return size; |
| 903 | } |