Blame - compiler/dex/quick/x86/assemble_x86.cc - platform_art

2013-12-20 17:27:23 -0800

[diff] [blame]

180

{ kX86Cmov32RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, {0, 0, 0x0F, 0x40, 0, 0, 0, 0}, "Cmovcc32RR", "!2c !0r,!1r" },

181

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \

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{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \

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{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \

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{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \

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{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }

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SHIFT_ENCODING_MAP(Rol, 0x0),

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SHIFT_ENCODING_MAP(Ror, 0x1),

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SHIFT_ENCODING_MAP(Rcl, 0x2),

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SHIFT_ENCODING_MAP(Rcr, 0x3),

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SHIFT_ENCODING_MAP(Sal, 0x4),

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SHIFT_ENCODING_MAP(Shr, 0x5),

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SHIFT_ENCODING_MAP(Sar, 0x7),

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#undef SHIFT_ENCODING_MAP

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{ kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0}, "Cmc", "" },

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{ kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" },

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{ kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" },

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{ kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" },

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{ kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" },

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{ kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" },

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{ kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" },

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{ kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0}, "Test32RR", "!0r,!1r" },

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#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \

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reg, reg_kind, reg_flags, \

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mem, mem_kind, mem_flags, \

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arr, arr_kind, arr_flags, imm, \

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b_flags, hw_flags, w_flags, \

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b_format, hw_format, w_format) \

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{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, #b_format "!0r" }, \

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{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, #b_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, #b_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, #hw_format "!0r" }, \

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{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, #hw_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, #hw_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, #w_format "!0r" }, \

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{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, #w_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, #w_format "[!0r+!1r<<!2d+!3d]" }

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UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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Mark Mendell

2bf31e6

2014-01-23 12:13:40 -0800

[diff] [blame]

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UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

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UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#undef UNARY_ENCODING_MAP

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Mark Mendell

2bf31e6

2014-01-23 12:13:40 -0800

[diff] [blame]

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{ kx86Cdq32Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { 0, 0, 0x99, 0, 0, 0, 0, 0 }, "Cdq", "" },

Vladimir Marko

a6fd8ba

2013-12-13 10:53:49 +0000

[diff] [blame]

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{ kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0 }, "Bswap32R", "!0r" },

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{ kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0 }, "Push32R", "!0r" },

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{ kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0 }, "Pop32R", "!0r" },

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

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Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \

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{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

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{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

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EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),

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{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

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{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),

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{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

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{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0),

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EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0),

Razvan A Lupusoru

d3266bc

2014-01-24 12:55:31 -0800

[diff] [blame^]

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EXT_0F_ENCODING_MAP(Punpckldq, 0x66, 0x62, REG_DEF0),

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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{ kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" },

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{ kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" },

Mark Mendell

bff1ef0

2013-12-13 13:47:34 -0800

[diff] [blame]

295

{ kX86SqrtsdRR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0xF2, 0, 0x0F, 0x51, 0, 0, 0, 0 }, "SqrtsdRR", "!0r,!1r" },

Vladimir Marko

12f9628

2013-12-16 14:44:03 +0000

[diff] [blame]

296

{ kX86FstpdM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0 }, "FstpdM", "[!0r,!1d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),

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{ kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" },

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{ kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" },

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{ kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

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{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

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{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

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// TODO: load/store?

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// Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.

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{ kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },

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EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES),

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EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES),

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{ kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" },

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{ kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" },

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{ kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

317

{ kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" },

318

{ kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Vladimir Marko

70b797d

2013-12-03 15:25:24 +0000

[diff] [blame]

319

{ kX86LockCmpxchg8bM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1d]" },

320

{ kX86LockCmpxchg8bA, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

321

322

EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),

323

EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),

324

EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),

325

EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),

326

#undef EXT_0F_ENCODING_MAP

327

328

{ kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },

329

{ kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },

330

{ kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },

331

{ kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },

332

{ kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" },

333

{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

334

{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

335

{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

336

{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

Brian Carlstrom

b1eba21

2013-07-17 18:07:19 -0700

[diff] [blame]

337

{ kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

338

339

{ kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" },

340

{ kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },

341

{ kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" },

342

};

343

344

static size_t ComputeSize(const X86EncodingMap* entry, int base, int displacement, bool has_sib) {

345

size_t size = 0;

346

if (entry->skeleton.prefix1 > 0) {

347

++size;

348

if (entry->skeleton.prefix2 > 0) {

++size;

}

}

++size; // opcode

if (entry->skeleton.opcode == 0x0F) {

354

++size;

355

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

if (has_sib || base == rX86_SP) {

361

// SP requires a SIB byte.

362

++size;

363

}

364

if (displacement != 0 || base == rBP) {

365

// BP requires an explicit displacement, even when it's 0.

366

if (entry->opcode != kX86Lea32RA) {

367

DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name;

368

}

369

size += IS_SIMM8(displacement) ? 1 : 4;

370

}

371

size += entry->skeleton.immediate_bytes;

return size;

}

int X86Mir2Lir::GetInsnSize(LIR* lir) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

376

DCHECK(!IsPseudoLirOp(lir->opcode));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

377

const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode];

378

switch (entry->kind) {

379

case kData:

380

return 4; // 4 bytes of data

381

case kNop:

382

return lir->operands[0]; // length of nop is sole operand

383

case kNullary:

384

return 1; // 1 byte of opcode

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

385

case kRegOpcode: // lir operands - 0: reg

386

return ComputeSize(entry, 0, 0, false) - 1; // substract 1 for modrm

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

387

case kReg: // lir operands - 0: reg

388

return ComputeSize(entry, 0, 0, false);

389

case kMem: // lir operands - 0: base, 1: disp

390

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

391

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

392

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

393

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

394

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

395

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

396

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

397

case kThreadReg: // lir operands - 0: disp, 1: reg

398

return ComputeSize(entry, 0, lir->operands[0], false);

399

case kRegReg:

400

return ComputeSize(entry, 0, 0, false);

401

case kRegRegStore:

402

return ComputeSize(entry, 0, 0, false);

403

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

404

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

405

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

406

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

407

case kRegThread: // lir operands - 0: reg, 1: disp

408

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

409

case kRegImm: { // lir operands - 0: reg, 1: immediate

410

size_t size = ComputeSize(entry, 0, 0, false);

411

if (entry->skeleton.ax_opcode == 0) {

412

return size;

413

} else {

414

// AX opcodes don't require the modrm byte.

415

int reg = lir->operands[0];

416

return size - (reg == rAX ? 1 : 0);

417

}

418

}

419

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

420

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

421

case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

422

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

423

case kThreadImm: // lir operands - 0: disp, 1: imm

424

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

425

case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

426

return ComputeSize(entry, 0, 0, false);

427

case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

428

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

429

case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

430

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

431

case kMovRegImm: // lir operands - 0: reg, 1: immediate

432

return 1 + entry->skeleton.immediate_bytes;

433

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

434

// Shift by immediate one has a shorter opcode.

435

return ComputeSize(entry, 0, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

436

case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

437

// Shift by immediate one has a shorter opcode.

438

return ComputeSize(entry, lir->operands[0], lir->operands[1], false) -

439

(lir->operands[2] == 1 ? 1 : 0);

440

case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

441

// Shift by immediate one has a shorter opcode.

442

return ComputeSize(entry, lir->operands[0], lir->operands[3], true) -

443

(lir->operands[4] == 1 ? 1 : 0);

444

case kShiftRegCl:

445

return ComputeSize(entry, 0, 0, false);

446

case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

447

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

448

case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

449

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

450

case kRegCond: // lir operands - 0: reg, 1: cond

451

return ComputeSize(entry, 0, 0, false);

452

case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

453

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

454

case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

455

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

456

case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: cond

457

return ComputeSize(entry, 0, 0, false);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

458

case kJcc:

459

if (lir->opcode == kX86Jcc8) {

460

return 2; // opcode + rel8

461

} else {

462

DCHECK(lir->opcode == kX86Jcc32);

463

return 6; // 2 byte opcode + rel32

464

}

465

case kJmp:

466

if (lir->opcode == kX86Jmp8) {

467

return 2; // opcode + rel8

468

} else if (lir->opcode == kX86Jmp32) {

469

return 5; // opcode + rel32

470

} else {

471

DCHECK(lir->opcode == kX86JmpR);

472

return 2; // opcode + modrm

473

}

474

case kCall:

475

switch (lir->opcode) {

476

case kX86CallR: return 2; // opcode modrm

477

case kX86CallM: // lir operands - 0: base, 1: disp

478

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

479

case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

480

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

481

case kX86CallT: // lir operands - 0: disp

482

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

default:

break;

}

break;

case kPcRel:

if (entry->opcode == kX86PcRelLoadRA) {

489

// lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

490

return ComputeSize(entry, lir->operands[1], 0x12345678, true);

491

} else {

492

DCHECK(entry->opcode == kX86PcRelAdr);

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

493

return 5; // opcode with reg + 4 byte immediate

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

494

}

495

case kMacro:

496

DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));

497

return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +

498

ComputeSize(&X86Mir2Lir::EncodingMap[kX86Sub32RI], 0, 0, false) -

499

(lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

return 0;

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

507

void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry) {

508

if (entry->skeleton.prefix1 != 0) {

509

code_buffer_.push_back(entry->skeleton.prefix1);

510

if (entry->skeleton.prefix2 != 0) {

511

code_buffer_.push_back(entry->skeleton.prefix2);

512

}

513

} else {

514

DCHECK_EQ(0, entry->skeleton.prefix2);

}

}

void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) {

519

code_buffer_.push_back(entry->skeleton.opcode);

520

if (entry->skeleton.opcode == 0x0F) {

521

code_buffer_.push_back(entry->skeleton.extra_opcode1);

522

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

523

code_buffer_.push_back(entry->skeleton.extra_opcode2);

524

} else {

525

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

526

}

527

} else {

528

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

529

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

}

}

void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry) {

EmitPrefix(entry);

EmitOpcode(entry);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

538

static uint8_t ModrmForDisp(int base, int disp) {

539

// BP requires an explicit disp, so do not omit it in the 0 case

540

if (disp == 0 && base != rBP) {

541

return 0;

542

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

549

void X86Mir2Lir::EmitDisp(uint8_t base, int disp) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

550

// BP requires an explicit disp, so do not omit it in the 0 case

551

if (disp == 0 && base != rBP) {

552

return;

553

} else if (IS_SIMM8(disp)) {

554

code_buffer_.push_back(disp & 0xFF);

555

} else {

556

code_buffer_.push_back(disp & 0xFF);

557

code_buffer_.push_back((disp >> 8) & 0xFF);

558

code_buffer_.push_back((disp >> 16) & 0xFF);

559

code_buffer_.push_back((disp >> 24) & 0xFF);

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

563

void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp) {

564

DCHECK_LT(reg_or_opcode, 8);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

565

DCHECK_LT(base, 8);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

566

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | base;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

567

code_buffer_.push_back(modrm);

568

if (base == rX86_SP) {

569

// Special SIB for SP base

570

code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);

571

}

572

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

573

}

574

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

575

void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index,

576

int scale, int disp) {

577

DCHECK_LT(reg_or_opcode, 8);

578

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | rX86_SP;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

579

code_buffer_.push_back(modrm);

DCHECK_LT(scale, 4);

DCHECK_LT(index, 8);

DCHECK_LT(base, 8);

uint8_t sib = (scale << 6) | (index << 3) | base;

584

code_buffer_.push_back(sib);

585

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

586

}

587

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

588

void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int imm) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

589

switch (entry->skeleton.immediate_bytes) {

590

case 1:

591

DCHECK(IS_SIMM8(imm));

592

code_buffer_.push_back(imm & 0xFF);

593

break;

594

case 2:

595

DCHECK(IS_SIMM16(imm));

596

code_buffer_.push_back(imm & 0xFF);

597

code_buffer_.push_back((imm >> 8) & 0xFF);

598

break;

599

case 4:

600

code_buffer_.push_back(imm & 0xFF);

601

code_buffer_.push_back((imm >> 8) & 0xFF);

602

code_buffer_.push_back((imm >> 16) & 0xFF);

603

code_buffer_.push_back((imm >> 24) & 0xFF);

604

break;

605

default:

606

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

607

<< ") for instruction: " << entry->name;

break;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

612

void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg) {

613

EmitPrefixAndOpcode(entry);

614

// There's no 3-byte instruction with +rd

615

DCHECK(entry->skeleton.opcode != 0x0F ||

616

(entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A));

617

DCHECK(!X86_FPREG(reg));

618

DCHECK_LT(reg, 8);

619

code_buffer_.back() += reg;

620

DCHECK_EQ(0, entry->skeleton.ax_opcode);

621

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

622

}

623

624

void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) {

625

EmitPrefixAndOpcode(entry);

626

if (X86_FPREG(reg)) {

627

reg = reg & X86_FP_REG_MASK;

628

}

629

if (reg >= 4) {

630

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

631

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

632

}

633

DCHECK_LT(reg, 8);

634

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

635

code_buffer_.push_back(modrm);

636

DCHECK_EQ(0, entry->skeleton.ax_opcode);

637

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

638

}

639

640

void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) {

641

EmitPrefix(entry);

642

code_buffer_.push_back(entry->skeleton.opcode);

643

DCHECK_NE(0x0F, entry->skeleton.opcode);

644

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

645

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

646

DCHECK_NE(rX86_SP, base);

647

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

648

DCHECK_EQ(0, entry->skeleton.ax_opcode);

649

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

650

}

651

652

void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index,

653

int scale, int disp) {

654

EmitPrefixAndOpcode(entry);

655

EmitModrmSibDisp(entry->skeleton.modrm_opcode, base, index, scale, disp);

656

DCHECK_EQ(0, entry->skeleton.ax_opcode);

657

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

658

}

659

660

void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry,

661

uint8_t base, int disp, uint8_t reg) {

662

EmitPrefixAndOpcode(entry);

663

if (X86_FPREG(reg)) {

664

reg = reg & X86_FP_REG_MASK;

665

}

666

if (reg >= 4) {

667

DCHECK(strchr(entry->name, '8') == NULL ||

668

entry->opcode == kX86Movzx8RM || entry->opcode == kX86Movsx8RM)

669

<< entry->name << " " << static_cast<int>(reg)

670

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

671

}

672

EmitModrmDisp(reg, base, disp);

673

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

674

DCHECK_EQ(0, entry->skeleton.ax_opcode);

675

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

676

}

677

678

void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry,

679

uint8_t reg, uint8_t base, int disp) {

680

// Opcode will flip operands.

681

EmitMemReg(entry, base, disp, reg);

682

}

683

684

void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index,

685

int scale, int disp) {

686

EmitPrefixAndOpcode(entry);

687

if (X86_FPREG(reg)) {

688

reg = reg & X86_FP_REG_MASK;

689

}

690

EmitModrmSibDisp(reg, base, index, scale, disp);

691

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

692

DCHECK_EQ(0, entry->skeleton.ax_opcode);

693

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

694

}

695

696

void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp,

697

uint8_t reg) {

698

// Opcode will flip operands.

699

EmitRegArray(entry, reg, base, index, scale, disp);

700

}

701

702

void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) {

703

DCHECK_NE(entry->skeleton.prefix1, 0);

704

EmitPrefixAndOpcode(entry);

705

if (X86_FPREG(reg)) {

706

reg = reg & X86_FP_REG_MASK;

707

}

708

if (reg >= 4) {

709

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

710

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

711

}

712

DCHECK_LT(reg, 8);

713

uint8_t modrm = (0 << 6) | (reg << 3) | rBP;

714

code_buffer_.push_back(modrm);

715

code_buffer_.push_back(disp & 0xFF);

716

code_buffer_.push_back((disp >> 8) & 0xFF);

717

code_buffer_.push_back((disp >> 16) & 0xFF);

718

code_buffer_.push_back((disp >> 24) & 0xFF);

719

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

720

DCHECK_EQ(0, entry->skeleton.ax_opcode);

721

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

722

}

723

724

void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) {

725

EmitPrefixAndOpcode(entry);

726

if (X86_FPREG(reg1)) {

727

reg1 = reg1 & X86_FP_REG_MASK;

728

}

729

if (X86_FPREG(reg2)) {

730

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

735

code_buffer_.push_back(modrm);

736

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

737

DCHECK_EQ(0, entry->skeleton.ax_opcode);

738

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

739

}

740

741

void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry,

742

uint8_t reg1, uint8_t reg2, int32_t imm) {

743

EmitPrefixAndOpcode(entry);

744

if (X86_FPREG(reg1)) {

745

reg1 = reg1 & X86_FP_REG_MASK;

746

}

747

if (X86_FPREG(reg2)) {

748

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

753

code_buffer_.push_back(modrm);

754

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

755

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

759

void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

760

if (entry->skeleton.prefix1 != 0) {

761

code_buffer_.push_back(entry->skeleton.prefix1);

762

if (entry->skeleton.prefix2 != 0) {

763

code_buffer_.push_back(entry->skeleton.prefix2);

764

}

765

} else {

766

DCHECK_EQ(0, entry->skeleton.prefix2);

767

}

768

if (reg == rAX && entry->skeleton.ax_opcode != 0) {

769

code_buffer_.push_back(entry->skeleton.ax_opcode);

770

} else {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

771

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

772

if (X86_FPREG(reg)) {

773

reg = reg & X86_FP_REG_MASK;

774

}

775

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

776

code_buffer_.push_back(modrm);

777

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

778

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

779

}

780

Mark Mendell

343adb5

2013-12-18 06:02:17 -0800

[diff] [blame]

781

void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm) {

782

EmitPrefixAndOpcode(entry);

783

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

784

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

788

void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

789

EmitPrefixAndOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

790

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

791

code_buffer_.push_back(modrm);

792

code_buffer_.push_back(disp & 0xFF);

793

code_buffer_.push_back((disp >> 8) & 0xFF);

794

code_buffer_.push_back((disp >> 16) & 0xFF);

795

code_buffer_.push_back((disp >> 24) & 0xFF);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

796

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

797

DCHECK_EQ(entry->skeleton.ax_opcode, 0);

798

}

799

800

void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

801

DCHECK_LT(reg, 8);

802

code_buffer_.push_back(0xB8 + reg);

803

code_buffer_.push_back(imm & 0xFF);

804

code_buffer_.push_back((imm >> 8) & 0xFF);

805

code_buffer_.push_back((imm >> 16) & 0xFF);

806

code_buffer_.push_back((imm >> 24) & 0xFF);

807

}

808

809

void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

810

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

811

if (imm != 1) {

812

code_buffer_.push_back(entry->skeleton.opcode);

813

} else {

814

// Shorter encoding for 1 bit shift

815

code_buffer_.push_back(entry->skeleton.ax_opcode);

816

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

817

DCHECK_NE(0x0F, entry->skeleton.opcode);

818

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

819

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

820

if (reg >= 4) {

821

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

822

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

823

}

824

DCHECK_LT(reg, 8);

825

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

826

code_buffer_.push_back(modrm);

827

if (imm != 1) {

828

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

829

DCHECK(IS_SIMM8(imm));

830

code_buffer_.push_back(imm & 0xFF);

}

}

void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl) {

835

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

836

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

837

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

838

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

839

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

840

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

841

DCHECK_LT(reg, 8);

842

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

843

code_buffer_.push_back(modrm);

844

DCHECK_EQ(0, entry->skeleton.ax_opcode);

845

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

846

}

847

848

void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) {

849

if (entry->skeleton.prefix1 != 0) {

850

code_buffer_.push_back(entry->skeleton.prefix1);

851

if (entry->skeleton.prefix2 != 0) {

852

code_buffer_.push_back(entry->skeleton.prefix2);

853

}

854

} else {

855

DCHECK_EQ(0, entry->skeleton.prefix2);

856

}

857

DCHECK_EQ(0, entry->skeleton.ax_opcode);

858

DCHECK_EQ(0x0F, entry->skeleton.opcode);

859

code_buffer_.push_back(0x0F);

860

DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);

861

code_buffer_.push_back(0x90 | condition);

862

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

863

DCHECK_LT(reg, 8);

864

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

865

code_buffer_.push_back(modrm);

866

DCHECK_EQ(entry->skeleton.immediate_bytes, 0);

867

}

868

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

869

void X86Mir2Lir::EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, uint8_t condition) {

870

// Generate prefix and opcode without the condition

871

EmitPrefixAndOpcode(entry);

872

873

// Now add the condition. The last byte of opcode is the one that receives it.

874

DCHECK_LE(condition, 0xF);

875

code_buffer_.back() += condition;

876

877

// Not expecting to have to encode immediate or do anything special for ModR/M since there are two registers.

878

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

879

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

880

881

// Check that registers requested for encoding are sane.

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

// For register to register encoding, the mod is 3.

886

const uint8_t mod = (3 << 6);

887

888

// Encode the ModR/M byte now.

889

const uint8_t modrm = mod | (reg1 << 3) | reg2;

890

code_buffer_.push_back(modrm);

891

}

892

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

893

void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int rel) {

894

if (entry->opcode == kX86Jmp8) {

895

DCHECK(IS_SIMM8(rel));

896

code_buffer_.push_back(0xEB);

897

code_buffer_.push_back(rel & 0xFF);

898

} else if (entry->opcode == kX86Jmp32) {

899

code_buffer_.push_back(0xE9);

900

code_buffer_.push_back(rel & 0xFF);

901

code_buffer_.push_back((rel >> 8) & 0xFF);

902

code_buffer_.push_back((rel >> 16) & 0xFF);

903

code_buffer_.push_back((rel >> 24) & 0xFF);

904

} else {

905

DCHECK(entry->opcode == kX86JmpR);

906

code_buffer_.push_back(entry->skeleton.opcode);

907

uint8_t reg = static_cast<uint8_t>(rel);

908

DCHECK_LT(reg, 8);

909

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

910

code_buffer_.push_back(modrm);

}

}

void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc) {

915

DCHECK_LT(cc, 16);

916

if (entry->opcode == kX86Jcc8) {

917

DCHECK(IS_SIMM8(rel));

918

code_buffer_.push_back(0x70 | cc);

919

code_buffer_.push_back(rel & 0xFF);

920

} else {

921

DCHECK(entry->opcode == kX86Jcc32);

922

code_buffer_.push_back(0x0F);

923

code_buffer_.push_back(0x80 | cc);

924

code_buffer_.push_back(rel & 0xFF);

925

code_buffer_.push_back((rel >> 8) & 0xFF);

926

code_buffer_.push_back((rel >> 16) & 0xFF);

927

code_buffer_.push_back((rel >> 24) & 0xFF);

}

}

void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

932

EmitPrefixAndOpcode(entry);

933

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

934

DCHECK_EQ(0, entry->skeleton.ax_opcode);

935

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

936

}

937

938

void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int disp) {

939

DCHECK_NE(entry->skeleton.prefix1, 0);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

940

EmitPrefixAndOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

941

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

942

code_buffer_.push_back(modrm);

943

code_buffer_.push_back(disp & 0xFF);

944

code_buffer_.push_back((disp >> 8) & 0xFF);

945

code_buffer_.push_back((disp >> 16) & 0xFF);

946

code_buffer_.push_back((disp >> 24) & 0xFF);

947

DCHECK_EQ(0, entry->skeleton.ax_opcode);

948

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

949

}

950

951

void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, uint8_t reg,

952

int base_or_table, uint8_t index, int scale, int table_or_disp) {

953

int disp;

954

if (entry->opcode == kX86PcRelLoadRA) {

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

955

Mir2Lir::EmbeddedData *tab_rec =

956

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

957

disp = tab_rec->offset;

958

} else {

959

DCHECK(entry->opcode == kX86PcRelAdr);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

960

Mir2Lir::EmbeddedData *tab_rec =

961

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(base_or_table));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

962

disp = tab_rec->offset;

963

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

964

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

965

if (X86_FPREG(reg)) {

966

reg = reg & X86_FP_REG_MASK;

967

}

968

DCHECK_LT(reg, 8);

969

if (entry->opcode == kX86PcRelLoadRA) {

970

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

971

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

972

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

973

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

974

uint8_t modrm = (2 << 6) | (reg << 3) | rX86_SP;

975

code_buffer_.push_back(modrm);

976

DCHECK_LT(scale, 4);

977

DCHECK_LT(index, 8);

978

DCHECK_LT(base_or_table, 8);

979

uint8_t base = static_cast<uint8_t>(base_or_table);

980

uint8_t sib = (scale << 6) | (index << 3) | base;

981

code_buffer_.push_back(sib);

982

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

983

} else {

984

code_buffer_.push_back(entry->skeleton.opcode + reg);

985

}

986

code_buffer_.push_back(disp & 0xFF);

987

code_buffer_.push_back((disp >> 8) & 0xFF);

988

code_buffer_.push_back((disp >> 16) & 0xFF);

989

code_buffer_.push_back((disp >> 24) & 0xFF);

990

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

991

DCHECK_EQ(0, entry->skeleton.ax_opcode);

992

}

993

994

void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset) {

995

DCHECK(entry->opcode == kX86StartOfMethod) << entry->name;

996

code_buffer_.push_back(0xE8); // call +0

997

code_buffer_.push_back(0);

998

code_buffer_.push_back(0);

999

code_buffer_.push_back(0);

1000

code_buffer_.push_back(0);

1001

1002

DCHECK_LT(reg, 8);

1003

code_buffer_.push_back(0x58 + reg); // pop reg

1004

1005

EmitRegImm(&X86Mir2Lir::EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */);

1006

}

1007

1008

void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) {

1009

UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " "

1010

<< BuildInsnString(entry->fmt, lir, 0);

1011

for (int i = 0; i < GetInsnSize(lir); ++i) {

1012

code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3

}

}

/*

* Assemble the LIR into binary instruction format. Note that we may

1018

* discover that pc-relative displacements may not fit the selected

1019

* instruction. In those cases we will try to substitute a new code

1020

* sequence or request that the trace be shortened and retried.

1021

*/

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1022

AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1023

LIR *lir;

1024

AssemblerStatus res = kSuccess; // Assume success

1025

1026

const bool kVerbosePcFixup = false;

1027

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1028

if (IsPseudoLirOp(lir->opcode)) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

continue;

}

if (lir->flags.is_nop) {

continue;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1036

if (lir->flags.fixup != kFixupNone) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1037

switch (lir->opcode) {

1038

case kX86Jcc8: {

1039

LIR *target_lir = lir->target;

1040

DCHECK(target_lir != NULL);

1041

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1042

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1043

if (IS_SIMM8(lir->operands[0])) {

1044

pc = lir->offset + 2 /* opcode + rel8 */;

1045

} else {

1046

pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1047

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1048

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1049

delta = target - pc;

1050

if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1051

if (kVerbosePcFixup) {

1052

LOG(INFO) << "Retry for JCC growth at " << lir->offset

1053

<< " delta: " << delta << " old delta: " << lir->operands[0];

1054

}

1055

lir->opcode = kX86Jcc32;

1056

SetupResourceMasks(lir);

1057

res = kRetryAll;

1058

}

1059

if (kVerbosePcFixup) {

1060

LOG(INFO) << "Source:";

1061

DumpLIRInsn(lir, 0);

1062

LOG(INFO) << "Target:";

1063

DumpLIRInsn(target_lir, 0);

1064

LOG(INFO) << "Delta " << delta;

1065

}

1066

lir->operands[0] = delta;

break;

}

case kX86Jcc32: {

LIR *target_lir = lir->target;

1071

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1072

CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1073

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1074

int delta = target - pc;

1075

if (kVerbosePcFixup) {

1076

LOG(INFO) << "Source:";

1077

DumpLIRInsn(lir, 0);

1078

LOG(INFO) << "Target:";

1079

DumpLIRInsn(target_lir, 0);

1080

LOG(INFO) << "Delta " << delta;

1081

}

1082

lir->operands[0] = delta;

break;

}

case kX86Jmp8: {

LIR *target_lir = lir->target;

1087

DCHECK(target_lir != NULL);

1088

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1089

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1090

if (IS_SIMM8(lir->operands[0])) {

1091

pc = lir->offset + 2 /* opcode + rel8 */;

1092

} else {

1093

pc = lir->offset + 5 /* opcode + rel32 */;

1094

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1095

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1096

delta = target - pc;

1097

if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) {

1098

// Useless branch

buzbee

252254b

2013-09-08 16:20:53 -0700

[diff] [blame]

1099

NopLIR(lir);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1100

if (kVerbosePcFixup) {

1101

LOG(INFO) << "Retry for useless branch at " << lir->offset;

1102

}

1103

res = kRetryAll;

1104

} else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1105

if (kVerbosePcFixup) {

1106

LOG(INFO) << "Retry for JMP growth at " << lir->offset;

1107

}

1108

lir->opcode = kX86Jmp32;

1109

SetupResourceMasks(lir);

1110

res = kRetryAll;

1111

}

1112

lir->operands[0] = delta;

break;

}

case kX86Jmp32: {

LIR *target_lir = lir->target;

1117

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1118

CodeOffset pc = lir->offset + 5 /* opcode + rel32 */;

1119

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1120

int delta = target - pc;

1121

lir->operands[0] = delta;

break;

}

default:

break;

}

}

/*

* If one of the pc-relative instructions expanded we'll have

1131

* to make another pass. Don't bother to fully assemble the

1132

* instruction.

1133

*/

1134

if (res != kSuccess) {

1135

continue;

1136

}

1137

CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size());

1138

const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode];

1139

size_t starting_cbuf_size = code_buffer_.size();

1140

switch (entry->kind) {

1141

case kData: // 4 bytes of data

1142

code_buffer_.push_back(lir->operands[0]);

1143

break;

1144

case kNullary: // 1 byte of opcode

1145

DCHECK_EQ(0, entry->skeleton.prefix1);

1146

DCHECK_EQ(0, entry->skeleton.prefix2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1147

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1148

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1149

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1150

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1151

break;

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

1152

case kRegOpcode: // lir operands - 0: reg

1153

EmitOpRegOpcode(entry, lir->operands[0]);

1154

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1155

case kReg: // lir operands - 0: reg

1156

EmitOpReg(entry, lir->operands[0]);

1157

break;

1158

case kMem: // lir operands - 0: base, 1: disp

1159

EmitOpMem(entry, lir->operands[0], lir->operands[1]);

1160

break;

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1161

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

1162

EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]);

1163

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1164

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

1165

EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1166

break;

Mark Mendell

343adb5

2013-12-18 06:02:17 -0800

[diff] [blame]

1167

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

1168

EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1169

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1170

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

1171

EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1172

lir->operands[3], lir->operands[4]);

1173

break;

1174

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

1175

EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1176

break;

1177

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

1178

EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1179

lir->operands[3], lir->operands[4]);

1180

break;

1181

case kRegThread: // lir operands - 0: reg, 1: disp

1182

EmitRegThread(entry, lir->operands[0], lir->operands[1]);

1183

break;

1184

case kRegReg: // lir operands - 0: reg1, 1: reg2

1185

EmitRegReg(entry, lir->operands[0], lir->operands[1]);

1186

break;

1187

case kRegRegStore: // lir operands - 0: reg2, 1: reg1

1188

EmitRegReg(entry, lir->operands[1], lir->operands[0]);

1189

break;

1190

case kRegRegImm:

1191

EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1192

break;

1193

case kRegImm: // lir operands - 0: reg, 1: immediate

1194

EmitRegImm(entry, lir->operands[0], lir->operands[1]);

1195

break;

1196

case kThreadImm: // lir operands - 0: disp, 1: immediate

1197

EmitThreadImm(entry, lir->operands[0], lir->operands[1]);

1198

break;

1199

case kMovRegImm: // lir operands - 0: reg, 1: immediate

1200

EmitMovRegImm(entry, lir->operands[0], lir->operands[1]);

1201

break;

1202

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

1203

EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]);

1204

break;

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

1205

case kShiftRegCl: // lir operands - 0: reg, 1: cl

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1206

EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]);

1207

break;

1208

case kRegCond: // lir operands - 0: reg, 1: condition

1209

EmitRegCond(entry, lir->operands[0], lir->operands[1]);

1210

break;

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

1211

case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: condition

1212

EmitRegRegCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1213

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1214

case kJmp: // lir operands - 0: rel

1215

EmitJmp(entry, lir->operands[0]);

1216

break;

1217

case kJcc: // lir operands - 0: rel, 1: CC, target assigned

1218

EmitJcc(entry, lir->operands[0], lir->operands[1]);

1219

break;

1220

case kCall:

1221

switch (entry->opcode) {

1222

case kX86CallM: // lir operands - 0: base, 1: disp

1223

EmitCallMem(entry, lir->operands[0], lir->operands[1]);

1224

break;

1225

case kX86CallT: // lir operands - 0: disp

1226

EmitCallThread(entry, lir->operands[0]);

1227

break;

1228

default:

1229

EmitUnimplemented(entry, lir);

break;

}

break;

case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

1234

EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1235

lir->operands[3], lir->operands[4]);

1236

break;

1237

case kMacro:

1238

EmitMacro(entry, lir->operands[0], lir->offset);

1239

break;

1240

default:

1241

EmitUnimplemented(entry, lir);

1242

break;

1243

}

1244

CHECK_EQ(static_cast<size_t>(GetInsnSize(lir)),

1245

code_buffer_.size() - starting_cbuf_size)

1246

<< "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name;

}

return res;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1251

// LIR offset assignment.

1252

// TODO: consolidate w/ Arm assembly mechanism.

1253

int X86Mir2Lir::AssignInsnOffsets() {

LIR* lir;

int offset = 0;

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

1258

lir->offset = offset;

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1259

if (LIKELY(!IsPseudoLirOp(lir->opcode))) {

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1260

if (!lir->flags.is_nop) {

1261

offset += lir->flags.size;

1262

}

1263

} else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) {

1264

if (offset & 0x2) {

1265

offset += 2;

1266

lir->operands[0] = 1;

1267

} else {

1268

lir->operands[0] = 0;

1269

}

1270

}

1271

/* Pseudo opcodes don't consume space */

}

return offset;

}

/*

* Walk the compilation unit and assign offsets to instructions

1278

* and literals and compute the total size of the compiled unit.

1279

* TODO: consolidate w/ Arm assembly mechanism.

1280

*/

1281

void X86Mir2Lir::AssignOffsets() {

1282

int offset = AssignInsnOffsets();

1283

1284

/* Const values have to be word aligned */

1285

offset = (offset + 3) & ~3;

1286

1287

/* Set up offsets for literals */

1288

data_offset_ = offset;

1289

1290

offset = AssignLiteralOffset(offset);

1291

1292

offset = AssignSwitchTablesOffset(offset);

1293

1294

offset = AssignFillArrayDataOffset(offset);

1295

1296

total_size_ = offset;

}

/*

* Go over each instruction in the list and calculate the offset from the top

1301

* before sending them off to the assembler. If out-of-range branch distance is

1302

* seen rearrange the instructions a bit to correct it.

1303

* TODO: consolidate w/ Arm assembly mechanism.

1304

*/

1305

void X86Mir2Lir::AssembleLIR() {

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1306

cu_->NewTimingSplit("Assemble");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1307

AssignOffsets();

1308

int assembler_retries = 0;

1309

/*

1310

* Assemble here. Note that we generate code with optimistic assumptions

1311

* and if found now to work, we'll have to redo the sequence and retry.

*/

while (true) {

AssemblerStatus res = AssembleInstructions(0);

1316

if (res == kSuccess) {

break;

} else {

assembler_retries++;

if (assembler_retries > MAX_ASSEMBLER_RETRIES) {

1321

CodegenDump();

1322

LOG(FATAL) << "Assembler error - too many retries";

1323

}

1324

// Redo offsets and try again

1325

AssignOffsets();

1326

code_buffer_.clear();

}

}

// Install literals

InstallLiteralPools();

1332

1333

// Install switch tables

1334

InstallSwitchTables();

1335

1336

// Install fill array data

1337

InstallFillArrayData();

1338

1339

// Create the mapping table and native offset to reference map.

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1340

cu_->NewTimingSplit("PcMappingTable");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1341

CreateMappingTables();

1342

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1343

cu_->NewTimingSplit("GcMap");

buzbee