Blame - compiler/dex/quick/x86/assemble_x86.cc - platform_art

2014-02-19 20:06:20 -0800

[diff] [blame]

178

{ kX86Lea32RM, kRegMem, IS_TERTIARY_OP | IS_LOAD | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RM", "!0r,[!1r+!2d]" },

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Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

180

{ kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

182

{ kX86Cmov32RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, {0, 0, 0x0F, 0x40, 0, 0, 0, 0}, "Cmovcc32RR", "!2c !0r,!1r" },

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Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \

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{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \

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{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \

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{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \

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{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }

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SHIFT_ENCODING_MAP(Rol, 0x0),

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SHIFT_ENCODING_MAP(Ror, 0x1),

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SHIFT_ENCODING_MAP(Rcl, 0x2),

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SHIFT_ENCODING_MAP(Rcr, 0x3),

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SHIFT_ENCODING_MAP(Sal, 0x4),

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SHIFT_ENCODING_MAP(Shr, 0x5),

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SHIFT_ENCODING_MAP(Sar, 0x7),

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#undef SHIFT_ENCODING_MAP

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{ kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0}, "Cmc", "" },

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

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{ kX86Shld32RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1}, "Shld32", "!0r,!1r,!2d" },

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{ kX86Shrd32RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1}, "Shrd32", "!0r,!1r,!2d" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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{ kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" },

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{ kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" },

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{ kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" },

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{ kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" },

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{ kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" },

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{ kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" },

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{ kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0}, "Test32RR", "!0r,!1r" },

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#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \

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reg, reg_kind, reg_flags, \

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mem, mem_kind, mem_flags, \

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arr, arr_kind, arr_flags, imm, \

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b_flags, hw_flags, w_flags, \

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b_format, hw_format, w_format) \

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{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, #b_format "!0r" }, \

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{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, #b_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, #b_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, #hw_format "!0r" }, \

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{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, #hw_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, #hw_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, #w_format "!0r" }, \

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{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, #w_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, #w_format "[!0r+!1r<<!2d+!3d]" }

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UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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Mark Mendell

2bf31e6

2014-01-23 12:13:40 -0800

[diff] [blame]

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UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

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UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

Brian Carlstrom

2013-07-12 13:46:57 -0700

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#undef UNARY_ENCODING_MAP

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Mark Mendell

2bf31e6

2014-01-23 12:13:40 -0800

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{ kx86Cdq32Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { 0, 0, 0x99, 0, 0, 0, 0, 0 }, "Cdq", "" },

Vladimir Marko

a6fd8ba

2013-12-13 10:53:49 +0000

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{ kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0 }, "Bswap32R", "!0r" },

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{ kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0 }, "Push32R", "!0r" },

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{ kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0 }, "Pop32R", "!0r" },

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

259

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \

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{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

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{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

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EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),

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{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

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{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),

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{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

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{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0),

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EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0),

Razvan A Lupusoru

d3266bc

2014-01-24 12:55:31 -0800

[diff] [blame]

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EXT_0F_ENCODING_MAP(Punpckldq, 0x66, 0x62, REG_DEF0),

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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{ kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" },

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{ kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" },

Mark Mendell

bff1ef0

2013-12-13 13:47:34 -0800

[diff] [blame]

299

{ kX86SqrtsdRR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0xF2, 0, 0x0F, 0x51, 0, 0, 0, 0 }, "SqrtsdRR", "!0r,!1r" },

Razvan A Lupusoru

614c2b4

2014-01-28 17:05:21 -0800

[diff] [blame]

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Serguei Katkov

e90501d

2014-03-12 15:56:54 +0700

[diff] [blame]

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{ kX86Fild32M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDB, 0x00, 0, 0, 0, 0 }, "Fild32M", "[!0r,!1d]" },

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{ kX86Fild64M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDF, 0x00, 0, 5, 0, 0 }, "Fild64M", "[!0r,!1d]" },

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{ kX86Fstp32M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 3, 0, 0 }, "FstpsM", "[!0r,!1d]" },

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{ kX86Fstp64M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0 }, "FstpdM", "[!0r,!1d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

305

Razvan A Lupusoru

2c498d1

2014-01-29 16:02:57 -0800

[diff] [blame]

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EXT_0F_ENCODING_MAP(Movups, 0x0, 0x10, REG_DEF0),

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{ kX86MovupsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovupsMR", "[!0r+!1d],!2r" },

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{ kX86MovupsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovupsAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movaps, 0x0, 0x28, REG_DEF0),

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{ kX86MovapsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0 }, "MovapsMR", "[!0r+!1d],!2r" },

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{ kX86MovapsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0 }, "MovapsAR", "[!0r+!1r<<!2d+!3d],!4r" },

313

314

{ kX86MovlpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0 }, "MovlpsRM", "!0r,[!1r+!2d]" },

315

{ kX86MovlpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0 }, "MovlpsRA", "!0r,[!1r+!2r<<!3d+!4d]" },

316

{ kX86MovlpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0 }, "MovlpsMR", "[!0r+!1d],!2r" },

317

{ kX86MovlpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0 }, "MovlpsAR", "[!0r+!1r<<!2d+!3d],!4r" },

318

319

{ kX86MovhpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0 }, "MovhpsRM", "!0r,[!1r+!2d]" },

320

{ kX86MovhpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0 }, "MovhpsRA", "!0r,[!1r+!2r<<!3d+!4d]" },

321

{ kX86MovhpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0 }, "MovhpsMR", "[!0r+!1d],!2r" },

322

{ kX86MovhpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0 }, "MovhpsAR", "[!0r+!1r<<!2d+!3d],!4r" },

323

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

324

EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),

325

{ kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" },

326

{ kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" },

327

{ kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },

328

329

{ kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

330

{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

331

{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

332

333

// TODO: load/store?

334

// Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.

335

{ kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },

336

337

EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES),

338

EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES),

339

340

{ kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" },

341

{ kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" },

342

{ kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

343

{ kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" },

344

{ kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Vladimir Marko

70b797d

2013-12-03 15:25:24 +0000

[diff] [blame]

345

{ kX86LockCmpxchg8bM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1d]" },

346

{ kX86LockCmpxchg8bA, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

347

348

EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),

349

EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),

350

EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),

351

EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),

352

#undef EXT_0F_ENCODING_MAP

353

354

{ kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },

355

{ kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },

356

{ kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },

357

{ kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },

358

{ kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" },

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

359

{ kX86Jecxz8, kJmp, NO_OPERAND | IS_BRANCH | NEEDS_FIXUP | REG_USEC, { 0, 0, 0xE3, 0, 0, 0, 0, 0 }, "Jecxz", "!0t" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

360

{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

361

{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

362

{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

363

{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

364

{ kX86CallI, kCall, IS_UNARY_OP | IS_BRANCH, { 0, 0, 0xE8, 0, 0, 0, 0, 4 }, "CallI", "!0d" },

Brian Carlstrom

b1eba21

2013-07-17 18:07:19 -0700

[diff] [blame]

365

{ kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

366

367

{ kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" },

368

{ kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },

369

{ kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" },

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

370

{ kX86RepneScasw, kPrefix2Nullary, NO_OPERAND | SETS_CCODES, { 0x66, 0xF2, 0xAF, 0, 0, 0, 0, 0 }, "RepNE ScasW", "" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

371

};

372

373

static size_t ComputeSize(const X86EncodingMap* entry, int base, int displacement, bool has_sib) {

374

size_t size = 0;

375

if (entry->skeleton.prefix1 > 0) {

376

++size;

377

if (entry->skeleton.prefix2 > 0) {

++size;

}

}

++size; // opcode

if (entry->skeleton.opcode == 0x0F) {

383

++size;

384

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

if (has_sib || base == rX86_SP) {

390

// SP requires a SIB byte.

391

++size;

392

}

393

if (displacement != 0 || base == rBP) {

394

// BP requires an explicit displacement, even when it's 0.

395

if (entry->opcode != kX86Lea32RA) {

396

DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name;

397

}

398

size += IS_SIMM8(displacement) ? 1 : 4;

399

}

400

size += entry->skeleton.immediate_bytes;

return size;

}

int X86Mir2Lir::GetInsnSize(LIR* lir) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

405

DCHECK(!IsPseudoLirOp(lir->opcode));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

406

const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode];

407

switch (entry->kind) {

408

case kData:

409

return 4; // 4 bytes of data

410

case kNop:

411

return lir->operands[0]; // length of nop is sole operand

412

case kNullary:

413

return 1; // 1 byte of opcode

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

414

case kPrefix2Nullary:

415

return 3; // 1 byte of opcode + 2 prefixes

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

416

case kRegOpcode: // lir operands - 0: reg

417

return ComputeSize(entry, 0, 0, false) - 1; // substract 1 for modrm

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

418

case kReg: // lir operands - 0: reg

419

return ComputeSize(entry, 0, 0, false);

420

case kMem: // lir operands - 0: base, 1: disp

421

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

422

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

423

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

424

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

425

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

426

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

427

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

428

case kThreadReg: // lir operands - 0: disp, 1: reg

429

return ComputeSize(entry, 0, lir->operands[0], false);

430

case kRegReg:

431

return ComputeSize(entry, 0, 0, false);

432

case kRegRegStore:

433

return ComputeSize(entry, 0, 0, false);

434

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

435

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

436

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

437

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

438

case kRegThread: // lir operands - 0: reg, 1: disp

439

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

440

case kRegImm: { // lir operands - 0: reg, 1: immediate

441

size_t size = ComputeSize(entry, 0, 0, false);

442

if (entry->skeleton.ax_opcode == 0) {

443

return size;

444

} else {

445

// AX opcodes don't require the modrm byte.

446

int reg = lir->operands[0];

447

return size - (reg == rAX ? 1 : 0);

448

}

449

}

450

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

451

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

452

case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

453

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

454

case kThreadImm: // lir operands - 0: disp, 1: imm

455

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

456

case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

457

case kRegRegImmRev:

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

458

return ComputeSize(entry, 0, 0, false);

459

case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

460

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

461

case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

462

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

463

case kMovRegImm: // lir operands - 0: reg, 1: immediate

464

return 1 + entry->skeleton.immediate_bytes;

465

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

466

// Shift by immediate one has a shorter opcode.

467

return ComputeSize(entry, 0, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

468

case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

469

// Shift by immediate one has a shorter opcode.

470

return ComputeSize(entry, lir->operands[0], lir->operands[1], false) -

471

(lir->operands[2] == 1 ? 1 : 0);

472

case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

473

// Shift by immediate one has a shorter opcode.

474

return ComputeSize(entry, lir->operands[0], lir->operands[3], true) -

475

(lir->operands[4] == 1 ? 1 : 0);

476

case kShiftRegCl:

477

return ComputeSize(entry, 0, 0, false);

478

case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

479

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

480

case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

481

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

482

case kRegCond: // lir operands - 0: reg, 1: cond

483

return ComputeSize(entry, 0, 0, false);

484

case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

485

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

486

case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

487

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

488

case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: cond

489

return ComputeSize(entry, 0, 0, false);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

490

case kJcc:

491

if (lir->opcode == kX86Jcc8) {

492

return 2; // opcode + rel8

493

} else {

494

DCHECK(lir->opcode == kX86Jcc32);

495

return 6; // 2 byte opcode + rel32

496

}

497

case kJmp:

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

498

if (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jecxz8) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

499

return 2; // opcode + rel8

500

} else if (lir->opcode == kX86Jmp32) {

501

return 5; // opcode + rel32

502

} else {

503

DCHECK(lir->opcode == kX86JmpR);

504

return 2; // opcode + modrm

505

}

506

case kCall:

507

switch (lir->opcode) {

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

508

case kX86CallI: return 5; // opcode 0:disp

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

509

case kX86CallR: return 2; // opcode modrm

510

case kX86CallM: // lir operands - 0: base, 1: disp

511

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

512

case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

513

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

514

case kX86CallT: // lir operands - 0: disp

515

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

default:

break;

}

break;

case kPcRel:

if (entry->opcode == kX86PcRelLoadRA) {

522

// lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

523

return ComputeSize(entry, lir->operands[1], 0x12345678, true);

524

} else {

525

DCHECK(entry->opcode == kX86PcRelAdr);

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

526

return 5; // opcode with reg + 4 byte immediate

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

527

}

528

case kMacro:

529

DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));

530

return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +

531

ComputeSize(&X86Mir2Lir::EncodingMap[kX86Sub32RI], 0, 0, false) -

532

(lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

return 0;

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

540

void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry) {

541

if (entry->skeleton.prefix1 != 0) {

542

code_buffer_.push_back(entry->skeleton.prefix1);

543

if (entry->skeleton.prefix2 != 0) {

544

code_buffer_.push_back(entry->skeleton.prefix2);

545

}

546

} else {

547

DCHECK_EQ(0, entry->skeleton.prefix2);

}

}

void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) {

552

code_buffer_.push_back(entry->skeleton.opcode);

553

if (entry->skeleton.opcode == 0x0F) {

554

code_buffer_.push_back(entry->skeleton.extra_opcode1);

555

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

556

code_buffer_.push_back(entry->skeleton.extra_opcode2);

557

} else {

558

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

559

}

560

} else {

561

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

562

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

}

}

void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry) {

EmitPrefix(entry);

EmitOpcode(entry);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

571

static uint8_t ModrmForDisp(int base, int disp) {

572

// BP requires an explicit disp, so do not omit it in the 0 case

573

if (disp == 0 && base != rBP) {

574

return 0;

575

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

582

void X86Mir2Lir::EmitDisp(uint8_t base, int disp) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

583

// BP requires an explicit disp, so do not omit it in the 0 case

584

if (disp == 0 && base != rBP) {

585

return;

586

} else if (IS_SIMM8(disp)) {

587

code_buffer_.push_back(disp & 0xFF);

588

} else {

589

code_buffer_.push_back(disp & 0xFF);

590

code_buffer_.push_back((disp >> 8) & 0xFF);

591

code_buffer_.push_back((disp >> 16) & 0xFF);

592

code_buffer_.push_back((disp >> 24) & 0xFF);

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

596

void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp) {

597

DCHECK_LT(reg_or_opcode, 8);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

598

DCHECK_LT(base, 8);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

599

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | base;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

600

code_buffer_.push_back(modrm);

601

if (base == rX86_SP) {

602

// Special SIB for SP base

603

code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);

604

}

605

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

606

}

607

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

608

void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index,

609

int scale, int disp) {

610

DCHECK_LT(reg_or_opcode, 8);

611

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | rX86_SP;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

612

code_buffer_.push_back(modrm);

DCHECK_LT(scale, 4);

DCHECK_LT(index, 8);

DCHECK_LT(base, 8);

uint8_t sib = (scale << 6) | (index << 3) | base;

617

code_buffer_.push_back(sib);

618

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

619

}

620

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

621

void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int imm) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

622

switch (entry->skeleton.immediate_bytes) {

623

case 1:

624

DCHECK(IS_SIMM8(imm));

625

code_buffer_.push_back(imm & 0xFF);

626

break;

627

case 2:

628

DCHECK(IS_SIMM16(imm));

629

code_buffer_.push_back(imm & 0xFF);

630

code_buffer_.push_back((imm >> 8) & 0xFF);

631

break;

632

case 4:

633

code_buffer_.push_back(imm & 0xFF);

634

code_buffer_.push_back((imm >> 8) & 0xFF);

635

code_buffer_.push_back((imm >> 16) & 0xFF);

636

code_buffer_.push_back((imm >> 24) & 0xFF);

637

break;

638

default:

639

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

640

<< ") for instruction: " << entry->name;

break;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

645

void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg) {

646

EmitPrefixAndOpcode(entry);

647

// There's no 3-byte instruction with +rd

648

DCHECK(entry->skeleton.opcode != 0x0F ||

649

(entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A));

650

DCHECK(!X86_FPREG(reg));

651

DCHECK_LT(reg, 8);

652

code_buffer_.back() += reg;

653

DCHECK_EQ(0, entry->skeleton.ax_opcode);

654

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

655

}

656

657

void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) {

658

EmitPrefixAndOpcode(entry);

659

if (X86_FPREG(reg)) {

660

reg = reg & X86_FP_REG_MASK;

661

}

662

if (reg >= 4) {

663

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

664

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

665

}

666

DCHECK_LT(reg, 8);

667

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

668

code_buffer_.push_back(modrm);

669

DCHECK_EQ(0, entry->skeleton.ax_opcode);

670

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

671

}

672

673

void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) {

674

EmitPrefix(entry);

675

code_buffer_.push_back(entry->skeleton.opcode);

676

DCHECK_NE(0x0F, entry->skeleton.opcode);

677

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

678

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

679

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

680

DCHECK_EQ(0, entry->skeleton.ax_opcode);

681

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

682

}

683

684

void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index,

685

int scale, int disp) {

686

EmitPrefixAndOpcode(entry);

687

EmitModrmSibDisp(entry->skeleton.modrm_opcode, base, index, scale, disp);

688

DCHECK_EQ(0, entry->skeleton.ax_opcode);

689

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

690

}

691

692

void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry,

693

uint8_t base, int disp, uint8_t reg) {

694

EmitPrefixAndOpcode(entry);

695

if (X86_FPREG(reg)) {

696

reg = reg & X86_FP_REG_MASK;

697

}

698

if (reg >= 4) {

699

DCHECK(strchr(entry->name, '8') == NULL ||

700

entry->opcode == kX86Movzx8RM || entry->opcode == kX86Movsx8RM)

701

<< entry->name << " " << static_cast<int>(reg)

702

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

703

}

704

EmitModrmDisp(reg, base, disp);

705

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

706

DCHECK_EQ(0, entry->skeleton.ax_opcode);

707

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

708

}

709

710

void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry,

711

uint8_t reg, uint8_t base, int disp) {

712

// Opcode will flip operands.

713

EmitMemReg(entry, base, disp, reg);

714

}

715

716

void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index,

717

int scale, int disp) {

718

EmitPrefixAndOpcode(entry);

719

if (X86_FPREG(reg)) {

720

reg = reg & X86_FP_REG_MASK;

721

}

722

EmitModrmSibDisp(reg, base, index, scale, disp);

723

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

724

DCHECK_EQ(0, entry->skeleton.ax_opcode);

725

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

726

}

727

728

void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp,

729

uint8_t reg) {

730

// Opcode will flip operands.

731

EmitRegArray(entry, reg, base, index, scale, disp);

732

}

733

734

void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) {

735

DCHECK_NE(entry->skeleton.prefix1, 0);

736

EmitPrefixAndOpcode(entry);

737

if (X86_FPREG(reg)) {

738

reg = reg & X86_FP_REG_MASK;

739

}

740

if (reg >= 4) {

741

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

742

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

743

}

744

DCHECK_LT(reg, 8);

745

uint8_t modrm = (0 << 6) | (reg << 3) | rBP;

746

code_buffer_.push_back(modrm);

747

code_buffer_.push_back(disp & 0xFF);

748

code_buffer_.push_back((disp >> 8) & 0xFF);

749

code_buffer_.push_back((disp >> 16) & 0xFF);

750

code_buffer_.push_back((disp >> 24) & 0xFF);

751

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

752

DCHECK_EQ(0, entry->skeleton.ax_opcode);

753

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

754

}

755

756

void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) {

757

EmitPrefixAndOpcode(entry);

758

if (X86_FPREG(reg1)) {

759

reg1 = reg1 & X86_FP_REG_MASK;

760

}

761

if (X86_FPREG(reg2)) {

762

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

767

code_buffer_.push_back(modrm);

768

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

769

DCHECK_EQ(0, entry->skeleton.ax_opcode);

770

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

771

}

772

773

void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry,

774

uint8_t reg1, uint8_t reg2, int32_t imm) {

775

EmitPrefixAndOpcode(entry);

776

if (X86_FPREG(reg1)) {

777

reg1 = reg1 & X86_FP_REG_MASK;

778

}

779

if (X86_FPREG(reg2)) {

780

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

785

code_buffer_.push_back(modrm);

786

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

787

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

791

void X86Mir2Lir::EmitRegRegImmRev(const X86EncodingMap* entry,

792

uint8_t reg1, uint8_t reg2, int32_t imm) {

793

EmitRegRegImm(entry, reg2, reg1, imm);

794

}

795

796

void X86Mir2Lir::EmitRegMemImm(const X86EncodingMap* entry,

797

uint8_t reg, uint8_t base, int disp, int32_t imm) {

798

EmitPrefixAndOpcode(entry);

799

DCHECK(!X86_FPREG(reg));

800

DCHECK_LT(reg, 8);

801

EmitModrmDisp(reg, base, disp);

802

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

803

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

807

void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

808

if (entry->skeleton.prefix1 != 0) {

809

code_buffer_.push_back(entry->skeleton.prefix1);

810

if (entry->skeleton.prefix2 != 0) {

811

code_buffer_.push_back(entry->skeleton.prefix2);

812

}

813

} else {

814

DCHECK_EQ(0, entry->skeleton.prefix2);

815

}

816

if (reg == rAX && entry->skeleton.ax_opcode != 0) {

817

code_buffer_.push_back(entry->skeleton.ax_opcode);

818

} else {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

819

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

820

if (X86_FPREG(reg)) {

821

reg = reg & X86_FP_REG_MASK;

822

}

823

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

824

code_buffer_.push_back(modrm);

825

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

826

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

827

}

828

Mark Mendell

343adb5

2013-12-18 06:02:17 -0800

[diff] [blame]

829

void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm) {

830

EmitPrefixAndOpcode(entry);

831

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

832

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

836

void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

837

EmitPrefixAndOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

838

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

839

code_buffer_.push_back(modrm);

840

code_buffer_.push_back(disp & 0xFF);

841

code_buffer_.push_back((disp >> 8) & 0xFF);

842

code_buffer_.push_back((disp >> 16) & 0xFF);

843

code_buffer_.push_back((disp >> 24) & 0xFF);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

844

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

845

DCHECK_EQ(entry->skeleton.ax_opcode, 0);

846

}

847

848

void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

849

DCHECK_LT(reg, 8);

850

code_buffer_.push_back(0xB8 + reg);

851

code_buffer_.push_back(imm & 0xFF);

852

code_buffer_.push_back((imm >> 8) & 0xFF);

853

code_buffer_.push_back((imm >> 16) & 0xFF);

854

code_buffer_.push_back((imm >> 24) & 0xFF);

855

}

856

857

void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

858

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

859

if (imm != 1) {

860

code_buffer_.push_back(entry->skeleton.opcode);

861

} else {

862

// Shorter encoding for 1 bit shift

863

code_buffer_.push_back(entry->skeleton.ax_opcode);

864

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

865

DCHECK_NE(0x0F, entry->skeleton.opcode);

866

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

867

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

868

if (reg >= 4) {

869

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

870

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

871

}

872

DCHECK_LT(reg, 8);

873

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

874

code_buffer_.push_back(modrm);

875

if (imm != 1) {

876

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

877

DCHECK(IS_SIMM8(imm));

878

code_buffer_.push_back(imm & 0xFF);

}

}

void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl) {

883

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

884

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

885

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

886

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

887

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

888

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

889

DCHECK_LT(reg, 8);

890

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

891

code_buffer_.push_back(modrm);

892

DCHECK_EQ(0, entry->skeleton.ax_opcode);

893

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

894

}

895

Mark Mendell

feb2b4e

2014-01-28 12:59:49 -0800

[diff] [blame]

896

void X86Mir2Lir::EmitShiftMemCl(const X86EncodingMap* entry, uint8_t base,

897

int displacement, uint8_t cl) {

898

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

899

EmitPrefix(entry);

900

code_buffer_.push_back(entry->skeleton.opcode);

901

DCHECK_NE(0x0F, entry->skeleton.opcode);

902

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

903

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

904

DCHECK_LT(base, 8);

905

EmitModrmDisp(entry->skeleton.modrm_opcode, base, displacement);

906

DCHECK_EQ(0, entry->skeleton.ax_opcode);

907

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

908

}

909

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

910

void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) {

911

if (entry->skeleton.prefix1 != 0) {

912

code_buffer_.push_back(entry->skeleton.prefix1);

913

if (entry->skeleton.prefix2 != 0) {

914

code_buffer_.push_back(entry->skeleton.prefix2);

915

}

916

} else {

917

DCHECK_EQ(0, entry->skeleton.prefix2);

918

}

919

DCHECK_EQ(0, entry->skeleton.ax_opcode);

920

DCHECK_EQ(0x0F, entry->skeleton.opcode);

921

code_buffer_.push_back(0x0F);

922

DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);

923

code_buffer_.push_back(0x90 | condition);

924

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

925

DCHECK_LT(reg, 8);

926

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

927

code_buffer_.push_back(modrm);

928

DCHECK_EQ(entry->skeleton.immediate_bytes, 0);

929

}

930

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

931

void X86Mir2Lir::EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, uint8_t condition) {

932

// Generate prefix and opcode without the condition

933

EmitPrefixAndOpcode(entry);

934

935

// Now add the condition. The last byte of opcode is the one that receives it.

936

DCHECK_LE(condition, 0xF);

937

code_buffer_.back() += condition;

938

939

// Not expecting to have to encode immediate or do anything special for ModR/M since there are two registers.

940

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

941

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

942

943

// Check that registers requested for encoding are sane.

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

// For register to register encoding, the mod is 3.

948

const uint8_t mod = (3 << 6);

949

950

// Encode the ModR/M byte now.

951

const uint8_t modrm = mod | (reg1 << 3) | reg2;

952

code_buffer_.push_back(modrm);

953

}

954

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

955

void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int rel) {

956

if (entry->opcode == kX86Jmp8) {

957

DCHECK(IS_SIMM8(rel));

958

code_buffer_.push_back(0xEB);

959

code_buffer_.push_back(rel & 0xFF);

960

} else if (entry->opcode == kX86Jmp32) {

961

code_buffer_.push_back(0xE9);

962

code_buffer_.push_back(rel & 0xFF);

963

code_buffer_.push_back((rel >> 8) & 0xFF);

964

code_buffer_.push_back((rel >> 16) & 0xFF);

965

code_buffer_.push_back((rel >> 24) & 0xFF);

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

966

} else if (entry->opcode == kX86Jecxz8) {

967

DCHECK(IS_SIMM8(rel));

968

code_buffer_.push_back(0xE3);

969

code_buffer_.push_back(rel & 0xFF);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

970

} else {

971

DCHECK(entry->opcode == kX86JmpR);

972

code_buffer_.push_back(entry->skeleton.opcode);

973

uint8_t reg = static_cast<uint8_t>(rel);

974

DCHECK_LT(reg, 8);

975

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

976

code_buffer_.push_back(modrm);

}

}

void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc) {

981

DCHECK_LT(cc, 16);

982

if (entry->opcode == kX86Jcc8) {

983

DCHECK(IS_SIMM8(rel));

984

code_buffer_.push_back(0x70 | cc);

985

code_buffer_.push_back(rel & 0xFF);

986

} else {

987

DCHECK(entry->opcode == kX86Jcc32);

988

code_buffer_.push_back(0x0F);

989

code_buffer_.push_back(0x80 | cc);

990

code_buffer_.push_back(rel & 0xFF);

991

code_buffer_.push_back((rel >> 8) & 0xFF);

992

code_buffer_.push_back((rel >> 16) & 0xFF);

993

code_buffer_.push_back((rel >> 24) & 0xFF);

}

}

void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

998

EmitPrefixAndOpcode(entry);

999

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1000

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1001

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1002

}

1003

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

1004

void X86Mir2Lir::EmitCallImmediate(const X86EncodingMap* entry, int disp) {

1005

EmitPrefixAndOpcode(entry);

1006

DCHECK_EQ(4, entry->skeleton.immediate_bytes);

1007

code_buffer_.push_back(disp & 0xFF);

1008

code_buffer_.push_back((disp >> 8) & 0xFF);

1009

code_buffer_.push_back((disp >> 16) & 0xFF);

1010

code_buffer_.push_back((disp >> 24) & 0xFF);

1011

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1012

}

1013

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1014

void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int disp) {

1015

DCHECK_NE(entry->skeleton.prefix1, 0);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1016

EmitPrefixAndOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1017

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

1018

code_buffer_.push_back(modrm);

1019

code_buffer_.push_back(disp & 0xFF);

1020

code_buffer_.push_back((disp >> 8) & 0xFF);

1021

code_buffer_.push_back((disp >> 16) & 0xFF);

1022

code_buffer_.push_back((disp >> 24) & 0xFF);

1023

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1024

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1025

}

1026

1027

void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, uint8_t reg,

1028

int base_or_table, uint8_t index, int scale, int table_or_disp) {

1029

int disp;

1030

if (entry->opcode == kX86PcRelLoadRA) {

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1031

Mir2Lir::EmbeddedData *tab_rec =

1032

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1033

disp = tab_rec->offset;

1034

} else {

1035

DCHECK(entry->opcode == kX86PcRelAdr);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1036

Mir2Lir::EmbeddedData *tab_rec =

1037

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(base_or_table));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1038

disp = tab_rec->offset;

1039

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1040

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1041

if (X86_FPREG(reg)) {

1042

reg = reg & X86_FP_REG_MASK;

1043

}

1044

DCHECK_LT(reg, 8);

1045

if (entry->opcode == kX86PcRelLoadRA) {

1046

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1047

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1048

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1049

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1050

uint8_t modrm = (2 << 6) | (reg << 3) | rX86_SP;

1051

code_buffer_.push_back(modrm);

1052

DCHECK_LT(scale, 4);

1053

DCHECK_LT(index, 8);

1054

DCHECK_LT(base_or_table, 8);

1055

uint8_t base = static_cast<uint8_t>(base_or_table);

1056

uint8_t sib = (scale << 6) | (index << 3) | base;

1057

code_buffer_.push_back(sib);

1058

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1059

} else {

1060

code_buffer_.push_back(entry->skeleton.opcode + reg);

1061

}

1062

code_buffer_.push_back(disp & 0xFF);

1063

code_buffer_.push_back((disp >> 8) & 0xFF);

1064

code_buffer_.push_back((disp >> 16) & 0xFF);

1065

code_buffer_.push_back((disp >> 24) & 0xFF);

1066

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1067

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1068

}

1069

1070

void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset) {

1071

DCHECK(entry->opcode == kX86StartOfMethod) << entry->name;

1072

code_buffer_.push_back(0xE8); // call +0

1073

code_buffer_.push_back(0);

1074

code_buffer_.push_back(0);

1075

code_buffer_.push_back(0);

1076

code_buffer_.push_back(0);

1077

1078

DCHECK_LT(reg, 8);

1079

code_buffer_.push_back(0x58 + reg); // pop reg

1080

1081

EmitRegImm(&X86Mir2Lir::EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */);

1082

}

1083

1084

void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) {

1085

UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " "

1086

<< BuildInsnString(entry->fmt, lir, 0);

1087

for (int i = 0; i < GetInsnSize(lir); ++i) {

1088

code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3

}

}

/*

* Assemble the LIR into binary instruction format. Note that we may

1094

* discover that pc-relative displacements may not fit the selected

1095

* instruction. In those cases we will try to substitute a new code

1096

* sequence or request that the trace be shortened and retried.

1097

*/

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1098

AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1099

LIR *lir;

1100

AssemblerStatus res = kSuccess; // Assume success

1101

1102

const bool kVerbosePcFixup = false;

1103

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1104

if (IsPseudoLirOp(lir->opcode)) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

continue;

}

if (lir->flags.is_nop) {

continue;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1112

if (lir->flags.fixup != kFixupNone) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1113

switch (lir->opcode) {

1114

case kX86Jcc8: {

1115

LIR *target_lir = lir->target;

1116

DCHECK(target_lir != NULL);

1117

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1118

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1119

if (IS_SIMM8(lir->operands[0])) {

1120

pc = lir->offset + 2 /* opcode + rel8 */;

1121

} else {

1122

pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1123

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1124

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1125

delta = target - pc;

1126

if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1127

if (kVerbosePcFixup) {

1128

LOG(INFO) << "Retry for JCC growth at " << lir->offset

1129

<< " delta: " << delta << " old delta: " << lir->operands[0];

1130

}

1131

lir->opcode = kX86Jcc32;

1132

SetupResourceMasks(lir);

1133

res = kRetryAll;

1134

}

1135

if (kVerbosePcFixup) {

1136

LOG(INFO) << "Source:";

1137

DumpLIRInsn(lir, 0);

1138

LOG(INFO) << "Target:";

1139

DumpLIRInsn(target_lir, 0);

1140

LOG(INFO) << "Delta " << delta;

1141

}

1142

lir->operands[0] = delta;

break;

}

case kX86Jcc32: {

LIR *target_lir = lir->target;

1147

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1148

CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1149

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1150

int delta = target - pc;

1151

if (kVerbosePcFixup) {

1152

LOG(INFO) << "Source:";

1153

DumpLIRInsn(lir, 0);

1154

LOG(INFO) << "Target:";

1155

DumpLIRInsn(target_lir, 0);

1156

LOG(INFO) << "Delta " << delta;

1157

}

1158

lir->operands[0] = delta;

1159

break;

1160

}

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

1161

case kX86Jecxz8: {

1162

LIR *target_lir = lir->target;

1163

DCHECK(target_lir != NULL);

1164

CodeOffset pc;

1165

pc = lir->offset + 2; // opcode + rel8

1166

CodeOffset target = target_lir->offset;

1167

int delta = target - pc;

1168

lir->operands[0] = delta;

1169

DCHECK(IS_SIMM8(delta));

1170

break;

1171

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1172

case kX86Jmp8: {

1173

LIR *target_lir = lir->target;

1174

DCHECK(target_lir != NULL);

1175

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1176

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1177

if (IS_SIMM8(lir->operands[0])) {

1178

pc = lir->offset + 2 /* opcode + rel8 */;

1179

} else {

1180

pc = lir->offset + 5 /* opcode + rel32 */;

1181

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1182

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1183

delta = target - pc;

1184

if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) {

1185

// Useless branch

buzbee

252254b

2013-09-08 16:20:53 -0700

[diff] [blame]

1186

NopLIR(lir);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1187

if (kVerbosePcFixup) {

1188

LOG(INFO) << "Retry for useless branch at " << lir->offset;

1189

}

1190

res = kRetryAll;

1191

} else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1192

if (kVerbosePcFixup) {

1193

LOG(INFO) << "Retry for JMP growth at " << lir->offset;

1194

}

1195

lir->opcode = kX86Jmp32;

1196

SetupResourceMasks(lir);

1197

res = kRetryAll;

1198

}

1199

lir->operands[0] = delta;

break;

}

case kX86Jmp32: {

LIR *target_lir = lir->target;

1204

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1205

CodeOffset pc = lir->offset + 5 /* opcode + rel32 */;

1206

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1207

int delta = target - pc;

1208

lir->operands[0] = delta;

1209

break;

1210

}

1211

default:

Mark Mendell

67c39c4

2014-01-31 17:28:00 -0800

[diff] [blame]

1212

if (lir->flags.fixup == kFixupLoad) {

1213

LIR *target_lir = lir->target;

1214

DCHECK(target_lir != NULL);

1215

CodeOffset target = target_lir->offset;

1216

lir->operands[2] = target;

1217

int newSize = GetInsnSize(lir);

1218

if (newSize != lir->flags.size) {

1219

lir->flags.size = newSize;

1220

res = kRetryAll;

1221

}

1222

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

break;

}

}

/*

* If one of the pc-relative instructions expanded we'll have

1229

* to make another pass. Don't bother to fully assemble the

1230

* instruction.

1231

*/

1232

if (res != kSuccess) {

1233

continue;

1234

}

1235

CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size());

1236

const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode];

1237

size_t starting_cbuf_size = code_buffer_.size();

1238

switch (entry->kind) {

1239

case kData: // 4 bytes of data

1240

code_buffer_.push_back(lir->operands[0]);

1241

break;

1242

case kNullary: // 1 byte of opcode

1243

DCHECK_EQ(0, entry->skeleton.prefix1);

1244

DCHECK_EQ(0, entry->skeleton.prefix2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1245

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1246

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1247

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1248

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1249

break;

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

1250

case kPrefix2Nullary: // 1 byte of opcode + 2 prefixes.

1251

DCHECK_NE(0, entry->skeleton.prefix1);

1252

DCHECK_NE(0, entry->skeleton.prefix2);

1253

EmitPrefixAndOpcode(entry);

1254

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1255

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1256

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1257

break;

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

1258

case kRegOpcode: // lir operands - 0: reg

1259

EmitOpRegOpcode(entry, lir->operands[0]);

1260

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1261

case kReg: // lir operands - 0: reg

1262

EmitOpReg(entry, lir->operands[0]);

1263

break;

1264

case kMem: // lir operands - 0: base, 1: disp

1265

EmitOpMem(entry, lir->operands[0], lir->operands[1]);

1266

break;

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1267

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

1268

EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]);

1269

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1270

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

1271

EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1272

break;

Mark Mendell

343adb5

2013-12-18 06:02:17 -0800

[diff] [blame]

1273

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

1274

EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1275

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1276

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

1277

EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1278

lir->operands[3], lir->operands[4]);

1279

break;

1280

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

1281

EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1282

break;

1283

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

1284

EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1285

lir->operands[3], lir->operands[4]);

1286

break;

1287

case kRegThread: // lir operands - 0: reg, 1: disp

1288

EmitRegThread(entry, lir->operands[0], lir->operands[1]);

1289

break;

1290

case kRegReg: // lir operands - 0: reg1, 1: reg2

1291

EmitRegReg(entry, lir->operands[0], lir->operands[1]);

1292

break;

1293

case kRegRegStore: // lir operands - 0: reg2, 1: reg1

1294

EmitRegReg(entry, lir->operands[1], lir->operands[0]);

1295

break;

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

1296

case kRegRegImmRev:

1297

EmitRegRegImmRev(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1298

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1299

case kRegRegImm:

1300

EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1301

break;

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

1302

case kRegMemImm:

1303

EmitRegMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1304

lir->operands[3]);

1305

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1306

case kRegImm: // lir operands - 0: reg, 1: immediate

1307

EmitRegImm(entry, lir->operands[0], lir->operands[1]);

1308

break;

1309

case kThreadImm: // lir operands - 0: disp, 1: immediate

1310

EmitThreadImm(entry, lir->operands[0], lir->operands[1]);

1311

break;

1312

case kMovRegImm: // lir operands - 0: reg, 1: immediate

1313

EmitMovRegImm(entry, lir->operands[0], lir->operands[1]);

1314

break;

1315

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

1316

EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]);

1317

break;

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

1318

case kShiftRegCl: // lir operands - 0: reg, 1: cl

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1319

EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]);

1320

break;

Mark Mendell

feb2b4e

2014-01-28 12:59:49 -0800

[diff] [blame]

1321

case kShiftMemCl: // lir operands - 0: base, 1:displacement, 2: cl

1322

EmitShiftMemCl(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1323

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1324

case kRegCond: // lir operands - 0: reg, 1: condition

1325

EmitRegCond(entry, lir->operands[0], lir->operands[1]);

1326

break;

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

1327

case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: condition

1328

EmitRegRegCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1329

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1330

case kJmp: // lir operands - 0: rel

1331

EmitJmp(entry, lir->operands[0]);

1332

break;

1333

case kJcc: // lir operands - 0: rel, 1: CC, target assigned

1334

EmitJcc(entry, lir->operands[0], lir->operands[1]);

1335

break;

1336

case kCall:

1337

switch (entry->opcode) {

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

1338

case kX86CallI: // lir operands - 0: disp

1339

EmitCallImmediate(entry, lir->operands[0]);

1340

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1341

case kX86CallM: // lir operands - 0: base, 1: disp

1342

EmitCallMem(entry, lir->operands[0], lir->operands[1]);

1343

break;

1344

case kX86CallT: // lir operands - 0: disp

1345

EmitCallThread(entry, lir->operands[0]);

1346

break;

1347

default:

1348

EmitUnimplemented(entry, lir);

break;

}

break;

case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

1353

EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1354

lir->operands[3], lir->operands[4]);

1355

break;

1356

case kMacro:

1357

EmitMacro(entry, lir->operands[0], lir->offset);

1358

break;

1359

default:

1360

EmitUnimplemented(entry, lir);

1361

break;

1362

}

1363

CHECK_EQ(static_cast<size_t>(GetInsnSize(lir)),

1364

code_buffer_.size() - starting_cbuf_size)

1365

<< "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name;

}

return res;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1370

// LIR offset assignment.

1371

// TODO: consolidate w/ Arm assembly mechanism.

1372

int X86Mir2Lir::AssignInsnOffsets() {

LIR* lir;

int offset = 0;

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

1377

lir->offset = offset;

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1378

if (LIKELY(!IsPseudoLirOp(lir->opcode))) {

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1379

if (!lir->flags.is_nop) {

1380

offset += lir->flags.size;

1381

}

1382

} else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) {

1383

if (offset & 0x2) {

1384

offset += 2;

1385

lir->operands[0] = 1;

1386

} else {

1387

lir->operands[0] = 0;

1388

}

1389

}

1390

/* Pseudo opcodes don't consume space */

}

return offset;

}

/*

* Walk the compilation unit and assign offsets to instructions

1397

* and literals and compute the total size of the compiled unit.

1398

* TODO: consolidate w/ Arm assembly mechanism.

1399

*/

1400

void X86Mir2Lir::AssignOffsets() {

1401

int offset = AssignInsnOffsets();

1402

1403

/* Const values have to be word aligned */

1404

offset = (offset + 3) & ~3;

1405

1406

/* Set up offsets for literals */

1407

data_offset_ = offset;

1408

1409

offset = AssignLiteralOffset(offset);

1410

1411

offset = AssignSwitchTablesOffset(offset);

1412

1413

offset = AssignFillArrayDataOffset(offset);

1414

1415

total_size_ = offset;

}

/*

* Go over each instruction in the list and calculate the offset from the top

1420

* before sending them off to the assembler. If out-of-range branch distance is

1421

* seen rearrange the instructions a bit to correct it.

1422

* TODO: consolidate w/ Arm assembly mechanism.

1423

*/

1424

void X86Mir2Lir::AssembleLIR() {

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1425

cu_->NewTimingSplit("Assemble");

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

1426

1427

// We will remove the method address if we never ended up using it

1428

if (store_method_addr_ && !store_method_addr_used_) {

1429

setup_method_address_[0]->flags.is_nop = true;

1430

setup_method_address_[1]->flags.is_nop = true;

1431

}

1432

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1433

AssignOffsets();

1434

int assembler_retries = 0;

1435

/*

1436

* Assemble here. Note that we generate code with optimistic assumptions

1437

* and if found now to work, we'll have to redo the sequence and retry.

*/

while (true) {

AssemblerStatus res = AssembleInstructions(0);

1442

if (res == kSuccess) {

break;

} else {

assembler_retries++;

if (assembler_retries > MAX_ASSEMBLER_RETRIES) {

1447

CodegenDump();

1448

LOG(FATAL) << "Assembler error - too many retries";

1449

}

1450

// Redo offsets and try again

1451

AssignOffsets();

1452

code_buffer_.clear();

}

}

// Install literals

InstallLiteralPools();

1458

1459

// Install switch tables

1460

InstallSwitchTables();

1461

1462

// Install fill array data

1463

InstallFillArrayData();

1464

1465

// Create the mapping table and native offset to reference map.

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1466

cu_->NewTimingSplit("PcMappingTable");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1467

CreateMappingTables();

1468

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1469

cu_->NewTimingSplit("GcMap");

buzbee