Blame - compiler/dex/quick/x86/assemble_x86.cc - platform_art

2013-12-20 17:27:23 -0800

[diff] [blame]

180

{ kX86Cmov32RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, {0, 0, 0x0F, 0x40, 0, 0, 0, 0}, "Cmovcc32RR", "!2c !0r,!1r" },

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Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \

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{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \

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{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \

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{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \

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{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }

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SHIFT_ENCODING_MAP(Rol, 0x0),

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SHIFT_ENCODING_MAP(Ror, 0x1),

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SHIFT_ENCODING_MAP(Rcl, 0x2),

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SHIFT_ENCODING_MAP(Rcr, 0x3),

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SHIFT_ENCODING_MAP(Sal, 0x4),

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SHIFT_ENCODING_MAP(Shr, 0x5),

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SHIFT_ENCODING_MAP(Sar, 0x7),

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#undef SHIFT_ENCODING_MAP

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{ kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0}, "Cmc", "" },

Mark Mendell

2014-01-22 09:05:18 -0800

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214

{ kX86Shld32RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1}, "Shld32", "!0r,!1r,!2d" },

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{ kX86Shrd32RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1}, "Shrd32", "!0r,!1r,!2d" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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{ kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" },

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{ kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" },

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{ kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" },

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{ kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" },

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{ kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" },

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{ kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" },

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{ kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0}, "Test32RR", "!0r,!1r" },

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#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \

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reg, reg_kind, reg_flags, \

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mem, mem_kind, mem_flags, \

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arr, arr_kind, arr_flags, imm, \

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b_flags, hw_flags, w_flags, \

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b_format, hw_format, w_format) \

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{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, #b_format "!0r" }, \

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{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, #b_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, #b_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, #hw_format "!0r" }, \

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{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, #hw_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, #hw_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, #w_format "!0r" }, \

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{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, #w_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, #w_format "[!0r+!1r<<!2d+!3d]" }

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UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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Mark Mendell

2bf31e6

2014-01-23 12:13:40 -0800

[diff] [blame]

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UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

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UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#undef UNARY_ENCODING_MAP

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Mark Mendell

2bf31e6

2014-01-23 12:13:40 -0800

[diff] [blame]

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{ kx86Cdq32Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { 0, 0, 0x99, 0, 0, 0, 0, 0 }, "Cdq", "" },

Vladimir Marko

a6fd8ba

2013-12-13 10:53:49 +0000

[diff] [blame]

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{ kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0 }, "Bswap32R", "!0r" },

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{ kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0 }, "Push32R", "!0r" },

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{ kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0 }, "Pop32R", "!0r" },

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

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Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \

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{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

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{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

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EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),

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{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

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{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),

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{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

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{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0),

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EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0),

Razvan A Lupusoru

d3266bc

2014-01-24 12:55:31 -0800

[diff] [blame]

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EXT_0F_ENCODING_MAP(Punpckldq, 0x66, 0x62, REG_DEF0),

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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{ kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" },

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{ kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" },

Mark Mendell

bff1ef0

2013-12-13 13:47:34 -0800

[diff] [blame]

297

{ kX86SqrtsdRR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0xF2, 0, 0x0F, 0x51, 0, 0, 0, 0 }, "SqrtsdRR", "!0r,!1r" },

Vladimir Marko

12f9628

2013-12-16 14:44:03 +0000

[diff] [blame]

298

{ kX86FstpdM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0 }, "FstpdM", "[!0r,!1d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),

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{ kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" },

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{ kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" },

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{ kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

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{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

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{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

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// TODO: load/store?

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// Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.

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{ kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },

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EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES),

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EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES),

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{ kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" },

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{ kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" },

318

{ kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

319

{ kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" },

320

{ kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Vladimir Marko

70b797d

2013-12-03 15:25:24 +0000

[diff] [blame]

321

{ kX86LockCmpxchg8bM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1d]" },

322

{ kX86LockCmpxchg8bA, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

323

324

EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),

325

EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),

326

EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),

327

EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),

328

#undef EXT_0F_ENCODING_MAP

329

330

{ kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },

331

{ kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },

332

{ kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },

333

{ kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },

334

{ kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" },

335

{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

336

{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

337

{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

338

{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

Brian Carlstrom

b1eba21

2013-07-17 18:07:19 -0700

[diff] [blame]

339

{ kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

340

341

{ kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" },

342

{ kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },

343

{ kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" },

344

};

345

346

static size_t ComputeSize(const X86EncodingMap* entry, int base, int displacement, bool has_sib) {

347

size_t size = 0;

348

if (entry->skeleton.prefix1 > 0) {

349

++size;

350

if (entry->skeleton.prefix2 > 0) {

++size;

}

}

++size; // opcode

if (entry->skeleton.opcode == 0x0F) {

356

++size;

357

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

if (has_sib || base == rX86_SP) {

363

// SP requires a SIB byte.

364

++size;

365

}

366

if (displacement != 0 || base == rBP) {

367

// BP requires an explicit displacement, even when it's 0.

368

if (entry->opcode != kX86Lea32RA) {

369

DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name;

370

}

371

size += IS_SIMM8(displacement) ? 1 : 4;

372

}

373

size += entry->skeleton.immediate_bytes;

return size;

}

int X86Mir2Lir::GetInsnSize(LIR* lir) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

378

DCHECK(!IsPseudoLirOp(lir->opcode));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

379

const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode];

380

switch (entry->kind) {

381

case kData:

382

return 4; // 4 bytes of data

383

case kNop:

384

return lir->operands[0]; // length of nop is sole operand

385

case kNullary:

386

return 1; // 1 byte of opcode

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

387

case kRegOpcode: // lir operands - 0: reg

388

return ComputeSize(entry, 0, 0, false) - 1; // substract 1 for modrm

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

389

case kReg: // lir operands - 0: reg

390

return ComputeSize(entry, 0, 0, false);

391

case kMem: // lir operands - 0: base, 1: disp

392

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

393

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

394

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

395

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

396

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

397

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

398

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

399

case kThreadReg: // lir operands - 0: disp, 1: reg

400

return ComputeSize(entry, 0, lir->operands[0], false);

401

case kRegReg:

402

return ComputeSize(entry, 0, 0, false);

403

case kRegRegStore:

404

return ComputeSize(entry, 0, 0, false);

405

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

406

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

407

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

408

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

409

case kRegThread: // lir operands - 0: reg, 1: disp

410

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

411

case kRegImm: { // lir operands - 0: reg, 1: immediate

412

size_t size = ComputeSize(entry, 0, 0, false);

413

if (entry->skeleton.ax_opcode == 0) {

414

return size;

415

} else {

416

// AX opcodes don't require the modrm byte.

417

int reg = lir->operands[0];

418

return size - (reg == rAX ? 1 : 0);

419

}

420

}

421

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

422

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

423

case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

424

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

425

case kThreadImm: // lir operands - 0: disp, 1: imm

426

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

427

case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

428

case kRegRegImmRev:

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

429

return ComputeSize(entry, 0, 0, false);

430

case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

431

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

432

case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

433

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

434

case kMovRegImm: // lir operands - 0: reg, 1: immediate

435

return 1 + entry->skeleton.immediate_bytes;

436

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

437

// Shift by immediate one has a shorter opcode.

438

return ComputeSize(entry, 0, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

439

case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

440

// Shift by immediate one has a shorter opcode.

441

return ComputeSize(entry, lir->operands[0], lir->operands[1], false) -

442

(lir->operands[2] == 1 ? 1 : 0);

443

case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

444

// Shift by immediate one has a shorter opcode.

445

return ComputeSize(entry, lir->operands[0], lir->operands[3], true) -

446

(lir->operands[4] == 1 ? 1 : 0);

447

case kShiftRegCl:

448

return ComputeSize(entry, 0, 0, false);

449

case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

450

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

451

case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

452

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

453

case kRegCond: // lir operands - 0: reg, 1: cond

454

return ComputeSize(entry, 0, 0, false);

455

case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

456

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

457

case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

458

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

459

case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: cond

460

return ComputeSize(entry, 0, 0, false);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

461

case kJcc:

462

if (lir->opcode == kX86Jcc8) {

463

return 2; // opcode + rel8

464

} else {

465

DCHECK(lir->opcode == kX86Jcc32);

466

return 6; // 2 byte opcode + rel32

467

}

468

case kJmp:

469

if (lir->opcode == kX86Jmp8) {

470

return 2; // opcode + rel8

471

} else if (lir->opcode == kX86Jmp32) {

472

return 5; // opcode + rel32

473

} else {

474

DCHECK(lir->opcode == kX86JmpR);

475

return 2; // opcode + modrm

476

}

477

case kCall:

478

switch (lir->opcode) {

479

case kX86CallR: return 2; // opcode modrm

480

case kX86CallM: // lir operands - 0: base, 1: disp

481

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

482

case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

483

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

484

case kX86CallT: // lir operands - 0: disp

485

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

default:

break;

}

break;

case kPcRel:

if (entry->opcode == kX86PcRelLoadRA) {

492

// lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

493

return ComputeSize(entry, lir->operands[1], 0x12345678, true);

494

} else {

495

DCHECK(entry->opcode == kX86PcRelAdr);

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

496

return 5; // opcode with reg + 4 byte immediate

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

497

}

498

case kMacro:

499

DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));

500

return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +

501

ComputeSize(&X86Mir2Lir::EncodingMap[kX86Sub32RI], 0, 0, false) -

502

(lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

return 0;

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

510

void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry) {

511

if (entry->skeleton.prefix1 != 0) {

512

code_buffer_.push_back(entry->skeleton.prefix1);

513

if (entry->skeleton.prefix2 != 0) {

514

code_buffer_.push_back(entry->skeleton.prefix2);

515

}

516

} else {

517

DCHECK_EQ(0, entry->skeleton.prefix2);

}

}

void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) {

522

code_buffer_.push_back(entry->skeleton.opcode);

523

if (entry->skeleton.opcode == 0x0F) {

524

code_buffer_.push_back(entry->skeleton.extra_opcode1);

525

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

526

code_buffer_.push_back(entry->skeleton.extra_opcode2);

527

} else {

528

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

529

}

530

} else {

531

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

532

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

}

}

void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry) {

EmitPrefix(entry);

EmitOpcode(entry);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

541

static uint8_t ModrmForDisp(int base, int disp) {

542

// BP requires an explicit disp, so do not omit it in the 0 case

543

if (disp == 0 && base != rBP) {

544

return 0;

545

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

552

void X86Mir2Lir::EmitDisp(uint8_t base, int disp) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

553

// BP requires an explicit disp, so do not omit it in the 0 case

554

if (disp == 0 && base != rBP) {

555

return;

556

} else if (IS_SIMM8(disp)) {

557

code_buffer_.push_back(disp & 0xFF);

558

} else {

559

code_buffer_.push_back(disp & 0xFF);

560

code_buffer_.push_back((disp >> 8) & 0xFF);

561

code_buffer_.push_back((disp >> 16) & 0xFF);

562

code_buffer_.push_back((disp >> 24) & 0xFF);

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

566

void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp) {

567

DCHECK_LT(reg_or_opcode, 8);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

568

DCHECK_LT(base, 8);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

569

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | base;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

570

code_buffer_.push_back(modrm);

571

if (base == rX86_SP) {

572

// Special SIB for SP base

573

code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);

574

}

575

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

576

}

577

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

578

void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index,

579

int scale, int disp) {

580

DCHECK_LT(reg_or_opcode, 8);

581

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | rX86_SP;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

582

code_buffer_.push_back(modrm);

DCHECK_LT(scale, 4);

DCHECK_LT(index, 8);

DCHECK_LT(base, 8);

uint8_t sib = (scale << 6) | (index << 3) | base;

587

code_buffer_.push_back(sib);

588

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

589

}

590

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

591

void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int imm) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

592

switch (entry->skeleton.immediate_bytes) {

593

case 1:

594

DCHECK(IS_SIMM8(imm));

595

code_buffer_.push_back(imm & 0xFF);

596

break;

597

case 2:

598

DCHECK(IS_SIMM16(imm));

599

code_buffer_.push_back(imm & 0xFF);

600

code_buffer_.push_back((imm >> 8) & 0xFF);

601

break;

602

case 4:

603

code_buffer_.push_back(imm & 0xFF);

604

code_buffer_.push_back((imm >> 8) & 0xFF);

605

code_buffer_.push_back((imm >> 16) & 0xFF);

606

code_buffer_.push_back((imm >> 24) & 0xFF);

607

break;

608

default:

609

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

610

<< ") for instruction: " << entry->name;

break;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

615

void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg) {

616

EmitPrefixAndOpcode(entry);

617

// There's no 3-byte instruction with +rd

618

DCHECK(entry->skeleton.opcode != 0x0F ||

619

(entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A));

620

DCHECK(!X86_FPREG(reg));

621

DCHECK_LT(reg, 8);

622

code_buffer_.back() += reg;

623

DCHECK_EQ(0, entry->skeleton.ax_opcode);

624

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

625

}

626

627

void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) {

628

EmitPrefixAndOpcode(entry);

629

if (X86_FPREG(reg)) {

630

reg = reg & X86_FP_REG_MASK;

631

}

632

if (reg >= 4) {

633

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

634

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

635

}

636

DCHECK_LT(reg, 8);

637

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

638

code_buffer_.push_back(modrm);

639

DCHECK_EQ(0, entry->skeleton.ax_opcode);

640

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

641

}

642

643

void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) {

644

EmitPrefix(entry);

645

code_buffer_.push_back(entry->skeleton.opcode);

646

DCHECK_NE(0x0F, entry->skeleton.opcode);

647

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

648

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

649

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

650

DCHECK_EQ(0, entry->skeleton.ax_opcode);

651

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

652

}

653

654

void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index,

655

int scale, int disp) {

656

EmitPrefixAndOpcode(entry);

657

EmitModrmSibDisp(entry->skeleton.modrm_opcode, base, index, scale, disp);

658

DCHECK_EQ(0, entry->skeleton.ax_opcode);

659

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

660

}

661

662

void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry,

663

uint8_t base, int disp, uint8_t reg) {

664

EmitPrefixAndOpcode(entry);

665

if (X86_FPREG(reg)) {

666

reg = reg & X86_FP_REG_MASK;

667

}

668

if (reg >= 4) {

669

DCHECK(strchr(entry->name, '8') == NULL ||

670

entry->opcode == kX86Movzx8RM || entry->opcode == kX86Movsx8RM)

671

<< entry->name << " " << static_cast<int>(reg)

672

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

673

}

674

EmitModrmDisp(reg, base, disp);

675

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

676

DCHECK_EQ(0, entry->skeleton.ax_opcode);

677

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

678

}

679

680

void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry,

681

uint8_t reg, uint8_t base, int disp) {

682

// Opcode will flip operands.

683

EmitMemReg(entry, base, disp, reg);

684

}

685

686

void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index,

687

int scale, int disp) {

688

EmitPrefixAndOpcode(entry);

689

if (X86_FPREG(reg)) {

690

reg = reg & X86_FP_REG_MASK;

691

}

692

EmitModrmSibDisp(reg, base, index, scale, disp);

693

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

694

DCHECK_EQ(0, entry->skeleton.ax_opcode);

695

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

696

}

697

698

void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp,

699

uint8_t reg) {

700

// Opcode will flip operands.

701

EmitRegArray(entry, reg, base, index, scale, disp);

702

}

703

704

void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) {

705

DCHECK_NE(entry->skeleton.prefix1, 0);

706

EmitPrefixAndOpcode(entry);

707

if (X86_FPREG(reg)) {

708

reg = reg & X86_FP_REG_MASK;

709

}

710

if (reg >= 4) {

711

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

712

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

713

}

714

DCHECK_LT(reg, 8);

715

uint8_t modrm = (0 << 6) | (reg << 3) | rBP;

716

code_buffer_.push_back(modrm);

717

code_buffer_.push_back(disp & 0xFF);

718

code_buffer_.push_back((disp >> 8) & 0xFF);

719

code_buffer_.push_back((disp >> 16) & 0xFF);

720

code_buffer_.push_back((disp >> 24) & 0xFF);

721

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

722

DCHECK_EQ(0, entry->skeleton.ax_opcode);

723

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

724

}

725

726

void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) {

727

EmitPrefixAndOpcode(entry);

728

if (X86_FPREG(reg1)) {

729

reg1 = reg1 & X86_FP_REG_MASK;

730

}

731

if (X86_FPREG(reg2)) {

732

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

737

code_buffer_.push_back(modrm);

738

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

739

DCHECK_EQ(0, entry->skeleton.ax_opcode);

740

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

741

}

742

743

void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry,

744

uint8_t reg1, uint8_t reg2, int32_t imm) {

745

EmitPrefixAndOpcode(entry);

746

if (X86_FPREG(reg1)) {

747

reg1 = reg1 & X86_FP_REG_MASK;

748

}

749

if (X86_FPREG(reg2)) {

750

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

755

code_buffer_.push_back(modrm);

756

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

757

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

761

void X86Mir2Lir::EmitRegRegImmRev(const X86EncodingMap* entry,

762

uint8_t reg1, uint8_t reg2, int32_t imm) {

763

EmitRegRegImm(entry, reg2, reg1, imm);

764

}

765

766

void X86Mir2Lir::EmitRegMemImm(const X86EncodingMap* entry,

767

uint8_t reg, uint8_t base, int disp, int32_t imm) {

768

EmitPrefixAndOpcode(entry);

769

DCHECK(!X86_FPREG(reg));

770

DCHECK_LT(reg, 8);

771

EmitModrmDisp(reg, base, disp);

772

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

773

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

777

void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

778

if (entry->skeleton.prefix1 != 0) {

779

code_buffer_.push_back(entry->skeleton.prefix1);

780

if (entry->skeleton.prefix2 != 0) {

781

code_buffer_.push_back(entry->skeleton.prefix2);

782

}

783

} else {

784

DCHECK_EQ(0, entry->skeleton.prefix2);

785

}

786

if (reg == rAX && entry->skeleton.ax_opcode != 0) {

787

code_buffer_.push_back(entry->skeleton.ax_opcode);

788

} else {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

789

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

790

if (X86_FPREG(reg)) {

791

reg = reg & X86_FP_REG_MASK;

792

}

793

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

794

code_buffer_.push_back(modrm);

795

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

796

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

797

}

798

Mark Mendell

343adb5

2013-12-18 06:02:17 -0800

[diff] [blame]

799

void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm) {

800

EmitPrefixAndOpcode(entry);

801

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

802

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

806

void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

807

EmitPrefixAndOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

808

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

809

code_buffer_.push_back(modrm);

810

code_buffer_.push_back(disp & 0xFF);

811

code_buffer_.push_back((disp >> 8) & 0xFF);

812

code_buffer_.push_back((disp >> 16) & 0xFF);

813

code_buffer_.push_back((disp >> 24) & 0xFF);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

814

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

815

DCHECK_EQ(entry->skeleton.ax_opcode, 0);

816

}

817

818

void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

819

DCHECK_LT(reg, 8);

820

code_buffer_.push_back(0xB8 + reg);

821

code_buffer_.push_back(imm & 0xFF);

822

code_buffer_.push_back((imm >> 8) & 0xFF);

823

code_buffer_.push_back((imm >> 16) & 0xFF);

824

code_buffer_.push_back((imm >> 24) & 0xFF);

825

}

826

827

void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

828

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

829

if (imm != 1) {

830

code_buffer_.push_back(entry->skeleton.opcode);

831

} else {

832

// Shorter encoding for 1 bit shift

833

code_buffer_.push_back(entry->skeleton.ax_opcode);

834

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

835

DCHECK_NE(0x0F, entry->skeleton.opcode);

836

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

837

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

838

if (reg >= 4) {

839

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

840

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

841

}

842

DCHECK_LT(reg, 8);

843

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

844

code_buffer_.push_back(modrm);

845

if (imm != 1) {

846

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

847

DCHECK(IS_SIMM8(imm));

848

code_buffer_.push_back(imm & 0xFF);

}

}

void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl) {

853

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

854

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

855

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

856

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

857

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

858

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

859

DCHECK_LT(reg, 8);

860

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

861

code_buffer_.push_back(modrm);

862

DCHECK_EQ(0, entry->skeleton.ax_opcode);

863

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

864

}

865

Mark Mendell

feb2b4e

2014-01-28 12:59:49 -0800

[diff] [blame]

866

void X86Mir2Lir::EmitShiftMemCl(const X86EncodingMap* entry, uint8_t base,

867

int displacement, uint8_t cl) {

868

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

869

EmitPrefix(entry);

870

code_buffer_.push_back(entry->skeleton.opcode);

871

DCHECK_NE(0x0F, entry->skeleton.opcode);

872

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

873

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

874

DCHECK_LT(base, 8);

875

EmitModrmDisp(entry->skeleton.modrm_opcode, base, displacement);

876

DCHECK_EQ(0, entry->skeleton.ax_opcode);

877

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

878

}

879

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

880

void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) {

881

if (entry->skeleton.prefix1 != 0) {

882

code_buffer_.push_back(entry->skeleton.prefix1);

883

if (entry->skeleton.prefix2 != 0) {

884

code_buffer_.push_back(entry->skeleton.prefix2);

885

}

886

} else {

887

DCHECK_EQ(0, entry->skeleton.prefix2);

888

}

889

DCHECK_EQ(0, entry->skeleton.ax_opcode);

890

DCHECK_EQ(0x0F, entry->skeleton.opcode);

891

code_buffer_.push_back(0x0F);

892

DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);

893

code_buffer_.push_back(0x90 | condition);

894

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

895

DCHECK_LT(reg, 8);

896

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

897

code_buffer_.push_back(modrm);

898

DCHECK_EQ(entry->skeleton.immediate_bytes, 0);

899

}

900

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

901

void X86Mir2Lir::EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, uint8_t condition) {

902

// Generate prefix and opcode without the condition

903

EmitPrefixAndOpcode(entry);

904

905

// Now add the condition. The last byte of opcode is the one that receives it.

906

DCHECK_LE(condition, 0xF);

907

code_buffer_.back() += condition;

908

909

// Not expecting to have to encode immediate or do anything special for ModR/M since there are two registers.

910

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

911

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

912

913

// Check that registers requested for encoding are sane.

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

// For register to register encoding, the mod is 3.

918

const uint8_t mod = (3 << 6);

919

920

// Encode the ModR/M byte now.

921

const uint8_t modrm = mod | (reg1 << 3) | reg2;

922

code_buffer_.push_back(modrm);

923

}

924

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

925

void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int rel) {

926

if (entry->opcode == kX86Jmp8) {

927

DCHECK(IS_SIMM8(rel));

928

code_buffer_.push_back(0xEB);

929

code_buffer_.push_back(rel & 0xFF);

930

} else if (entry->opcode == kX86Jmp32) {

931

code_buffer_.push_back(0xE9);

932

code_buffer_.push_back(rel & 0xFF);

933

code_buffer_.push_back((rel >> 8) & 0xFF);

934

code_buffer_.push_back((rel >> 16) & 0xFF);

935

code_buffer_.push_back((rel >> 24) & 0xFF);

936

} else {

937

DCHECK(entry->opcode == kX86JmpR);

938

code_buffer_.push_back(entry->skeleton.opcode);

939

uint8_t reg = static_cast<uint8_t>(rel);

940

DCHECK_LT(reg, 8);

941

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

942

code_buffer_.push_back(modrm);

}

}

void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc) {

947

DCHECK_LT(cc, 16);

948

if (entry->opcode == kX86Jcc8) {

949

DCHECK(IS_SIMM8(rel));

950

code_buffer_.push_back(0x70 | cc);

951

code_buffer_.push_back(rel & 0xFF);

952

} else {

953

DCHECK(entry->opcode == kX86Jcc32);

954

code_buffer_.push_back(0x0F);

955

code_buffer_.push_back(0x80 | cc);

956

code_buffer_.push_back(rel & 0xFF);

957

code_buffer_.push_back((rel >> 8) & 0xFF);

958

code_buffer_.push_back((rel >> 16) & 0xFF);

959

code_buffer_.push_back((rel >> 24) & 0xFF);

}

}

void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

964

EmitPrefixAndOpcode(entry);

965

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

966

DCHECK_EQ(0, entry->skeleton.ax_opcode);

967

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

968

}

969

970

void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int disp) {

971

DCHECK_NE(entry->skeleton.prefix1, 0);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

972

EmitPrefixAndOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

973

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

974

code_buffer_.push_back(modrm);

975

code_buffer_.push_back(disp & 0xFF);

976

code_buffer_.push_back((disp >> 8) & 0xFF);

977

code_buffer_.push_back((disp >> 16) & 0xFF);

978

code_buffer_.push_back((disp >> 24) & 0xFF);

979

DCHECK_EQ(0, entry->skeleton.ax_opcode);

980

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

981

}

982

983

void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, uint8_t reg,

984

int base_or_table, uint8_t index, int scale, int table_or_disp) {

985

int disp;

986

if (entry->opcode == kX86PcRelLoadRA) {

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

987

Mir2Lir::EmbeddedData *tab_rec =

988

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

989

disp = tab_rec->offset;

990

} else {

991

DCHECK(entry->opcode == kX86PcRelAdr);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

992

Mir2Lir::EmbeddedData *tab_rec =

993

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(base_or_table));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

994

disp = tab_rec->offset;

995

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

996

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

997

if (X86_FPREG(reg)) {

998

reg = reg & X86_FP_REG_MASK;

999

}

1000

DCHECK_LT(reg, 8);

1001

if (entry->opcode == kX86PcRelLoadRA) {

1002

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1003

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1004

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1005

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1006

uint8_t modrm = (2 << 6) | (reg << 3) | rX86_SP;

1007

code_buffer_.push_back(modrm);

1008

DCHECK_LT(scale, 4);

1009

DCHECK_LT(index, 8);

1010

DCHECK_LT(base_or_table, 8);

1011

uint8_t base = static_cast<uint8_t>(base_or_table);

1012

uint8_t sib = (scale << 6) | (index << 3) | base;

1013

code_buffer_.push_back(sib);

1014

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1015

} else {

1016

code_buffer_.push_back(entry->skeleton.opcode + reg);

1017

}

1018

code_buffer_.push_back(disp & 0xFF);

1019

code_buffer_.push_back((disp >> 8) & 0xFF);

1020

code_buffer_.push_back((disp >> 16) & 0xFF);

1021

code_buffer_.push_back((disp >> 24) & 0xFF);

1022

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1023

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1024

}

1025

1026

void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset) {

1027

DCHECK(entry->opcode == kX86StartOfMethod) << entry->name;

1028

code_buffer_.push_back(0xE8); // call +0

1029

code_buffer_.push_back(0);

1030

code_buffer_.push_back(0);

1031

code_buffer_.push_back(0);

1032

code_buffer_.push_back(0);

1033

1034

DCHECK_LT(reg, 8);

1035

code_buffer_.push_back(0x58 + reg); // pop reg

1036

1037

EmitRegImm(&X86Mir2Lir::EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */);

1038

}

1039

1040

void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) {

1041

UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " "

1042

<< BuildInsnString(entry->fmt, lir, 0);

1043

for (int i = 0; i < GetInsnSize(lir); ++i) {

1044

code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3

}

}

/*

* Assemble the LIR into binary instruction format. Note that we may

1050

* discover that pc-relative displacements may not fit the selected

1051

* instruction. In those cases we will try to substitute a new code

1052

* sequence or request that the trace be shortened and retried.

1053

*/

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1054

AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1055

LIR *lir;

1056

AssemblerStatus res = kSuccess; // Assume success

1057

1058

const bool kVerbosePcFixup = false;

1059

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1060

if (IsPseudoLirOp(lir->opcode)) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

continue;

}

if (lir->flags.is_nop) {

continue;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1068

if (lir->flags.fixup != kFixupNone) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1069

switch (lir->opcode) {

1070

case kX86Jcc8: {

1071

LIR *target_lir = lir->target;

1072

DCHECK(target_lir != NULL);

1073

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1074

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1075

if (IS_SIMM8(lir->operands[0])) {

1076

pc = lir->offset + 2 /* opcode + rel8 */;

1077

} else {

1078

pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1079

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1080

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1081

delta = target - pc;

1082

if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1083

if (kVerbosePcFixup) {

1084

LOG(INFO) << "Retry for JCC growth at " << lir->offset

1085

<< " delta: " << delta << " old delta: " << lir->operands[0];

1086

}

1087

lir->opcode = kX86Jcc32;

1088

SetupResourceMasks(lir);

1089

res = kRetryAll;

1090

}

1091

if (kVerbosePcFixup) {

1092

LOG(INFO) << "Source:";

1093

DumpLIRInsn(lir, 0);

1094

LOG(INFO) << "Target:";

1095

DumpLIRInsn(target_lir, 0);

1096

LOG(INFO) << "Delta " << delta;

1097

}

1098

lir->operands[0] = delta;

break;

}

case kX86Jcc32: {

LIR *target_lir = lir->target;

1103

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1104

CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1105

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1106

int delta = target - pc;

1107

if (kVerbosePcFixup) {

1108

LOG(INFO) << "Source:";

1109

DumpLIRInsn(lir, 0);

1110

LOG(INFO) << "Target:";

1111

DumpLIRInsn(target_lir, 0);

1112

LOG(INFO) << "Delta " << delta;

1113

}

1114

lir->operands[0] = delta;

break;

}

case kX86Jmp8: {

LIR *target_lir = lir->target;

1119

DCHECK(target_lir != NULL);

1120

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1121

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1122

if (IS_SIMM8(lir->operands[0])) {

1123

pc = lir->offset + 2 /* opcode + rel8 */;

1124

} else {

1125

pc = lir->offset + 5 /* opcode + rel32 */;

1126

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1127

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1128

delta = target - pc;

1129

if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) {

1130

// Useless branch

buzbee

252254b

2013-09-08 16:20:53 -0700

[diff] [blame]

1131

NopLIR(lir);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1132

if (kVerbosePcFixup) {

1133

LOG(INFO) << "Retry for useless branch at " << lir->offset;

1134

}

1135

res = kRetryAll;

1136

} else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1137

if (kVerbosePcFixup) {

1138

LOG(INFO) << "Retry for JMP growth at " << lir->offset;

1139

}

1140

lir->opcode = kX86Jmp32;

1141

SetupResourceMasks(lir);

1142

res = kRetryAll;

1143

}

1144

lir->operands[0] = delta;

break;

}

case kX86Jmp32: {

LIR *target_lir = lir->target;

1149

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1150

CodeOffset pc = lir->offset + 5 /* opcode + rel32 */;

1151

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1152

int delta = target - pc;

1153

lir->operands[0] = delta;

1154

break;

1155

}

1156

default:

Mark Mendell

67c39c4

2014-01-31 17:28:00 -0800

[diff] [blame^]

1157

if (lir->flags.fixup == kFixupLoad) {

1158

LIR *target_lir = lir->target;

1159

DCHECK(target_lir != NULL);

1160

CodeOffset target = target_lir->offset;

1161

lir->operands[2] = target;

1162

int newSize = GetInsnSize(lir);

1163

if (newSize != lir->flags.size) {

1164

lir->flags.size = newSize;

1165

res = kRetryAll;

1166

}

1167

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

break;

}

}

/*

* If one of the pc-relative instructions expanded we'll have

1174

* to make another pass. Don't bother to fully assemble the

1175

* instruction.

1176

*/

1177

if (res != kSuccess) {

1178

continue;

1179

}

1180

CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size());

1181

const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode];

1182

size_t starting_cbuf_size = code_buffer_.size();

1183

switch (entry->kind) {

1184

case kData: // 4 bytes of data

1185

code_buffer_.push_back(lir->operands[0]);

1186

break;

1187

case kNullary: // 1 byte of opcode

1188

DCHECK_EQ(0, entry->skeleton.prefix1);

1189

DCHECK_EQ(0, entry->skeleton.prefix2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1190

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1191

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1192

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1193

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1194

break;

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

1195

case kRegOpcode: // lir operands - 0: reg

1196

EmitOpRegOpcode(entry, lir->operands[0]);

1197

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1198

case kReg: // lir operands - 0: reg

1199

EmitOpReg(entry, lir->operands[0]);

1200

break;

1201

case kMem: // lir operands - 0: base, 1: disp

1202

EmitOpMem(entry, lir->operands[0], lir->operands[1]);

1203

break;

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1204

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

1205

EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]);

1206

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1207

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

1208

EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1209

break;

Mark Mendell

343adb5

2013-12-18 06:02:17 -0800

[diff] [blame]

1210

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

1211

EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1212

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1213

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

1214

EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1215

lir->operands[3], lir->operands[4]);

1216

break;

1217

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

1218

EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1219

break;

1220

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

1221

EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1222

lir->operands[3], lir->operands[4]);

1223

break;

1224

case kRegThread: // lir operands - 0: reg, 1: disp

1225

EmitRegThread(entry, lir->operands[0], lir->operands[1]);

1226

break;

1227

case kRegReg: // lir operands - 0: reg1, 1: reg2

1228

EmitRegReg(entry, lir->operands[0], lir->operands[1]);

1229

break;

1230

case kRegRegStore: // lir operands - 0: reg2, 1: reg1

1231

EmitRegReg(entry, lir->operands[1], lir->operands[0]);

1232

break;

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

1233

case kRegRegImmRev:

1234

EmitRegRegImmRev(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1235

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1236

case kRegRegImm:

1237

EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1238

break;

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

1239

case kRegMemImm:

1240

EmitRegMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1241

lir->operands[3]);

1242

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1243

case kRegImm: // lir operands - 0: reg, 1: immediate

1244

EmitRegImm(entry, lir->operands[0], lir->operands[1]);

1245

break;

1246

case kThreadImm: // lir operands - 0: disp, 1: immediate

1247

EmitThreadImm(entry, lir->operands[0], lir->operands[1]);

1248

break;

1249

case kMovRegImm: // lir operands - 0: reg, 1: immediate

1250

EmitMovRegImm(entry, lir->operands[0], lir->operands[1]);

1251

break;

1252

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

1253

EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]);

1254

break;

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

1255

case kShiftRegCl: // lir operands - 0: reg, 1: cl

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1256

EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]);

1257

break;

Mark Mendell

feb2b4e

2014-01-28 12:59:49 -0800

[diff] [blame]

1258

case kShiftMemCl: // lir operands - 0: base, 1:displacement, 2: cl

1259

EmitShiftMemCl(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1260

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1261

case kRegCond: // lir operands - 0: reg, 1: condition

1262

EmitRegCond(entry, lir->operands[0], lir->operands[1]);

1263

break;

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

1264

case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: condition

1265

EmitRegRegCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1266

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1267

case kJmp: // lir operands - 0: rel

1268

EmitJmp(entry, lir->operands[0]);

1269

break;

1270

case kJcc: // lir operands - 0: rel, 1: CC, target assigned

1271

EmitJcc(entry, lir->operands[0], lir->operands[1]);

1272

break;

1273

case kCall:

1274

switch (entry->opcode) {

1275

case kX86CallM: // lir operands - 0: base, 1: disp

1276

EmitCallMem(entry, lir->operands[0], lir->operands[1]);

1277

break;

1278

case kX86CallT: // lir operands - 0: disp

1279

EmitCallThread(entry, lir->operands[0]);

1280

break;

1281

default:

1282

EmitUnimplemented(entry, lir);

break;

}

break;

case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

1287

EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1288

lir->operands[3], lir->operands[4]);

1289

break;

1290

case kMacro:

1291

EmitMacro(entry, lir->operands[0], lir->offset);

1292

break;

1293

default:

1294

EmitUnimplemented(entry, lir);

1295

break;

1296

}

1297

CHECK_EQ(static_cast<size_t>(GetInsnSize(lir)),

1298

code_buffer_.size() - starting_cbuf_size)

1299

<< "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name;

}

return res;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1304

// LIR offset assignment.

1305

// TODO: consolidate w/ Arm assembly mechanism.

1306

int X86Mir2Lir::AssignInsnOffsets() {

LIR* lir;

int offset = 0;

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

1311

lir->offset = offset;

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1312

if (LIKELY(!IsPseudoLirOp(lir->opcode))) {

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1313

if (!lir->flags.is_nop) {

1314

offset += lir->flags.size;

1315

}

1316

} else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) {

1317

if (offset & 0x2) {

1318

offset += 2;

1319

lir->operands[0] = 1;

1320

} else {

1321

lir->operands[0] = 0;

1322

}

1323

}

1324

/* Pseudo opcodes don't consume space */

}

return offset;

}

/*

* Walk the compilation unit and assign offsets to instructions

1331

* and literals and compute the total size of the compiled unit.

1332

* TODO: consolidate w/ Arm assembly mechanism.

1333

*/

1334

void X86Mir2Lir::AssignOffsets() {

1335

int offset = AssignInsnOffsets();

1336

1337

/* Const values have to be word aligned */

1338

offset = (offset + 3) & ~3;

1339

1340

/* Set up offsets for literals */

1341

data_offset_ = offset;

1342

1343

offset = AssignLiteralOffset(offset);

1344

1345

offset = AssignSwitchTablesOffset(offset);

1346

1347

offset = AssignFillArrayDataOffset(offset);

1348

1349

total_size_ = offset;

}

/*

* Go over each instruction in the list and calculate the offset from the top

1354

* before sending them off to the assembler. If out-of-range branch distance is

1355

* seen rearrange the instructions a bit to correct it.

1356

* TODO: consolidate w/ Arm assembly mechanism.

1357

*/

1358

void X86Mir2Lir::AssembleLIR() {

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1359

cu_->NewTimingSplit("Assemble");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1360

AssignOffsets();

1361

int assembler_retries = 0;

1362

/*

1363

* Assemble here. Note that we generate code with optimistic assumptions

1364

* and if found now to work, we'll have to redo the sequence and retry.

*/

while (true) {

AssemblerStatus res = AssembleInstructions(0);

1369

if (res == kSuccess) {

break;

} else {

assembler_retries++;

if (assembler_retries > MAX_ASSEMBLER_RETRIES) {

1374

CodegenDump();

1375

LOG(FATAL) << "Assembler error - too many retries";

1376

}

1377

// Redo offsets and try again

1378

AssignOffsets();

1379

code_buffer_.clear();

}

}

// Install literals

InstallLiteralPools();

1385

1386

// Install switch tables

1387

InstallSwitchTables();

1388

1389

// Install fill array data

1390

InstallFillArrayData();

1391

1392

// Create the mapping table and native offset to reference map.

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1393

cu_->NewTimingSplit("PcMappingTable");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1394

CreateMappingTables();

1395

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1396

cu_->NewTimingSplit("GcMap");

buzbee