Blame - compiler/dex/quick/x86/assemble_x86.cc - platform_art

2013-12-20 17:27:23 -0800

[diff] [blame]

180

{ kX86Cmov32RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, {0, 0, 0x0F, 0x40, 0, 0, 0, 0}, "Cmovcc32RR", "!2c !0r,!1r" },

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Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \

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{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \

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{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \

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{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \

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{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }

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SHIFT_ENCODING_MAP(Rol, 0x0),

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SHIFT_ENCODING_MAP(Ror, 0x1),

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SHIFT_ENCODING_MAP(Rcl, 0x2),

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SHIFT_ENCODING_MAP(Rcr, 0x3),

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SHIFT_ENCODING_MAP(Sal, 0x4),

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SHIFT_ENCODING_MAP(Shr, 0x5),

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SHIFT_ENCODING_MAP(Sar, 0x7),

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#undef SHIFT_ENCODING_MAP

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{ kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0}, "Cmc", "" },

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

214

{ kX86Shld32RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1}, "Shld32", "!0r,!1r,!2d" },

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{ kX86Shrd32RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1}, "Shrd32", "!0r,!1r,!2d" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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{ kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" },

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{ kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" },

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{ kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" },

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{ kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" },

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{ kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" },

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{ kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" },

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{ kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0}, "Test32RR", "!0r,!1r" },

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#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \

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reg, reg_kind, reg_flags, \

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mem, mem_kind, mem_flags, \

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arr, arr_kind, arr_flags, imm, \

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b_flags, hw_flags, w_flags, \

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b_format, hw_format, w_format) \

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{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, #b_format "!0r" }, \

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{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, #b_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, #b_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, #hw_format "!0r" }, \

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{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, #hw_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, #hw_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, #w_format "!0r" }, \

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{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, #w_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, #w_format "[!0r+!1r<<!2d+!3d]" }

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UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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Mark Mendell

2bf31e6

2014-01-23 12:13:40 -0800

[diff] [blame]

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UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

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UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#undef UNARY_ENCODING_MAP

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Mark Mendell

2bf31e6

2014-01-23 12:13:40 -0800

[diff] [blame]

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{ kx86Cdq32Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { 0, 0, 0x99, 0, 0, 0, 0, 0 }, "Cdq", "" },

Vladimir Marko

a6fd8ba

2013-12-13 10:53:49 +0000

[diff] [blame]

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{ kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0 }, "Bswap32R", "!0r" },

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{ kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0 }, "Push32R", "!0r" },

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{ kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0 }, "Pop32R", "!0r" },

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

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Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \

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{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

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{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

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EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),

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{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

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{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),

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{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

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{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0),

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EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0),

Razvan A Lupusoru

d3266bc

2014-01-24 12:55:31 -0800

[diff] [blame]

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EXT_0F_ENCODING_MAP(Punpckldq, 0x66, 0x62, REG_DEF0),

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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{ kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" },

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{ kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" },

Mark Mendell

bff1ef0

2013-12-13 13:47:34 -0800

[diff] [blame]

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{ kX86SqrtsdRR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0xF2, 0, 0x0F, 0x51, 0, 0, 0, 0 }, "SqrtsdRR", "!0r,!1r" },

Vladimir Marko

12f9628

2013-12-16 14:44:03 +0000

[diff] [blame]

298

{ kX86FstpdM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0 }, "FstpdM", "[!0r,!1d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

299

Razvan A Lupusoru

2c498d1

2014-01-29 16:02:57 -0800

[diff] [blame]

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EXT_0F_ENCODING_MAP(Movups, 0x0, 0x10, REG_DEF0),

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{ kX86MovupsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovupsMR", "[!0r+!1d],!2r" },

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{ kX86MovupsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovupsAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movaps, 0x0, 0x28, REG_DEF0),

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{ kX86MovapsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0 }, "MovapsMR", "[!0r+!1d],!2r" },

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{ kX86MovapsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0 }, "MovapsAR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86MovlpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0 }, "MovlpsRM", "!0r,[!1r+!2d]" },

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{ kX86MovlpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0 }, "MovlpsRA", "!0r,[!1r+!2r<<!3d+!4d]" },

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{ kX86MovlpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0 }, "MovlpsMR", "[!0r+!1d],!2r" },

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{ kX86MovlpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0 }, "MovlpsAR", "[!0r+!1r<<!2d+!3d],!4r" },

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{ kX86MovhpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0 }, "MovhpsRM", "!0r,[!1r+!2d]" },

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{ kX86MovhpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0 }, "MovhpsRA", "!0r,[!1r+!2r<<!3d+!4d]" },

315

{ kX86MovhpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0 }, "MovhpsMR", "[!0r+!1d],!2r" },

316

{ kX86MovhpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0 }, "MovhpsAR", "[!0r+!1r<<!2d+!3d],!4r" },

317

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

318

EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),

319

{ kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" },

320

{ kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" },

321

{ kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },

322

323

{ kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

324

{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

325

{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

326

327

// TODO: load/store?

328

// Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.

329

{ kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },

330

331

EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES),

332

EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES),

333

334

{ kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" },

335

{ kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" },

336

{ kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

337

{ kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" },

338

{ kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Vladimir Marko

70b797d

2013-12-03 15:25:24 +0000

[diff] [blame]

339

{ kX86LockCmpxchg8bM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1d]" },

340

{ kX86LockCmpxchg8bA, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

341

342

EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),

343

EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),

344

EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),

345

EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),

346

#undef EXT_0F_ENCODING_MAP

347

348

{ kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },

349

{ kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },

350

{ kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },

351

{ kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },

352

{ kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" },

353

{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

354

{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

355

{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

356

{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame^]

357

{ kX86CallI, kCall, IS_UNARY_OP | IS_BRANCH, { 0, 0, 0xE8, 0, 0, 0, 0, 4 }, "CallI", "!0d" },

Brian Carlstrom

b1eba21

2013-07-17 18:07:19 -0700

[diff] [blame]

358

{ kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

359

360

{ kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" },

361

{ kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },

362

{ kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" },

363

};

364

365

static size_t ComputeSize(const X86EncodingMap* entry, int base, int displacement, bool has_sib) {

366

size_t size = 0;

367

if (entry->skeleton.prefix1 > 0) {

368

++size;

369

if (entry->skeleton.prefix2 > 0) {

++size;

}

}

++size; // opcode

if (entry->skeleton.opcode == 0x0F) {

375

++size;

376

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

if (has_sib || base == rX86_SP) {

382

// SP requires a SIB byte.

383

++size;

384

}

385

if (displacement != 0 || base == rBP) {

386

// BP requires an explicit displacement, even when it's 0.

387

if (entry->opcode != kX86Lea32RA) {

388

DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name;

389

}

390

size += IS_SIMM8(displacement) ? 1 : 4;

391

}

392

size += entry->skeleton.immediate_bytes;

return size;

}

int X86Mir2Lir::GetInsnSize(LIR* lir) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

397

DCHECK(!IsPseudoLirOp(lir->opcode));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

398

const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode];

399

switch (entry->kind) {

400

case kData:

401

return 4; // 4 bytes of data

402

case kNop:

403

return lir->operands[0]; // length of nop is sole operand

404

case kNullary:

405

return 1; // 1 byte of opcode

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

406

case kRegOpcode: // lir operands - 0: reg

407

return ComputeSize(entry, 0, 0, false) - 1; // substract 1 for modrm

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

408

case kReg: // lir operands - 0: reg

409

return ComputeSize(entry, 0, 0, false);

410

case kMem: // lir operands - 0: base, 1: disp

411

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

412

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

413

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

414

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

415

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

416

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

417

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

418

case kThreadReg: // lir operands - 0: disp, 1: reg

419

return ComputeSize(entry, 0, lir->operands[0], false);

420

case kRegReg:

421

return ComputeSize(entry, 0, 0, false);

422

case kRegRegStore:

423

return ComputeSize(entry, 0, 0, false);

424

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

425

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

426

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

427

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

428

case kRegThread: // lir operands - 0: reg, 1: disp

429

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

430

case kRegImm: { // lir operands - 0: reg, 1: immediate

431

size_t size = ComputeSize(entry, 0, 0, false);

432

if (entry->skeleton.ax_opcode == 0) {

433

return size;

434

} else {

435

// AX opcodes don't require the modrm byte.

436

int reg = lir->operands[0];

437

return size - (reg == rAX ? 1 : 0);

438

}

439

}

440

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

441

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

442

case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

443

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

444

case kThreadImm: // lir operands - 0: disp, 1: imm

445

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

446

case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

447

case kRegRegImmRev:

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

448

return ComputeSize(entry, 0, 0, false);

449

case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

450

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

451

case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

452

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

453

case kMovRegImm: // lir operands - 0: reg, 1: immediate

454

return 1 + entry->skeleton.immediate_bytes;

455

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

456

// Shift by immediate one has a shorter opcode.

457

return ComputeSize(entry, 0, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

458

case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

459

// Shift by immediate one has a shorter opcode.

460

return ComputeSize(entry, lir->operands[0], lir->operands[1], false) -

461

(lir->operands[2] == 1 ? 1 : 0);

462

case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

463

// Shift by immediate one has a shorter opcode.

464

return ComputeSize(entry, lir->operands[0], lir->operands[3], true) -

465

(lir->operands[4] == 1 ? 1 : 0);

466

case kShiftRegCl:

467

return ComputeSize(entry, 0, 0, false);

468

case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

469

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

470

case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

471

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

472

case kRegCond: // lir operands - 0: reg, 1: cond

473

return ComputeSize(entry, 0, 0, false);

474

case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

475

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

476

case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

477

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

478

case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: cond

479

return ComputeSize(entry, 0, 0, false);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

480

case kJcc:

481

if (lir->opcode == kX86Jcc8) {

482

return 2; // opcode + rel8

483

} else {

484

DCHECK(lir->opcode == kX86Jcc32);

485

return 6; // 2 byte opcode + rel32

486

}

487

case kJmp:

488

if (lir->opcode == kX86Jmp8) {

489

return 2; // opcode + rel8

490

} else if (lir->opcode == kX86Jmp32) {

491

return 5; // opcode + rel32

492

} else {

493

DCHECK(lir->opcode == kX86JmpR);

494

return 2; // opcode + modrm

495

}

496

case kCall:

497

switch (lir->opcode) {

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame^]

498

case kX86CallI: return 5; // opcode 0:disp

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

499

case kX86CallR: return 2; // opcode modrm

500

case kX86CallM: // lir operands - 0: base, 1: disp

501

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

502

case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

503

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

504

case kX86CallT: // lir operands - 0: disp

505

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

default:

break;

}

break;

case kPcRel:

if (entry->opcode == kX86PcRelLoadRA) {

512

// lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

513

return ComputeSize(entry, lir->operands[1], 0x12345678, true);

514

} else {

515

DCHECK(entry->opcode == kX86PcRelAdr);

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

516

return 5; // opcode with reg + 4 byte immediate

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

517

}

518

case kMacro:

519

DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));

520

return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +

521

ComputeSize(&X86Mir2Lir::EncodingMap[kX86Sub32RI], 0, 0, false) -

522

(lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

return 0;

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

530

void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry) {

531

if (entry->skeleton.prefix1 != 0) {

532

code_buffer_.push_back(entry->skeleton.prefix1);

533

if (entry->skeleton.prefix2 != 0) {

534

code_buffer_.push_back(entry->skeleton.prefix2);

535

}

536

} else {

537

DCHECK_EQ(0, entry->skeleton.prefix2);

}

}

void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) {

542

code_buffer_.push_back(entry->skeleton.opcode);

543

if (entry->skeleton.opcode == 0x0F) {

544

code_buffer_.push_back(entry->skeleton.extra_opcode1);

545

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

546

code_buffer_.push_back(entry->skeleton.extra_opcode2);

547

} else {

548

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

549

}

550

} else {

551

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

552

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

}

}

void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry) {

EmitPrefix(entry);

EmitOpcode(entry);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

561

static uint8_t ModrmForDisp(int base, int disp) {

562

// BP requires an explicit disp, so do not omit it in the 0 case

563

if (disp == 0 && base != rBP) {

564

return 0;

565

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

572

void X86Mir2Lir::EmitDisp(uint8_t base, int disp) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

573

// BP requires an explicit disp, so do not omit it in the 0 case

574

if (disp == 0 && base != rBP) {

575

return;

576

} else if (IS_SIMM8(disp)) {

577

code_buffer_.push_back(disp & 0xFF);

578

} else {

579

code_buffer_.push_back(disp & 0xFF);

580

code_buffer_.push_back((disp >> 8) & 0xFF);

581

code_buffer_.push_back((disp >> 16) & 0xFF);

582

code_buffer_.push_back((disp >> 24) & 0xFF);

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

586

void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp) {

587

DCHECK_LT(reg_or_opcode, 8);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

588

DCHECK_LT(base, 8);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

589

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | base;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

590

code_buffer_.push_back(modrm);

591

if (base == rX86_SP) {

592

// Special SIB for SP base

593

code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);

594

}

595

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

596

}

597

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

598

void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index,

599

int scale, int disp) {

600

DCHECK_LT(reg_or_opcode, 8);

601

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | rX86_SP;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

602

code_buffer_.push_back(modrm);

DCHECK_LT(scale, 4);

DCHECK_LT(index, 8);

DCHECK_LT(base, 8);

uint8_t sib = (scale << 6) | (index << 3) | base;

607

code_buffer_.push_back(sib);

608

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

609

}

610

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

611

void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int imm) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

612

switch (entry->skeleton.immediate_bytes) {

613

case 1:

614

DCHECK(IS_SIMM8(imm));

615

code_buffer_.push_back(imm & 0xFF);

616

break;

617

case 2:

618

DCHECK(IS_SIMM16(imm));

619

code_buffer_.push_back(imm & 0xFF);

620

code_buffer_.push_back((imm >> 8) & 0xFF);

621

break;

622

case 4:

623

code_buffer_.push_back(imm & 0xFF);

624

code_buffer_.push_back((imm >> 8) & 0xFF);

625

code_buffer_.push_back((imm >> 16) & 0xFF);

626

code_buffer_.push_back((imm >> 24) & 0xFF);

627

break;

628

default:

629

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

630

<< ") for instruction: " << entry->name;

break;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

635

void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg) {

636

EmitPrefixAndOpcode(entry);

637

// There's no 3-byte instruction with +rd

638

DCHECK(entry->skeleton.opcode != 0x0F ||

639

(entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A));

640

DCHECK(!X86_FPREG(reg));

641

DCHECK_LT(reg, 8);

642

code_buffer_.back() += reg;

643

DCHECK_EQ(0, entry->skeleton.ax_opcode);

644

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

645

}

646

647

void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) {

648

EmitPrefixAndOpcode(entry);

649

if (X86_FPREG(reg)) {

650

reg = reg & X86_FP_REG_MASK;

651

}

652

if (reg >= 4) {

653

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

654

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

655

}

656

DCHECK_LT(reg, 8);

657

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

658

code_buffer_.push_back(modrm);

659

DCHECK_EQ(0, entry->skeleton.ax_opcode);

660

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

661

}

662

663

void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) {

664

EmitPrefix(entry);

665

code_buffer_.push_back(entry->skeleton.opcode);

666

DCHECK_NE(0x0F, entry->skeleton.opcode);

667

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

668

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

669

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

670

DCHECK_EQ(0, entry->skeleton.ax_opcode);

671

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

672

}

673

674

void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index,

675

int scale, int disp) {

676

EmitPrefixAndOpcode(entry);

677

EmitModrmSibDisp(entry->skeleton.modrm_opcode, base, index, scale, disp);

678

DCHECK_EQ(0, entry->skeleton.ax_opcode);

679

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

680

}

681

682

void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry,

683

uint8_t base, int disp, uint8_t reg) {

684

EmitPrefixAndOpcode(entry);

685

if (X86_FPREG(reg)) {

686

reg = reg & X86_FP_REG_MASK;

687

}

688

if (reg >= 4) {

689

DCHECK(strchr(entry->name, '8') == NULL ||

690

entry->opcode == kX86Movzx8RM || entry->opcode == kX86Movsx8RM)

691

<< entry->name << " " << static_cast<int>(reg)

692

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

693

}

694

EmitModrmDisp(reg, base, disp);

695

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

696

DCHECK_EQ(0, entry->skeleton.ax_opcode);

697

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

698

}

699

700

void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry,

701

uint8_t reg, uint8_t base, int disp) {

702

// Opcode will flip operands.

703

EmitMemReg(entry, base, disp, reg);

704

}

705

706

void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index,

707

int scale, int disp) {

708

EmitPrefixAndOpcode(entry);

709

if (X86_FPREG(reg)) {

710

reg = reg & X86_FP_REG_MASK;

711

}

712

EmitModrmSibDisp(reg, base, index, scale, disp);

713

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

714

DCHECK_EQ(0, entry->skeleton.ax_opcode);

715

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

716

}

717

718

void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp,

719

uint8_t reg) {

720

// Opcode will flip operands.

721

EmitRegArray(entry, reg, base, index, scale, disp);

722

}

723

724

void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) {

725

DCHECK_NE(entry->skeleton.prefix1, 0);

726

EmitPrefixAndOpcode(entry);

727

if (X86_FPREG(reg)) {

728

reg = reg & X86_FP_REG_MASK;

729

}

730

if (reg >= 4) {

731

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

732

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

733

}

734

DCHECK_LT(reg, 8);

735

uint8_t modrm = (0 << 6) | (reg << 3) | rBP;

736

code_buffer_.push_back(modrm);

737

code_buffer_.push_back(disp & 0xFF);

738

code_buffer_.push_back((disp >> 8) & 0xFF);

739

code_buffer_.push_back((disp >> 16) & 0xFF);

740

code_buffer_.push_back((disp >> 24) & 0xFF);

741

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

742

DCHECK_EQ(0, entry->skeleton.ax_opcode);

743

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

744

}

745

746

void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) {

747

EmitPrefixAndOpcode(entry);

748

if (X86_FPREG(reg1)) {

749

reg1 = reg1 & X86_FP_REG_MASK;

750

}

751

if (X86_FPREG(reg2)) {

752

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

757

code_buffer_.push_back(modrm);

758

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

759

DCHECK_EQ(0, entry->skeleton.ax_opcode);

760

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

761

}

762

763

void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry,

764

uint8_t reg1, uint8_t reg2, int32_t imm) {

765

EmitPrefixAndOpcode(entry);

766

if (X86_FPREG(reg1)) {

767

reg1 = reg1 & X86_FP_REG_MASK;

768

}

769

if (X86_FPREG(reg2)) {

770

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

775

code_buffer_.push_back(modrm);

776

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

777

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

781

void X86Mir2Lir::EmitRegRegImmRev(const X86EncodingMap* entry,

782

uint8_t reg1, uint8_t reg2, int32_t imm) {

783

EmitRegRegImm(entry, reg2, reg1, imm);

784

}

785

786

void X86Mir2Lir::EmitRegMemImm(const X86EncodingMap* entry,

787

uint8_t reg, uint8_t base, int disp, int32_t imm) {

788

EmitPrefixAndOpcode(entry);

789

DCHECK(!X86_FPREG(reg));

790

DCHECK_LT(reg, 8);

791

EmitModrmDisp(reg, base, disp);

792

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

793

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

797

void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

798

if (entry->skeleton.prefix1 != 0) {

799

code_buffer_.push_back(entry->skeleton.prefix1);

800

if (entry->skeleton.prefix2 != 0) {

801

code_buffer_.push_back(entry->skeleton.prefix2);

802

}

803

} else {

804

DCHECK_EQ(0, entry->skeleton.prefix2);

805

}

806

if (reg == rAX && entry->skeleton.ax_opcode != 0) {

807

code_buffer_.push_back(entry->skeleton.ax_opcode);

808

} else {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

809

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

810

if (X86_FPREG(reg)) {

811

reg = reg & X86_FP_REG_MASK;

812

}

813

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

814

code_buffer_.push_back(modrm);

815

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

816

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

817

}

818

Mark Mendell

343adb5

2013-12-18 06:02:17 -0800

[diff] [blame]

819

void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm) {

820

EmitPrefixAndOpcode(entry);

821

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

822

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

826

void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

827

EmitPrefixAndOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

828

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

829

code_buffer_.push_back(modrm);

830

code_buffer_.push_back(disp & 0xFF);

831

code_buffer_.push_back((disp >> 8) & 0xFF);

832

code_buffer_.push_back((disp >> 16) & 0xFF);

833

code_buffer_.push_back((disp >> 24) & 0xFF);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

834

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

835

DCHECK_EQ(entry->skeleton.ax_opcode, 0);

836

}

837

838

void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

839

DCHECK_LT(reg, 8);

840

code_buffer_.push_back(0xB8 + reg);

841

code_buffer_.push_back(imm & 0xFF);

842

code_buffer_.push_back((imm >> 8) & 0xFF);

843

code_buffer_.push_back((imm >> 16) & 0xFF);

844

code_buffer_.push_back((imm >> 24) & 0xFF);

845

}

846

847

void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

848

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

849

if (imm != 1) {

850

code_buffer_.push_back(entry->skeleton.opcode);

851

} else {

852

// Shorter encoding for 1 bit shift

853

code_buffer_.push_back(entry->skeleton.ax_opcode);

854

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

855

DCHECK_NE(0x0F, entry->skeleton.opcode);

856

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

857

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

858

if (reg >= 4) {

859

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

860

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

861

}

862

DCHECK_LT(reg, 8);

863

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

864

code_buffer_.push_back(modrm);

865

if (imm != 1) {

866

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

867

DCHECK(IS_SIMM8(imm));

868

code_buffer_.push_back(imm & 0xFF);

}

}

void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl) {

873

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

874

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

875

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

876

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

877

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

878

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

879

DCHECK_LT(reg, 8);

880

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

881

code_buffer_.push_back(modrm);

882

DCHECK_EQ(0, entry->skeleton.ax_opcode);

883

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

884

}

885

Mark Mendell

feb2b4e

2014-01-28 12:59:49 -0800

[diff] [blame]

886

void X86Mir2Lir::EmitShiftMemCl(const X86EncodingMap* entry, uint8_t base,

887

int displacement, uint8_t cl) {

888

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

889

EmitPrefix(entry);

890

code_buffer_.push_back(entry->skeleton.opcode);

891

DCHECK_NE(0x0F, entry->skeleton.opcode);

892

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

893

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

894

DCHECK_LT(base, 8);

895

EmitModrmDisp(entry->skeleton.modrm_opcode, base, displacement);

896

DCHECK_EQ(0, entry->skeleton.ax_opcode);

897

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

898

}

899

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

900

void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) {

901

if (entry->skeleton.prefix1 != 0) {

902

code_buffer_.push_back(entry->skeleton.prefix1);

903

if (entry->skeleton.prefix2 != 0) {

904

code_buffer_.push_back(entry->skeleton.prefix2);

905

}

906

} else {

907

DCHECK_EQ(0, entry->skeleton.prefix2);

908

}

909

DCHECK_EQ(0, entry->skeleton.ax_opcode);

910

DCHECK_EQ(0x0F, entry->skeleton.opcode);

911

code_buffer_.push_back(0x0F);

912

DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);

913

code_buffer_.push_back(0x90 | condition);

914

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

915

DCHECK_LT(reg, 8);

916

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

917

code_buffer_.push_back(modrm);

918

DCHECK_EQ(entry->skeleton.immediate_bytes, 0);

919

}

920

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

921

void X86Mir2Lir::EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, uint8_t condition) {

922

// Generate prefix and opcode without the condition

923

EmitPrefixAndOpcode(entry);

924

925

// Now add the condition. The last byte of opcode is the one that receives it.

926

DCHECK_LE(condition, 0xF);

927

code_buffer_.back() += condition;

928

929

// Not expecting to have to encode immediate or do anything special for ModR/M since there are two registers.

930

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

931

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

932

933

// Check that registers requested for encoding are sane.

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

// For register to register encoding, the mod is 3.

938

const uint8_t mod = (3 << 6);

939

940

// Encode the ModR/M byte now.

941

const uint8_t modrm = mod | (reg1 << 3) | reg2;

942

code_buffer_.push_back(modrm);

943

}

944

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

945

void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int rel) {

946

if (entry->opcode == kX86Jmp8) {

947

DCHECK(IS_SIMM8(rel));

948

code_buffer_.push_back(0xEB);

949

code_buffer_.push_back(rel & 0xFF);

950

} else if (entry->opcode == kX86Jmp32) {

951

code_buffer_.push_back(0xE9);

952

code_buffer_.push_back(rel & 0xFF);

953

code_buffer_.push_back((rel >> 8) & 0xFF);

954

code_buffer_.push_back((rel >> 16) & 0xFF);

955

code_buffer_.push_back((rel >> 24) & 0xFF);

956

} else {

957

DCHECK(entry->opcode == kX86JmpR);

958

code_buffer_.push_back(entry->skeleton.opcode);

959

uint8_t reg = static_cast<uint8_t>(rel);

960

DCHECK_LT(reg, 8);

961

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

962

code_buffer_.push_back(modrm);

}

}

void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc) {

967

DCHECK_LT(cc, 16);

968

if (entry->opcode == kX86Jcc8) {

969

DCHECK(IS_SIMM8(rel));

970

code_buffer_.push_back(0x70 | cc);

971

code_buffer_.push_back(rel & 0xFF);

972

} else {

973

DCHECK(entry->opcode == kX86Jcc32);

974

code_buffer_.push_back(0x0F);

975

code_buffer_.push_back(0x80 | cc);

976

code_buffer_.push_back(rel & 0xFF);

977

code_buffer_.push_back((rel >> 8) & 0xFF);

978

code_buffer_.push_back((rel >> 16) & 0xFF);

979

code_buffer_.push_back((rel >> 24) & 0xFF);

}

}

void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

984

EmitPrefixAndOpcode(entry);

985

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

986

DCHECK_EQ(0, entry->skeleton.ax_opcode);

987

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

988

}

989

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame^]

990

void X86Mir2Lir::EmitCallImmediate(const X86EncodingMap* entry, int disp) {

991

EmitPrefixAndOpcode(entry);

992

DCHECK_EQ(4, entry->skeleton.immediate_bytes);

993

code_buffer_.push_back(disp & 0xFF);

994

code_buffer_.push_back((disp >> 8) & 0xFF);

995

code_buffer_.push_back((disp >> 16) & 0xFF);

996

code_buffer_.push_back((disp >> 24) & 0xFF);

997

DCHECK_EQ(0, entry->skeleton.ax_opcode);

998

}

999

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1000

void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int disp) {

1001

DCHECK_NE(entry->skeleton.prefix1, 0);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1002

EmitPrefixAndOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1003

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

1004

code_buffer_.push_back(modrm);

1005

code_buffer_.push_back(disp & 0xFF);

1006

code_buffer_.push_back((disp >> 8) & 0xFF);

1007

code_buffer_.push_back((disp >> 16) & 0xFF);

1008

code_buffer_.push_back((disp >> 24) & 0xFF);

1009

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1010

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1011

}

1012

1013

void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, uint8_t reg,

1014

int base_or_table, uint8_t index, int scale, int table_or_disp) {

1015

int disp;

1016

if (entry->opcode == kX86PcRelLoadRA) {

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1017

Mir2Lir::EmbeddedData *tab_rec =

1018

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1019

disp = tab_rec->offset;

1020

} else {

1021

DCHECK(entry->opcode == kX86PcRelAdr);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1022

Mir2Lir::EmbeddedData *tab_rec =

1023

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(base_or_table));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1024

disp = tab_rec->offset;

1025

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1026

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1027

if (X86_FPREG(reg)) {

1028

reg = reg & X86_FP_REG_MASK;

1029

}

1030

DCHECK_LT(reg, 8);

1031

if (entry->opcode == kX86PcRelLoadRA) {

1032

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1033

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1034

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1035

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1036

uint8_t modrm = (2 << 6) | (reg << 3) | rX86_SP;

1037

code_buffer_.push_back(modrm);

1038

DCHECK_LT(scale, 4);

1039

DCHECK_LT(index, 8);

1040

DCHECK_LT(base_or_table, 8);

1041

uint8_t base = static_cast<uint8_t>(base_or_table);

1042

uint8_t sib = (scale << 6) | (index << 3) | base;

1043

code_buffer_.push_back(sib);

1044

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1045

} else {

1046

code_buffer_.push_back(entry->skeleton.opcode + reg);

1047

}

1048

code_buffer_.push_back(disp & 0xFF);

1049

code_buffer_.push_back((disp >> 8) & 0xFF);

1050

code_buffer_.push_back((disp >> 16) & 0xFF);

1051

code_buffer_.push_back((disp >> 24) & 0xFF);

1052

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1053

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1054

}

1055

1056

void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset) {

1057

DCHECK(entry->opcode == kX86StartOfMethod) << entry->name;

1058

code_buffer_.push_back(0xE8); // call +0

1059

code_buffer_.push_back(0);

1060

code_buffer_.push_back(0);

1061

code_buffer_.push_back(0);

1062

code_buffer_.push_back(0);

1063

1064

DCHECK_LT(reg, 8);

1065

code_buffer_.push_back(0x58 + reg); // pop reg

1066

1067

EmitRegImm(&X86Mir2Lir::EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */);

1068

}

1069

1070

void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) {

1071

UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " "

1072

<< BuildInsnString(entry->fmt, lir, 0);

1073

for (int i = 0; i < GetInsnSize(lir); ++i) {

1074

code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3

}

}

/*

* Assemble the LIR into binary instruction format. Note that we may

1080

* discover that pc-relative displacements may not fit the selected

1081

* instruction. In those cases we will try to substitute a new code

1082

* sequence or request that the trace be shortened and retried.

1083

*/

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1084

AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1085

LIR *lir;

1086

AssemblerStatus res = kSuccess; // Assume success

1087

1088

const bool kVerbosePcFixup = false;

1089

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1090

if (IsPseudoLirOp(lir->opcode)) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

continue;

}

if (lir->flags.is_nop) {

continue;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1098

if (lir->flags.fixup != kFixupNone) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1099

switch (lir->opcode) {

1100

case kX86Jcc8: {

1101

LIR *target_lir = lir->target;

1102

DCHECK(target_lir != NULL);

1103

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1104

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1105

if (IS_SIMM8(lir->operands[0])) {

1106

pc = lir->offset + 2 /* opcode + rel8 */;

1107

} else {

1108

pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1109

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1110

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1111

delta = target - pc;

1112

if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1113

if (kVerbosePcFixup) {

1114

LOG(INFO) << "Retry for JCC growth at " << lir->offset

1115

<< " delta: " << delta << " old delta: " << lir->operands[0];

1116

}

1117

lir->opcode = kX86Jcc32;

1118

SetupResourceMasks(lir);

1119

res = kRetryAll;

1120

}

1121

if (kVerbosePcFixup) {

1122

LOG(INFO) << "Source:";

1123

DumpLIRInsn(lir, 0);

1124

LOG(INFO) << "Target:";

1125

DumpLIRInsn(target_lir, 0);

1126

LOG(INFO) << "Delta " << delta;

1127

}

1128

lir->operands[0] = delta;

break;

}

case kX86Jcc32: {

LIR *target_lir = lir->target;

1133

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1134

CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1135

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1136

int delta = target - pc;

1137

if (kVerbosePcFixup) {

1138

LOG(INFO) << "Source:";

1139

DumpLIRInsn(lir, 0);

1140

LOG(INFO) << "Target:";

1141

DumpLIRInsn(target_lir, 0);

1142

LOG(INFO) << "Delta " << delta;

1143

}

1144

lir->operands[0] = delta;

break;

}

case kX86Jmp8: {

LIR *target_lir = lir->target;

1149

DCHECK(target_lir != NULL);

1150

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1151

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1152

if (IS_SIMM8(lir->operands[0])) {

1153

pc = lir->offset + 2 /* opcode + rel8 */;

1154

} else {

1155

pc = lir->offset + 5 /* opcode + rel32 */;

1156

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1157

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1158

delta = target - pc;

1159

if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) {

1160

// Useless branch

buzbee

252254b

2013-09-08 16:20:53 -0700

[diff] [blame]

1161

NopLIR(lir);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1162

if (kVerbosePcFixup) {

1163

LOG(INFO) << "Retry for useless branch at " << lir->offset;

1164

}

1165

res = kRetryAll;

1166

} else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1167

if (kVerbosePcFixup) {

1168

LOG(INFO) << "Retry for JMP growth at " << lir->offset;

1169

}

1170

lir->opcode = kX86Jmp32;

1171

SetupResourceMasks(lir);

1172

res = kRetryAll;

1173

}

1174

lir->operands[0] = delta;

break;

}

case kX86Jmp32: {

LIR *target_lir = lir->target;

1179

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1180

CodeOffset pc = lir->offset + 5 /* opcode + rel32 */;

1181

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1182

int delta = target - pc;

1183

lir->operands[0] = delta;

1184

break;

1185

}

1186

default:

Mark Mendell

67c39c4

2014-01-31 17:28:00 -0800

[diff] [blame]

1187

if (lir->flags.fixup == kFixupLoad) {

1188

LIR *target_lir = lir->target;

1189

DCHECK(target_lir != NULL);

1190

CodeOffset target = target_lir->offset;

1191

lir->operands[2] = target;

1192

int newSize = GetInsnSize(lir);

1193

if (newSize != lir->flags.size) {

1194

lir->flags.size = newSize;

1195

res = kRetryAll;

1196

}

1197

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

break;

}

}

/*

* If one of the pc-relative instructions expanded we'll have

1204

* to make another pass. Don't bother to fully assemble the

1205

* instruction.

1206

*/

1207

if (res != kSuccess) {

1208

continue;

1209

}

1210

CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size());

1211

const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode];

1212

size_t starting_cbuf_size = code_buffer_.size();

1213

switch (entry->kind) {

1214

case kData: // 4 bytes of data

1215

code_buffer_.push_back(lir->operands[0]);

1216

break;

1217

case kNullary: // 1 byte of opcode

1218

DCHECK_EQ(0, entry->skeleton.prefix1);

1219

DCHECK_EQ(0, entry->skeleton.prefix2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1220

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1221

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1222

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1223

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1224

break;

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

1225

case kRegOpcode: // lir operands - 0: reg

1226

EmitOpRegOpcode(entry, lir->operands[0]);

1227

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1228

case kReg: // lir operands - 0: reg

1229

EmitOpReg(entry, lir->operands[0]);

1230

break;

1231

case kMem: // lir operands - 0: base, 1: disp

1232

EmitOpMem(entry, lir->operands[0], lir->operands[1]);

1233

break;

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1234

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

1235

EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]);

1236

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1237

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

1238

EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1239

break;

Mark Mendell

343adb5

2013-12-18 06:02:17 -0800

[diff] [blame]

1240

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

1241

EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1242

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1243

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

1244

EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1245

lir->operands[3], lir->operands[4]);

1246

break;

1247

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

1248

EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1249

break;

1250

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

1251

EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1252

lir->operands[3], lir->operands[4]);

1253

break;

1254

case kRegThread: // lir operands - 0: reg, 1: disp

1255

EmitRegThread(entry, lir->operands[0], lir->operands[1]);

1256

break;

1257

case kRegReg: // lir operands - 0: reg1, 1: reg2

1258

EmitRegReg(entry, lir->operands[0], lir->operands[1]);

1259

break;

1260

case kRegRegStore: // lir operands - 0: reg2, 1: reg1

1261

EmitRegReg(entry, lir->operands[1], lir->operands[0]);

1262

break;

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

1263

case kRegRegImmRev:

1264

EmitRegRegImmRev(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1265

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1266

case kRegRegImm:

1267

EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1268

break;

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

1269

case kRegMemImm:

1270

EmitRegMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1271

lir->operands[3]);

1272

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1273

case kRegImm: // lir operands - 0: reg, 1: immediate

1274

EmitRegImm(entry, lir->operands[0], lir->operands[1]);

1275

break;

1276

case kThreadImm: // lir operands - 0: disp, 1: immediate

1277

EmitThreadImm(entry, lir->operands[0], lir->operands[1]);

1278

break;

1279

case kMovRegImm: // lir operands - 0: reg, 1: immediate

1280

EmitMovRegImm(entry, lir->operands[0], lir->operands[1]);

1281

break;

1282

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

1283

EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]);

1284

break;

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

1285

case kShiftRegCl: // lir operands - 0: reg, 1: cl

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1286

EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]);

1287

break;

Mark Mendell

feb2b4e

2014-01-28 12:59:49 -0800

[diff] [blame]

1288

case kShiftMemCl: // lir operands - 0: base, 1:displacement, 2: cl

1289

EmitShiftMemCl(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1290

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1291

case kRegCond: // lir operands - 0: reg, 1: condition

1292

EmitRegCond(entry, lir->operands[0], lir->operands[1]);

1293

break;

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

1294

case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: condition

1295

EmitRegRegCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1296

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1297

case kJmp: // lir operands - 0: rel

1298

EmitJmp(entry, lir->operands[0]);

1299

break;

1300

case kJcc: // lir operands - 0: rel, 1: CC, target assigned

1301

EmitJcc(entry, lir->operands[0], lir->operands[1]);

1302

break;

1303

case kCall:

1304

switch (entry->opcode) {

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame^]

1305

case kX86CallI: // lir operands - 0: disp

1306

EmitCallImmediate(entry, lir->operands[0]);

1307

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1308

case kX86CallM: // lir operands - 0: base, 1: disp

1309

EmitCallMem(entry, lir->operands[0], lir->operands[1]);

1310

break;

1311

case kX86CallT: // lir operands - 0: disp

1312

EmitCallThread(entry, lir->operands[0]);

1313

break;

1314

default:

1315

EmitUnimplemented(entry, lir);

break;

}

break;

case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

1320

EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1321

lir->operands[3], lir->operands[4]);

1322

break;

1323

case kMacro:

1324

EmitMacro(entry, lir->operands[0], lir->offset);

1325

break;

1326

default:

1327

EmitUnimplemented(entry, lir);

1328

break;

1329

}

1330

CHECK_EQ(static_cast<size_t>(GetInsnSize(lir)),

1331

code_buffer_.size() - starting_cbuf_size)

1332

<< "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name;

}

return res;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1337

// LIR offset assignment.

1338

// TODO: consolidate w/ Arm assembly mechanism.

1339

int X86Mir2Lir::AssignInsnOffsets() {

LIR* lir;

int offset = 0;

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

1344

lir->offset = offset;

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1345

if (LIKELY(!IsPseudoLirOp(lir->opcode))) {

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1346

if (!lir->flags.is_nop) {

1347

offset += lir->flags.size;

1348

}

1349

} else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) {

1350

if (offset & 0x2) {

1351

offset += 2;

1352

lir->operands[0] = 1;

1353

} else {

1354

lir->operands[0] = 0;

1355

}

1356

}

1357

/* Pseudo opcodes don't consume space */

}

return offset;

}

/*

* Walk the compilation unit and assign offsets to instructions

1364

* and literals and compute the total size of the compiled unit.

1365

* TODO: consolidate w/ Arm assembly mechanism.

1366

*/

1367

void X86Mir2Lir::AssignOffsets() {

1368

int offset = AssignInsnOffsets();

1369

1370

/* Const values have to be word aligned */

1371

offset = (offset + 3) & ~3;

1372

1373

/* Set up offsets for literals */

1374

data_offset_ = offset;

1375

1376

offset = AssignLiteralOffset(offset);

1377

1378

offset = AssignSwitchTablesOffset(offset);

1379

1380

offset = AssignFillArrayDataOffset(offset);

1381

1382

total_size_ = offset;

}

/*

* Go over each instruction in the list and calculate the offset from the top

1387

* before sending them off to the assembler. If out-of-range branch distance is

1388

* seen rearrange the instructions a bit to correct it.

1389

* TODO: consolidate w/ Arm assembly mechanism.

1390

*/

1391

void X86Mir2Lir::AssembleLIR() {

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1392

cu_->NewTimingSplit("Assemble");

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame^]

1393

1394

// We will remove the method address if we never ended up using it

1395

if (store_method_addr_ && !store_method_addr_used_) {

1396

setup_method_address_[0]->flags.is_nop = true;

1397

setup_method_address_[1]->flags.is_nop = true;

1398

}

1399

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1400

AssignOffsets();

1401

int assembler_retries = 0;

1402

/*

1403

* Assemble here. Note that we generate code with optimistic assumptions

1404

* and if found now to work, we'll have to redo the sequence and retry.

*/

while (true) {

AssemblerStatus res = AssembleInstructions(0);

1409

if (res == kSuccess) {

break;

} else {

assembler_retries++;

if (assembler_retries > MAX_ASSEMBLER_RETRIES) {

1414

CodegenDump();

1415

LOG(FATAL) << "Assembler error - too many retries";

1416

}

1417

// Redo offsets and try again

1418

AssignOffsets();

1419

code_buffer_.clear();

}

}

// Install literals

InstallLiteralPools();

1425

1426

// Install switch tables

1427

InstallSwitchTables();

1428

1429

// Install fill array data

1430

InstallFillArrayData();

1431

1432

// Create the mapping table and native offset to reference map.

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1433

cu_->NewTimingSplit("PcMappingTable");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1434

CreateMappingTables();

1435

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1436

cu_->NewTimingSplit("GcMap");

buzbee