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Saurabh Shah66c941b2016-07-06 17:34:05 -07001/*
Mahesh Aia25b22712019-01-04 11:49:46 -08002* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
Saurabh Shah66c941b2016-07-06 17:34:05 -07003*
4* Redistribution and use in source and binary forms, with or without
5* modification, are permitted provided that the following conditions are
6* met:
7* * Redistributions of source code must retain the above copyright
8* notice, this list of conditions and the following disclaimer.
9* * Redistributions in binary form must reproduce the above
10* copyright notice, this list of conditions and the following
11* disclaimer in the documentation and/or other materials provided
12* with the distribution.
13* * Neither the name of The Linux Foundation nor the names of its
14* contributors may be used to endorse or promote products derived
15* from this software without specific prior written permission.
16*
17* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
18* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
20* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
21* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
24* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
25* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
26* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
27* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28*/
29
30#ifndef __DRM_INTERFACE_H__
31#define __DRM_INTERFACE_H__
32
33#include <map>
34#include <string>
35#include <utility>
36#include <vector>
Camus Wongb116aa42018-12-18 19:50:54 -050037#include <bitset>
Saurabh Shah66c941b2016-07-06 17:34:05 -070038
39#include "xf86drm.h"
40#include "xf86drmMode.h"
Sushil Chauhan80e58432017-07-06 11:39:17 -070041#include <drm/msm_drm.h>
Yuchao Ma577f0f72018-07-09 11:20:00 +080042#include <drm/msm_drm_pp.h>
Saurabh Shah66c941b2016-07-06 17:34:05 -070043
44namespace sde_drm {
Ramkumar Radhakrishnan9ed1fd82017-03-09 18:46:41 -080045
46typedef std::map<std::pair<uint32_t, uint64_t>, float> CompRatioMap;
47
Saurabh Shah66c941b2016-07-06 17:34:05 -070048/*
49 * Drm Atomic Operation Codes
50 */
51enum struct DRMOps {
52 /*
53 * Op: Sets plane source crop
54 * Arg: uint32_t - Plane ID
55 * DRMRect - Source Rectangle
56 */
57 PLANE_SET_SRC_RECT,
58 /*
59 * Op: Sets plane destination rect
60 * Arg: uint32_t - Plane ID
61 * DRMRect - Dst Rectangle
62 */
63 PLANE_SET_DST_RECT,
64 /*
Namit Solanki6d0d8062017-11-30 17:29:48 +053065 * Op: Sets plane exclusion rect
66 * Arg: uint32_t - Plane ID
67 * drm_clip_rect - Exclusion Rectangle
68 */
69 PLANE_SET_EXCL_RECT,
70 /*
Saurabh Shah66c941b2016-07-06 17:34:05 -070071 * Op: Sets plane zorder
72 * Arg: uint32_t - Plane ID
73 * uint32_t - zorder
74 */
75 PLANE_SET_ZORDER,
76 /*
77 * Op: Sets plane rotation flags
78 * Arg: uint32_t - Plane ID
79 * uint32_t - bit mask of rotation flags (See drm_mode.h for enums)
80 */
81 PLANE_SET_ROTATION,
82 /*
83 * Op: Sets plane alpha
84 * Arg: uint32_t - Plane ID
85 * uint32_t - alpha value
86 */
87 PLANE_SET_ALPHA,
88 /*
89 * Op: Sets the blend type
90 * Arg: uint32_t - Plane ID
91 * uint32_t - blend type (see DRMBlendType)
92 */
93 PLANE_SET_BLEND_TYPE,
94 /*
95 * Op: Sets horizontal decimation
96 * Arg: uint32_t - Plane ID
97 * uint32_t - decimation factor
98 */
99 PLANE_SET_H_DECIMATION,
100 /*
101 * Op: Sets vertical decimation
102 * Arg: uint32_t - Plane ID
103 * uint32_t - decimation factor
104 */
105 PLANE_SET_V_DECIMATION,
106 /*
Prabhanjan Kandula585aa652017-01-26 18:39:11 -0800107 * Op: Sets source config flags
108 * Arg: uint32_t - Plane ID
109 * uint32_t - flags to enable or disable a specific op. E.g. deinterlacing
110 */
111 PLANE_SET_SRC_CONFIG,
112 /*
Saurabh Shah66c941b2016-07-06 17:34:05 -0700113 * Op: Sets frame buffer ID for plane. Set together with CRTC.
114 * Arg: uint32_t - Plane ID
115 * uint32_t - Framebuffer ID
116 */
117 PLANE_SET_FB_ID,
118 /*
119 * Op: Sets the crtc for this plane. Set together with FB_ID.
120 * Arg: uint32_t - Plane ID
121 * uint32_t - CRTC ID
122 */
123 PLANE_SET_CRTC,
124 /*
125 * Op: Sets acquire fence for this plane's buffer. Set together with FB_ID, CRTC.
126 * Arg: uint32_t - Plane ID
127 * uint32_t - Input fence
128 */
129 PLANE_SET_INPUT_FENCE,
130 /*
Saurabh Shah0ffee302016-11-22 10:42:11 -0800131 * Op: Sets scaler config on this plane.
132 * Arg: uint32_t - Plane ID
133 * uint64_t - Address of the scaler config object (version based)
134 */
135 PLANE_SET_SCALER_CONFIG,
136 /*
Rohit Kulkarni8622e362017-01-30 18:14:10 -0800137 * Op: Sets plane rotation destination rect
138 * Arg: uint32_t - Plane ID
139 * DRMRect - rotator dst Rectangle
140 */
141 PLANE_SET_ROTATION_DST_RECT,
142 /*
Sushil Chauhan1021cc02017-05-03 15:11:43 -0700143 * Op: Sets FB Secure mode for this plane.
144 * Arg: uint32_t - Plane ID
145 * uint32_t - Value of the FB Secure mode.
146 */
147 PLANE_SET_FB_SECURE_MODE,
148 /*
Ping Li8d6dd622017-07-03 12:05:15 -0700149 * Op: Sets csc config on this plane.
150 * Arg: uint32_t - Plane ID
151 * uint32_t* - pointer to csc type
152 */
153 PLANE_SET_CSC_CONFIG,
154 /*
Ramkumar Radhakrishnan07254302017-11-13 16:18:22 -0800155 * Op: Sets multirect mode on this plane.
156 * Arg: uint32_t - Plane ID
157 * uint32_t - multirect mode
158 */
159 PLANE_SET_MULTIRECT_MODE,
160 /*
Rohit Kulkarni2d7151c2017-12-14 22:17:49 -0800161 * Op: Sets rotator output frame buffer ID for plane.
162 * Arg: uint32_t - Plane ID
163 * uint32_t - Framebuffer ID
164 */
165 PLANE_SET_ROT_FB_ID,
166 /*
Arun Kumar K.R5d30ab52017-12-28 09:05:36 +0530167 * Op: Sets inverse pma mode on this plane.
168 * Arg: uint32_t - Plane ID
169 * uint32_t - enable/disable inverse pma.
170 */
171 PLANE_SET_INVERSE_PMA,
172 /*
173 * Op: Sets csc config on this plane.
174 * Arg: uint32_t - Plane ID
175 * uint64_t - Address of the csc config object(version based)
176 */
177 PLANE_SET_DGM_CSC_CONFIG,
178 /*
179 * Op: Sets SSPP Feature
180 * Arg: uint32_t - Plane ID
181 * DRMPPFeatureInfo * - PP feature data pointer
182 */
183 PLANE_SET_POST_PROC,
184 /*
Saurabh Shah66c941b2016-07-06 17:34:05 -0700185 * Op: Activate or deactivate a CRTC
186 * Arg: uint32_t - CRTC ID
187 * uint32_t - 1 to enable, 0 to disable
188 */
189 CRTC_SET_ACTIVE,
190 /*
191 * Op: Sets display mode
192 * Arg: uint32_t - CRTC ID
193 * drmModeModeInfo* - Pointer to display mode
194 */
195 CRTC_SET_MODE,
196 /*
197 * Op: Sets an offset indicating when a release fence should be signalled.
198 * Arg: uint32_t - offset
199 * 0: non-speculative, default
200 * 1: speculative
201 */
202 CRTC_SET_OUTPUT_FENCE_OFFSET,
203 /*
Ramkumar Radhakrishnan9ed1fd82017-03-09 18:46:41 -0800204 * Op: Sets overall SDE core clock
205 * Arg: uint32_t - CRTC ID
206 * uint32_t - core_clk
207 */
208 CRTC_SET_CORE_CLK,
Ramkumar Radhakrishnan3c4de112017-05-24 22:38:30 -0700209 /*
210 * Op: Sets MNOC bus average bandwidth
Ramkumar Radhakrishnan9ed1fd82017-03-09 18:46:41 -0800211 * Arg: uint32_t - CRTC ID
212 * uint32_t - core_ab
213 */
214 CRTC_SET_CORE_AB,
215 /*
Ramkumar Radhakrishnan3c4de112017-05-24 22:38:30 -0700216 * Op: Sets MNOC bus instantaneous bandwidth
Ramkumar Radhakrishnan9ed1fd82017-03-09 18:46:41 -0800217 * Arg: uint32_t - CRTC ID
218 * uint32_t - core_ib
219 */
220 CRTC_SET_CORE_IB,
221 /*
Ramkumar Radhakrishnan3c4de112017-05-24 22:38:30 -0700222 * Op: Sets LLCC Bus average bandwidth
223 * Arg: uint32_t - CRTC ID
224 * uint32_t - llcc_ab
225 */
226 CRTC_SET_LLCC_AB,
227 /*
228 * Op: Sets LLCC Bus instantaneous bandwidth
229 * Arg: uint32_t - CRTC ID
230 * uint32_t - llcc_ib
231 */
232 CRTC_SET_LLCC_IB,
233 /*
234 * Op: Sets DRAM bus average bandwidth
235 * Arg: uint32_t - CRTC ID
236 * uint32_t - dram_ab
237 */
238 CRTC_SET_DRAM_AB,
239 /*
240 * Op: Sets DRAM bus instantaneous bandwidth
241 * Arg: uint32_t - CRTC ID
242 * uint32_t - dram_ib
243 */
244 CRTC_SET_DRAM_IB,
245 /*
Ramkumar Radhakrishnanb7910442017-12-11 13:32:47 -0800246 * Op: Sets Rotator BW for inline rotation
247 * Arg: uint32_t - CRTC ID
248 * uint32_t - rot_bw
249 */
250 CRTC_SET_ROT_PREFILL_BW,
251 /*
Ramkumar Radhakrishnan3c4de112017-05-24 22:38:30 -0700252 * Op: Sets rotator clock for inline rotation
253 * Arg: uint32_t - CRTC ID
254 * uint32_t - rot_clk
255 */
Namit Solanki24921ab2017-05-23 20:16:25 +0530256 CRTC_SET_ROT_CLK,
257 /*
258 * Op: Sets destination scalar data
259 * Arg: uint32_t - CRTC ID
260 * uint64_t - Pointer to destination scalar data
261 */
262 CRTC_SET_DEST_SCALER_CONFIG,
263 /*
Saurabh Shah66c941b2016-07-06 17:34:05 -0700264 * Op: Returns release fence for this frame. Should be called after Commit() on
265 * DRMAtomicReqInterface.
266 * Arg: uint32_t - CRTC ID
267 * int * - Pointer to an integer that will hold the returned fence
268 */
269 CRTC_GET_RELEASE_FENCE,
270 /*
Ping Li281f48d2017-01-16 12:45:40 -0800271 * Op: Sets PP feature
272 * Arg: uint32_t - CRTC ID
273 * DRMPPFeatureInfo * - PP feature data pointer
274 */
275 CRTC_SET_POST_PROC,
276 /*
Saurabh Shahe9f55d72017-03-03 15:14:13 -0800277 * Op: Sets CRTC ROIs.
278 * Arg: uint32_t - CRTC ID
279 * uint32_t - number of ROIs
280 * DRMRect * - Array of CRTC ROIs
281 */
282 CRTC_SET_ROI,
283 /*
Sushil Chauhan1021cc02017-05-03 15:11:43 -0700284 * Op: Sets Security level for CRTC.
285 * Arg: uint32_t - CRTC ID
286 * uint32_t - Security level
287 */
288 CRTC_SET_SECURITY_LEVEL,
289 /*
Prabhanjan Kanduladbc8aed2017-03-24 14:43:16 -0700290 * Op: sets solid fill stages
291 * Arg: uint32_t - CRTC ID
292 * Vector of DRMSolidfillStage
293 */
294 CRTC_SET_SOLIDFILL_STAGES,
295 /*
Anjaneya Prasad Musunurie8c67f22017-07-01 16:16:13 +0530296 * Op: Sets idle timeout.
297 * Arg: uint32_t - CRTC ID
298 * uint32_t - idle timeout in ms
299 */
300 CRTC_SET_IDLE_TIMEOUT,
301 /*
Sushil Chauhan741ac312018-04-02 12:22:16 -0700302 * Op: Sets Capture mode for Concurrent Writeback feature.
303 * Arg: uint32_t - CRTC ID
304 * uint32_t - Capture mode
305 */
306 CRTC_SET_CAPTURE_MODE,
307 /*
Ramkumar Radhakrishnanf985d482018-07-23 18:10:41 -0700308 * Op: Sets Idle PC state for CRTC.
309 * Arg: uint32_t - CRTC ID
310 * uint32_t - idle pc state
311 */
312 CRTC_SET_IDLE_PC_STATE,
313 /*
Saurabh Shah66c941b2016-07-06 17:34:05 -0700314 * Op: Returns retire fence for this commit. Should be called after Commit() on
315 * DRMAtomicReqInterface.
316 * Arg: uint32_t - Connector ID
317 * int * - Pointer to an integer that will hold the returned fence
318 */
319 CONNECTOR_GET_RETIRE_FENCE,
320 /*
321 * Op: Sets writeback connector destination rect
322 * Arg: uint32_t - Connector ID
323 * DRMRect - Dst Rectangle
324 */
325 CONNECTOR_SET_OUTPUT_RECT,
326 /*
327 * Op: Sets frame buffer ID for writeback connector.
328 * Arg: uint32_t - Connector ID
329 * uint32_t - Framebuffer ID
330 */
331 CONNECTOR_SET_OUTPUT_FB_ID,
Sushil Chauhan3396e202017-04-14 18:34:22 -0700332 /*
333 * Op: Sets power mode for connector.
334 * Arg: uint32_t - Connector ID
335 * uint32_t - Power Mode
336 */
337 CONNECTOR_SET_POWER_MODE,
Saurabh Shahe9f55d72017-03-03 15:14:13 -0800338 /*
339 * Op: Sets panel ROIs.
340 * Arg: uint32_t - Connector ID
341 * uint32_t - number of ROIs
342 * DRMRect * - Array of Connector ROIs
343 */
344 CONNECTOR_SET_ROI,
Sushil Chauhane2f89c92017-08-23 11:30:34 -0700345 /*
Saurabh Shahf3635952017-10-16 17:08:18 -0700346 * Op: Sets the connector to autorefresh mode.
347 * Arg: uint32_t - Connector ID
348 * uint32_t - Enable-1, Disable-0
349 */
350 CONNECTOR_SET_AUTOREFRESH,
351 /*
Sushil Chauhane2f89c92017-08-23 11:30:34 -0700352 * Op: Set FB secure mode for Writeback connector.
353 * Arg: uint32_t - Connector ID
354 * uint32_t - FB Secure mode
355 */
356 CONNECTOR_SET_FB_SECURE_MODE,
Saurabh Shah82b06f42017-09-06 16:43:49 -0700357 /*
358 * Op: Sets a crtc id to this connector
359 * Arg: uint32_t - Connector ID
360 * uint32_t - CRTC ID
361 */
362 CONNECTOR_SET_CRTC,
Srikanth Rajagopalan7a09b2e2017-06-19 18:41:03 -0700363 /*
Gopikrishnaiah Anandan739faf92017-07-21 12:32:00 -0700364 * Op: Sets PP feature
365 * Arg: uint32_t - Connector ID
366 * DRMPPFeatureInfo * - PP feature data pointer
367 */
Xu Yang32e58c22017-11-20 09:58:11 +0800368 CONNECTOR_SET_POST_PROC,
Gopikrishnaiah Anandan739faf92017-07-21 12:32:00 -0700369 /*
Srikanth Rajagopalan7a09b2e2017-06-19 18:41:03 -0700370 * Op: Sets connector hdr metadata
371 * Arg: uint32_t - Connector ID
372 * drm_msm_ext_hdr_metadata - hdr_metadata
373 */
374 CONNECTOR_SET_HDR_METADATA,
Xu Yang32e58c22017-11-20 09:58:11 +0800375 /*
376 * Op: Cache Dpps features.
377 * Arg: uint32_t - Object ID
378 uint32_t - Feature ID
379 * uint64_t - Pointer to feature config data
380 */
381 DPPS_CACHE_FEATURE,
Xu Yangda642222018-06-12 10:32:33 +0800382 /*
383 * Op: Commit Dpps features.
384 * Arg: drmModeAtomicReq - Atomic request
385 */
386 DPPS_COMMIT_FEATURE,
Sushil Chauhan8f514a52018-02-27 17:35:44 -0800387 /*
388 * Op: Sets qsync mode on connector
389 * Arg: uint32_t - Connector ID
390 * uint32_t - qsync mode
391 */
392 CONNECTOR_SET_QSYNC_MODE,
Mathew Joseph Karimpanalb7f20c62018-10-09 12:17:20 +0530393 /*
394 * Op: Sets topology control on this connector
395 * Arg: uint32_t - Connector ID
396 * uint32_t - Topology control bit-mask
397 */
398 CONNECTOR_SET_TOPOLOGY_CONTROL,
Saurabh Shah66c941b2016-07-06 17:34:05 -0700399};
400
Saurabh Shahf9266ee2017-04-19 15:25:46 -0700401enum struct DRMRotation {
402 FLIP_H = 0x1,
403 FLIP_V = 0x2,
Prabhanjan Kandula5bc7f8b2017-05-23 12:24:57 -0700404 ROT_180 = FLIP_H | FLIP_V,
Saurabh Shahf9266ee2017-04-19 15:25:46 -0700405 ROT_90 = 0x4,
406};
407
Sushil Chauhan3396e202017-04-14 18:34:22 -0700408enum struct DRMPowerMode {
409 ON,
410 DOZE,
411 DOZE_SUSPEND,
412 OFF,
413};
414
Saurabh Shah66c941b2016-07-06 17:34:05 -0700415enum struct DRMBlendType {
416 UNDEFINED = 0,
417 OPAQUE = 1,
418 PREMULTIPLIED = 2,
419 COVERAGE = 3,
420};
421
Prabhanjan Kandula585aa652017-01-26 18:39:11 -0800422enum struct DRMSrcConfig {
423 DEINTERLACE = 0,
424};
425
Ramkumar Radhakrishnanf985d482018-07-23 18:10:41 -0700426enum struct DRMIdlePCState {
427 NONE,
428 ENABLE,
429 DISABLE,
430};
431
432
Saurabh Shah66c941b2016-07-06 17:34:05 -0700433/* Display type to identify a suitable connector */
434enum struct DRMDisplayType {
435 PERIPHERAL,
436 TV,
437 VIRTUAL,
438};
439
440struct DRMRect {
441 uint32_t left; // Left-most pixel coordinate.
442 uint32_t top; // Top-most pixel coordinate.
443 uint32_t right; // Right-most pixel coordinate.
444 uint32_t bottom; // Bottom-most pixel coordinate.
445};
446
447//------------------------------------------------------------------------
448// DRM Info Query Types
449//------------------------------------------------------------------------
450
451enum struct QSEEDVersion {
452 V1,
453 V2,
454 V3,
Ramakant Singh1ba882f2018-06-06 10:23:21 +0530455 V3LITE,
Saurabh Shah66c941b2016-07-06 17:34:05 -0700456};
457
Rohit Kulkarnibfa855c2017-06-29 17:52:10 -0700458/* QSEED3 Step version */
459enum struct QSEEDStepVersion {
460 V2,
461 V3,
462 V4,
Ramakant Singh1ba882f2018-06-06 10:23:21 +0530463 V3LITE_V4,
464 V3LITE_V5,
Rohit Kulkarnibfa855c2017-06-29 17:52:10 -0700465};
466
Prabhanjan Kandulae6dfab92017-03-14 11:02:49 -0700467enum struct SmartDMARevision {
468 V1,
469 V2,
Mathew Joseph Karimpanal1f8a21c2017-10-20 20:47:42 +0530470 V2p5
Prabhanjan Kandulae6dfab92017-03-14 11:02:49 -0700471};
472
Rohit Kulkarni2d7151c2017-12-14 22:17:49 -0800473/* Inline Rotation version */
474enum struct InlineRotationVersion {
475 UNKNOWN,
476 V1,
477 V1p1, // Rotator FB ID needs to be set
478};
479
Saurabh Shah66c941b2016-07-06 17:34:05 -0700480/* Per CRTC Resource Info*/
481struct DRMCrtcInfo {
482 bool has_src_split;
Srikanth Rajagopalan49380782017-07-06 15:23:12 -0700483 bool has_hdr;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700484 uint32_t max_blend_stages;
Prabhanjan Kanduladbc8aed2017-03-24 14:43:16 -0700485 uint32_t max_solidfill_stages;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700486 QSEEDVersion qseed_version;
Prabhanjan Kandulae6dfab92017-03-14 11:02:49 -0700487 SmartDMARevision smart_dma_rev;
Ramkumar Radhakrishnan9ed1fd82017-03-09 18:46:41 -0800488 float ib_fudge_factor;
489 float clk_fudge_factor;
490 uint32_t dest_scale_prefill_lines;
491 uint32_t undersized_prefill_lines;
492 uint32_t macrotile_prefill_lines;
493 uint32_t nv12_prefill_lines;
494 uint32_t linear_prefill_lines;
495 uint32_t downscale_prefill_lines;
496 uint32_t extra_prefill_lines;
497 uint32_t amortized_threshold;
498 uint64_t max_bandwidth_low;
499 uint64_t max_bandwidth_high;
500 uint32_t max_sde_clk;
501 CompRatioMap comp_ratio_rt_map;
502 CompRatioMap comp_ratio_nrt_map;
Gopikrishnaiah Anandan76815522017-06-27 15:18:04 -0700503 uint32_t hw_version;
Namit Solanki24921ab2017-05-23 20:16:25 +0530504 uint32_t dest_scaler_count = 0;
505 uint32_t max_dest_scaler_input_width = 0;
506 uint32_t max_dest_scaler_output_width = 0;
507 uint32_t max_dest_scale_up = 1;
Pullakavi Srinivas3e2c0402017-12-05 17:50:15 +0530508 uint32_t min_prefill_lines = 0;
Ramkumar Radhakrishnana38b7602018-03-15 14:49:52 -0700509 int secure_disp_blend_stage = -1;
Sushil Chauhanc75358e2018-04-24 14:36:38 -0700510 bool concurrent_writeback = false;
Pullakavi Srinivasdfae05c2019-02-22 14:56:22 +0530511 uint32_t num_mnocports;
512 uint32_t mnoc_bus_width;
Ramakant Singh21f77e92019-07-28 10:39:20 +0530513 bool use_baselayer_for_stage = false;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700514};
515
516enum struct DRMPlaneType {
517 // Has CSC and scaling capability
518 VIG = 0,
519 // Has scaling capability but no CSC
520 RGB,
521 // No scaling support
522 DMA,
523 // Supports a small dimension and doesn't use a CRTC stage
524 CURSOR,
525 MAX,
526};
527
Arun Kumar K.R5d30ab52017-12-28 09:05:36 +0530528enum struct DRMTonemapLutType {
529 DMA_1D_GC,
530 DMA_1D_IGC,
531 VIG_1D_IGC,
532 VIG_3D_GAMUT,
533};
534
Saurabh Shah66c941b2016-07-06 17:34:05 -0700535struct DRMPlaneTypeInfo {
Prabhanjan Kandulae6dfab92017-03-14 11:02:49 -0700536 DRMPlaneType type;
537 uint32_t master_plane_id;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700538 // FourCC format enum and modifier
539 std::vector<std::pair<uint32_t, uint64_t>> formats_supported;
540 uint32_t max_linewidth;
Mathew Joseph Karimpanal1f8a21c2017-10-20 20:47:42 +0530541 uint32_t max_scaler_linewidth;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700542 uint32_t max_upscale;
543 uint32_t max_downscale;
544 uint32_t max_horizontal_deci;
545 uint32_t max_vertical_deci;
Ramkumar Radhakrishnan9ed1fd82017-03-09 18:46:41 -0800546 uint64_t max_pipe_bandwidth;
Rohit Kulkarni8622e362017-01-30 18:14:10 -0800547 uint32_t cache_size; // cache size in bytes for inline rotation support.
Namit Solanki6d0d8062017-11-30 17:29:48 +0530548 bool has_excl_rect = false;
Rohit Kulkarnibfa855c2017-06-29 17:52:10 -0700549 QSEEDStepVersion qseed3_version;
Ramkumar Radhakrishnan07254302017-11-13 16:18:22 -0800550 bool multirect_prop_present = false;
Rohit Kulkarni2d7151c2017-12-14 22:17:49 -0800551 InlineRotationVersion inrot_version; // inline rotation version
Arun Kumar K.R5d30ab52017-12-28 09:05:36 +0530552 bool inverse_pma = false;
553 uint32_t dgm_csc_version = 0; // csc used with DMA
554 std::map<DRMTonemapLutType, uint32_t> tonemap_lut_version_map = {};
Ramkumar Radhakrishnan4a269752018-03-08 14:53:15 -0800555 bool block_sec_ui = false;
Camus Wongb116aa42018-12-18 19:50:54 -0500556 // Allow all planes to be usable on all displays by default
557 std::bitset<32> hw_block_mask = std::bitset<32>().set();
Saurabh Shah66c941b2016-07-06 17:34:05 -0700558};
559
Prabhanjan Kandulae6dfab92017-03-14 11:02:49 -0700560// All DRM Planes as map<Plane_id , plane_type_info> listed from highest to lowest priority
561typedef std::vector<std::pair<uint32_t, DRMPlaneTypeInfo>> DRMPlanesInfo;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700562
563enum struct DRMTopology {
Rohit Kulkarni2faa91c2017-06-05 15:43:48 -0700564 UNKNOWN, // To be compat with driver defs in sde_rm.h
Saurabh Shah66c941b2016-07-06 17:34:05 -0700565 SINGLE_LM,
Rohit Kulkarni2faa91c2017-06-05 15:43:48 -0700566 SINGLE_LM_DSC,
Saurabh Shah66c941b2016-07-06 17:34:05 -0700567 DUAL_LM,
Rohit Kulkarni2faa91c2017-06-05 15:43:48 -0700568 DUAL_LM_DSC,
Saurabh Shah66c941b2016-07-06 17:34:05 -0700569 DUAL_LM_MERGE,
Rohit Kulkarni2faa91c2017-06-05 15:43:48 -0700570 DUAL_LM_MERGE_DSC,
571 DUAL_LM_DSCMERGE,
572 PPSPLIT,
Saurabh Shah66c941b2016-07-06 17:34:05 -0700573};
574
575enum struct DRMPanelMode {
576 VIDEO,
577 COMMAND,
578};
579
Saurabh Shah7e16c932017-11-03 17:55:36 -0700580/* Per mode info */
581struct DRMModeInfo {
582 drmModeModeInfo mode;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700583 DRMTopology topology;
Saurabh Shahe9f55d72017-03-03 15:14:13 -0800584 // Valid only if mode is command
585 int num_roi;
586 int xstart;
587 int ystart;
588 int walign;
589 int halign;
590 int wmin;
591 int hmin;
592 bool roi_merge;
Pullakavi Srinivas9189e602018-12-19 16:58:07 +0530593 uint64_t bit_clk_rate;
Mahesh Aia25b22712019-01-04 11:49:46 -0800594 uint32_t transfer_time_us;
Saurabh Shah7e16c932017-11-03 17:55:36 -0700595};
596
597/* Per Connector Info*/
598struct DRMConnectorInfo {
599 uint32_t mmWidth;
600 uint32_t mmHeight;
601 uint32_t type;
602 std::vector<DRMModeInfo> modes;
603 std::string panel_name;
604 DRMPanelMode panel_mode;
605 bool is_primary;
606 // Valid only if DRMPanelMode is VIDEO
607 bool dynamic_fps;
608 // FourCC format enum and modifier
609 std::vector<std::pair<uint32_t, uint64_t>> formats_supported;
610 // Valid only if type is DRM_MODE_CONNECTOR_VIRTUAL
611 uint32_t max_linewidth;
Prabhanjan Kandula5bc7f8b2017-05-23 12:24:57 -0700612 DRMRotation panel_orientation;
Sushil Chauhan80e58432017-07-06 11:39:17 -0700613 drm_panel_hdr_properties panel_hdr_prop;
Srikanth Rajagopalance0f7cb2017-06-12 15:14:26 -0700614 drm_msm_ext_hdr_properties ext_hdr_prop;
Sushil Chauhan8f514a52018-02-27 17:35:44 -0800615 bool qsync_support;
Mathew Joseph Karimpanal731bc932017-11-22 10:04:56 +0530616 // Connection status of this connector
617 bool is_connected;
Ramakant Singhdbe738a2018-08-23 23:57:07 +0530618 bool is_wb_ubwc_supported;
Mathew Joseph Karimpanalb7f20c62018-10-09 12:17:20 +0530619 uint32_t topology_control;
Pullakavi Srinivas9189e602018-12-19 16:58:07 +0530620 bool dyn_bitclk_support;
Varun Arora771fcd22019-02-07 18:08:18 -0800621 std::vector<uint8_t> edid;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700622};
623
Mathew Joseph Karimpanal731bc932017-11-22 10:04:56 +0530624// All DRM Connectors as map<Connector_id , connector_info>
625typedef std::map<uint32_t, DRMConnectorInfo> DRMConnectorsInfo;
626
627/* Per Encoder Info */
628struct DRMEncoderInfo {
629 uint32_t type;
630};
631
632// All DRM Encoders as map<Encoder_id , encoder_info>
633typedef std::map<uint32_t, DRMEncoderInfo> DRMEncodersInfo;
634
Saurabh Shah66c941b2016-07-06 17:34:05 -0700635/* Identifier token for a display */
636struct DRMDisplayToken {
637 uint32_t conn_id;
638 uint32_t crtc_id;
Saurabh Shahf8226712018-02-05 15:51:53 -0800639 uint32_t crtc_index;
Mathew Joseph Karimpanal731bc932017-11-22 10:04:56 +0530640 uint32_t encoder_id;
Varun Arora771fcd22019-02-07 18:08:18 -0800641 uint8_t hw_port;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700642};
643
Ping Li281f48d2017-01-16 12:45:40 -0800644enum DRMPPFeatureID {
645 kFeaturePcc,
646 kFeatureIgc,
647 kFeaturePgc,
648 kFeatureMixerGc,
649 kFeaturePaV2,
650 kFeatureDither,
651 kFeatureGamut,
652 kFeaturePADither,
Rajesh Yadavd30b0cc2017-09-22 00:26:54 +0530653 kFeaturePAHsic,
654 kFeaturePASixZone,
Rajesh Yadav99535ac2017-08-28 16:33:04 +0530655 kFeaturePAMemColSkin,
656 kFeaturePAMemColSky,
657 kFeaturePAMemColFoliage,
658 kFeaturePAMemColProt,
Rajesh Yadavc4f67b82017-11-15 20:37:13 +0530659 kFeatureDgmIgc,
660 kFeatureDgmGc,
661 kFeatureVigIgc,
662 kFeatureVigGamut,
Ping Li281f48d2017-01-16 12:45:40 -0800663 kPPFeaturesMax,
664};
665
666enum DRMPPPropType {
667 kPropEnum,
668 kPropRange,
669 kPropBlob,
670 kPropTypeMax,
671};
672
673struct DRMPPFeatureInfo {
674 DRMPPFeatureID id;
675 DRMPPPropType type;
676 uint32_t version;
677 uint32_t payload_size;
678 void *payload;
Gopikrishnaiah Anandan739faf92017-07-21 12:32:00 -0700679 uint32_t object_type;
Ping Li281f48d2017-01-16 12:45:40 -0800680};
681
Xu Yang32e58c22017-11-20 09:58:11 +0800682enum DRMDPPSFeatureID {
683 // Ad4 properties
684 kFeatureAd4Mode,
685 kFeatureAd4Init,
686 kFeatureAd4Cfg,
687 kFeatureAd4Input,
Yuchao Ma577f0f72018-07-09 11:20:00 +0800688 kFeatureAd4Roi,
Xu Yang32e58c22017-11-20 09:58:11 +0800689 kFeatureAd4Backlight,
690 kFeatureAd4Assertiveness,
691 kFeatureAd4ManualStrength,
692 // ABA properties
693 kFeatureAbaHistCtrl,
694 kFeatureAbaHistIRQ,
695 kFeatureAbaLut,
696 // BL scale properties
697 kFeatureAd4BlScale,
698 kFeatureBacklightScale,
699 // Events
700 kFeaturePowerEvent,
701 kFeatureAbaHistEvent,
702 kFeatureBackLightEvent,
703 kFeatureAdAttBlEvent,
704 // Insert features above
705 kDppsFeaturesMax,
706};
707
Ping Li6a74d892018-05-02 15:54:58 -0700708struct DppsFeaturePayload {
709 uint32_t object_type;
710 uint32_t feature_id;
711 uint64_t value;
712};
713
Xu Yang32e58c22017-11-20 09:58:11 +0800714struct DRMDppsFeatureInfo {
715 DRMDPPSFeatureID id;
716 uint32_t version;
717};
718
719enum AD4Modes {
720 kAd4Off,
721 kAd4AutoStrength,
722 kAd4Calibration,
723 kAd4Manual,
724 kAd4ModeMax,
725};
726
727enum HistModes {
728 kHistDisabled,
729 kHistEnabled,
730};
731
732struct DRMDppsEventInfo {
733 uint32_t object_type;
734 uint32_t event_type;
735 int drm_fd;
736 bool enable;
737};
738
Ping Li8d6dd622017-07-03 12:05:15 -0700739enum DRMCscType {
740 kCscYuv2Rgb601L,
741 kCscYuv2Rgb601FR,
742 kCscYuv2Rgb709L,
743 kCscYuv2Rgb2020L,
744 kCscYuv2Rgb2020FR,
745 kCscTypeMax,
746};
747
Saurabh Shah0ffee302016-11-22 10:42:11 -0800748struct DRMScalerLUTInfo {
749 uint32_t dir_lut_size = 0;
750 uint32_t cir_lut_size = 0;
751 uint32_t sep_lut_size = 0;
752 uint64_t dir_lut = 0;
753 uint64_t cir_lut = 0;
754 uint64_t sep_lut = 0;
755};
756
Sushil Chauhan1021cc02017-05-03 15:11:43 -0700757enum struct DRMSecureMode {
758 NON_SECURE,
759 SECURE,
760 NON_SECURE_DIR_TRANSLATION,
761 SECURE_DIR_TRANSLATION,
762};
763
764enum struct DRMSecurityLevel {
765 SECURE_NON_SECURE,
766 SECURE_ONLY,
767};
768
Ramkumar Radhakrishnan07254302017-11-13 16:18:22 -0800769enum struct DRMMultiRectMode {
770 NONE = 0,
771 PARALLEL = 1,
772 SERIAL = 2,
773};
774
Sushil Chauhan741ac312018-04-02 12:22:16 -0700775enum struct DRMCWbCaptureMode {
776 MIXER_OUT = 0,
777 DSPP_OUT = 1,
778};
779
Sushil Chauhan8f514a52018-02-27 17:35:44 -0800780enum struct DRMQsyncMode {
781 NONE = 0,
782 CONTINUOUS,
Pullakavi Srinivas76e3ae02019-08-14 12:18:12 +0530783 ONESHOT,
Sushil Chauhan8f514a52018-02-27 17:35:44 -0800784};
785
Mathew Joseph Karimpanalb7f20c62018-10-09 12:17:20 +0530786enum struct DRMTopologyControl {
787 NONE = 0,
788 RESERVE_LOCK = 1 << 0,
789 RESERVE_CLEAR = 1 << 1,
790 DSPP = 1 << 2,
791 DEST_SCALER = 1 << 3,
792};
793
Prabhanjan Kanduladbc8aed2017-03-24 14:43:16 -0700794struct DRMSolidfillStage {
Xu Yang32e58c22017-11-20 09:58:11 +0800795 DRMRect bounding_rect {};
796 bool is_exclusion_rect = false;
797 uint32_t color = 0xff000000; // in 8bit argb
798 uint32_t red = 0;
799 uint32_t blue = 0;
800 uint32_t green = 0;
801 uint32_t alpha = 0xff;
802 uint32_t color_bit_depth = 0;
803 uint32_t z_order = 0;
804 uint32_t plane_alpha = 0xff;
Prabhanjan Kanduladbc8aed2017-03-24 14:43:16 -0700805};
806
Saurabh Shah66c941b2016-07-06 17:34:05 -0700807/* DRM Atomic Request Property Set.
808 *
809 * Helper class to create and populate atomic properties of DRM components
810 * when rendered in DRM atomic mode */
811class DRMAtomicReqInterface {
812 public:
813 virtual ~DRMAtomicReqInterface() {}
814 /* Perform request operation.
815 *
816 * [input]: opcode: operation code from DRMOps list.
Saurabh Shah1abcdf62017-11-21 14:03:22 -0800817 * obj_id: Relevant crtc, connector, plane id
Saurabh Shah66c941b2016-07-06 17:34:05 -0700818 * var_arg: arguments for DRMOps's can differ in number and
819 * data type. Refer above DRMOps to details.
820 * [return]: Error code if the API fails, 0 on success.
821 */
Saurabh Shah1abcdf62017-11-21 14:03:22 -0800822 virtual int Perform(DRMOps opcode, uint32_t obj_id, ...) = 0;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700823
824 /*
825 * Commit the params set via Perform(). Also resets the properties after commit. Needs to be
826 * called every frame.
827 * [input]: synchronous: Determines if the call should block until a h/w flip
Saurabh Shaha917aa72017-09-15 13:27:24 -0700828 * [input]: retain_planes: Retains already staged planes. Useful when not explicitly programming
829 * planes but still need the previously staged ones to not be unstaged
Saurabh Shah66c941b2016-07-06 17:34:05 -0700830 * [return]: Error code if the API fails, 0 on success.
831 */
Saurabh Shaha917aa72017-09-15 13:27:24 -0700832 virtual int Commit(bool synchronous, bool retain_planes) = 0;
Varun Arorabaa16472018-08-16 16:19:59 -0700833
Saurabh Shah66c941b2016-07-06 17:34:05 -0700834 /*
835 * Validate the params set via Perform().
836 * [return]: Error code if the API fails, 0 on success.
837 */
838 virtual int Validate() = 0;
839};
840
841class DRMManagerInterface;
842
843/* Populates a singleton instance of DRMManager */
844typedef int (*GetDRMManager)(int fd, DRMManagerInterface **intf);
845
846/* Destroy DRMManager instance */
Saurabh Shahab7807c2017-02-08 15:41:08 -0800847typedef int (*DestroyDRMManager)();
Saurabh Shah66c941b2016-07-06 17:34:05 -0700848
849/*
850 * DRM Manager Interface - Any class which plans to implement helper function for vendor
851 * specific DRM driver implementation must implement the below interface routines to work
852 * with SDM.
853 */
854
855class DRMManagerInterface {
856 public:
857 virtual ~DRMManagerInterface() {}
858
859 /*
860 * Since SDM completely manages the planes. GetPlanesInfo will provide all
861 * the plane information.
862 * [output]: DRMPlanesInfo: Resource Info for planes.
863 */
864 virtual void GetPlanesInfo(DRMPlanesInfo *info) = 0;
865
866 /*
867 * Will provide all the information of a selected crtc.
868 * [input]: Use crtc id 0 to obtain system wide info
869 * [output]: DRMCrtcInfo: Resource Info for the given CRTC id.
Mathew Joseph Karimpanal43c9d692018-06-14 13:45:27 +0530870 * [return]: 0 on success, a negative error value otherwise.
Saurabh Shah66c941b2016-07-06 17:34:05 -0700871 */
Mathew Joseph Karimpanal43c9d692018-06-14 13:45:27 +0530872 virtual int GetCrtcInfo(uint32_t crtc_id, DRMCrtcInfo *info) = 0;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700873
874 /*
875 * Will provide all the information of a selected connector.
876 * [output]: DRMConnectorInfo: Resource Info for the given connector id
Mathew Joseph Karimpanal43c9d692018-06-14 13:45:27 +0530877 * [return]: 0 on success, a negative error value otherwise.
Saurabh Shah66c941b2016-07-06 17:34:05 -0700878 */
Mathew Joseph Karimpanal43c9d692018-06-14 13:45:27 +0530879 virtual int GetConnectorInfo(uint32_t conn_id, DRMConnectorInfo *info) = 0;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700880
881 /*
Mathew Joseph Karimpanal731bc932017-11-22 10:04:56 +0530882 * Provides information on all connectors.
883 * [output]: DRMConnectorsInfo: Resource info for connectors.
884 * [return]: 0 on success, a negative error value otherwise.
885 */
886 virtual int GetConnectorsInfo(DRMConnectorsInfo *info) = 0;
887
888 /*
889 * Provides information on a selected encoder.
890 * [output]: DRMEncoderInfo: Resource info for the given encoder id.
891 * [return]: 0 on success, a negative error value otherwise.
892 */
893 virtual int GetEncoderInfo(uint32_t encoder_id, DRMEncoderInfo *info) = 0;
894
895 /*
896 * Provides information on all encoders.
897 * [output]: DRMEncodersInfo: Resource info for encoders.
898 * [return]: 0 on success, a negative error value otherwise.
899 */
900 virtual int GetEncodersInfo(DRMEncodersInfo *info) = 0;
901
902 /*
Ping Li281f48d2017-01-16 12:45:40 -0800903 * Will query post propcessing feature info of a CRTC.
904 * [output]: DRMPPFeatureInfo: CRTC post processing feature info
905 */
Namit Solanki24921ab2017-05-23 20:16:25 +0530906 virtual void GetCrtcPPInfo(uint32_t crtc_id, DRMPPFeatureInfo *info) = 0;
Mathew Joseph Karimpanal731bc932017-11-22 10:04:56 +0530907
Ping Li281f48d2017-01-16 12:45:40 -0800908 /*
Saurabh Shah66c941b2016-07-06 17:34:05 -0700909 * Register a logical display to receive a token.
Mathew Joseph Karimpanal731bc932017-11-22 10:04:56 +0530910 * Each display pipeline in DRM is identified by its CRTC and Connector(s). On display connect
911 * (bootup or hotplug), clients should invoke this interface to establish the pipeline for the
912 * display and should get a DisplayToken populated with crtc, encoder and connnector(s) id's. Here
913 * onwards, Client should use this token to represent the display for any Perform operations if
Saurabh Shah66c941b2016-07-06 17:34:05 -0700914 * needed.
915 *
916 * [input]: disp_type - Peripheral / TV / Virtual
Mathew Joseph Karimpanal731bc932017-11-22 10:04:56 +0530917 * [output]: DRMDisplayToken - CRTC and Connector IDs for the display.
918 * [return]: 0 on success, a negative error value otherwise.
Saurabh Shah66c941b2016-07-06 17:34:05 -0700919 */
920 virtual int RegisterDisplay(DRMDisplayType disp_type, DRMDisplayToken *tok) = 0;
921
Mathew Joseph Karimpanal731bc932017-11-22 10:04:56 +0530922 /*
923 * Register a logical display to receive a token.
924 * Each display pipeline in DRM is identified by its CRTC and Connector(s). On display connect
925 * (bootup or hotplug), clients should invoke this interface to establish the pipeline for the
926 * display and should get a DisplayToken populated with crtc, encoder and connnector(s) id's. Here
927 * onwards, Client should use this token to represent the display for any Perform operations if
928 * needed.
929 *
930 * [input]: display_id - Connector ID
931 * [output]: DRMDisplayToken - CRTC and Connector id's for the display.
932 * [return]: 0 on success, a negative error value otherwise.
933 */
Varun Arora771fcd22019-02-07 18:08:18 -0800934 virtual int RegisterDisplay(int32_t display_id, DRMDisplayToken *token) = 0;
Mathew Joseph Karimpanal731bc932017-11-22 10:04:56 +0530935
Saurabh Shah66c941b2016-07-06 17:34:05 -0700936 /* Client should invoke this interface on display disconnect.
937 * [input]: DRMDisplayToken - identifier for the display.
938 */
Varun Arora771fcd22019-02-07 18:08:18 -0800939 virtual void UnregisterDisplay(DRMDisplayToken *token) = 0;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700940
941 /*
942 * Creates and returns an instance of DRMAtomicReqInterface corresponding to a display token
943 * returned as part of RegisterDisplay API. Needs to be called per display.
944 * [input]: DRMDisplayToken that identifies a display pipeline
945 * [output]: Pointer to an instance of DRMAtomicReqInterface.
946 * [return]: Error code if the API fails, 0 on success.
947 */
948 virtual int CreateAtomicReq(const DRMDisplayToken &token, DRMAtomicReqInterface **intf) = 0;
949
950 /*
951 * Destroys the instance of DRMAtomicReqInterface
952 * [input]: Pointer to a DRMAtomicReqInterface
953 * [return]: Error code if the API fails, 0 on success.
954 */
955 virtual int DestroyAtomicReq(DRMAtomicReqInterface *intf) = 0;
Varun Arorabaa16472018-08-16 16:19:59 -0700956
Saurabh Shah0ffee302016-11-22 10:42:11 -0800957 /*
958 * Sets the global scaler LUT
959 * [input]: LUT Info
960 * [return]: Error code if the API fails, 0 on success.
961 */
962 virtual int SetScalerLUT(const DRMScalerLUTInfo &lut_info) = 0;
Xu Yang32e58c22017-11-20 09:58:11 +0800963
964 /*
Varun Arorabaa16472018-08-16 16:19:59 -0700965 * Unsets the global scaler LUT
966 * [input]: None
967 * [return]: Error code if the API fails, 0 on success.
968 */
969 virtual int UnsetScalerLUT() = 0;
970
971 /*
Xu Yang32e58c22017-11-20 09:58:11 +0800972 * Get the DPPS feature info
973 * [input]: Dpps feature id, info->id
974 * [output]: Dpps feature version, info->version
975 */
976 virtual void GetDppsFeatureInfo(DRMDppsFeatureInfo *info) = 0;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700977};
Saurabh Shah0ffee302016-11-22 10:42:11 -0800978
Saurabh Shah66c941b2016-07-06 17:34:05 -0700979} // namespace sde_drm
980#endif // __DRM_INTERFACE_H__