Blame - compiler/dex/quick/x86/assemble_x86.cc - platform_art

2014-02-19 20:06:20 -0800

[diff] [blame]

178

{ kX86Lea32RM, kRegMem, IS_TERTIARY_OP | IS_LOAD | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RM", "!0r,[!1r+!2d]" },

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Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

180

{ kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

182

{ kX86Cmov32RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, {0, 0, 0x0F, 0x40, 0, 0, 0, 0}, "Cmovcc32RR", "!2c !0r,!1r" },

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Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \

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{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \

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{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \

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{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \

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{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }

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SHIFT_ENCODING_MAP(Rol, 0x0),

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SHIFT_ENCODING_MAP(Ror, 0x1),

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SHIFT_ENCODING_MAP(Rcl, 0x2),

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SHIFT_ENCODING_MAP(Rcr, 0x3),

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SHIFT_ENCODING_MAP(Sal, 0x4),

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SHIFT_ENCODING_MAP(Shr, 0x5),

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SHIFT_ENCODING_MAP(Sar, 0x7),

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#undef SHIFT_ENCODING_MAP

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{ kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0}, "Cmc", "" },

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

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{ kX86Shld32RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1}, "Shld32", "!0r,!1r,!2d" },

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{ kX86Shrd32RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1}, "Shrd32", "!0r,!1r,!2d" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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{ kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" },

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{ kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" },

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{ kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" },

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{ kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" },

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{ kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" },

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{ kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" },

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{ kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0}, "Test32RR", "!0r,!1r" },

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#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \

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reg, reg_kind, reg_flags, \

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mem, mem_kind, mem_flags, \

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arr, arr_kind, arr_flags, imm, \

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b_flags, hw_flags, w_flags, \

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b_format, hw_format, w_format) \

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{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, #b_format "!0r" }, \

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{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, #b_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, #b_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, #hw_format "!0r" }, \

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{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, #hw_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, #hw_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, #w_format "!0r" }, \

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{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, #w_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, #w_format "[!0r+!1r<<!2d+!3d]" }

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UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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Mark Mendell

2bf31e6

2014-01-23 12:13:40 -0800

[diff] [blame]

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UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

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UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

Brian Carlstrom

2013-07-12 13:46:57 -0700

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#undef UNARY_ENCODING_MAP

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Mark Mendell

2bf31e6

2014-01-23 12:13:40 -0800

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{ kx86Cdq32Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { 0, 0, 0x99, 0, 0, 0, 0, 0 }, "Cdq", "" },

Vladimir Marko

a6fd8ba

2013-12-13 10:53:49 +0000

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{ kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0 }, "Bswap32R", "!0r" },

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{ kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0 }, "Push32R", "!0r" },

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{ kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0 }, "Pop32R", "!0r" },

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

259

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \

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{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

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{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

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EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),

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{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

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{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),

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{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

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{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0),

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EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0),

Razvan A Lupusoru

d3266bc

2014-01-24 12:55:31 -0800

[diff] [blame]

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EXT_0F_ENCODING_MAP(Punpckldq, 0x66, 0x62, REG_DEF0),

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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{ kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" },

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{ kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" },

Mark Mendell

bff1ef0

2013-12-13 13:47:34 -0800

[diff] [blame]

299

{ kX86SqrtsdRR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0xF2, 0, 0x0F, 0x51, 0, 0, 0, 0 }, "SqrtsdRR", "!0r,!1r" },

Razvan A Lupusoru

614c2b4

2014-01-28 17:05:21 -0800

[diff] [blame]

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Serguei Katkov

e90501d

2014-03-12 15:56:54 +0700

[diff] [blame]

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{ kX86Fild32M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDB, 0x00, 0, 0, 0, 0 }, "Fild32M", "[!0r,!1d]" },

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{ kX86Fild64M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDF, 0x00, 0, 5, 0, 0 }, "Fild64M", "[!0r,!1d]" },

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{ kX86Fstp32M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 3, 0, 0 }, "FstpsM", "[!0r,!1d]" },

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{ kX86Fstp64M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0 }, "FstpdM", "[!0r,!1d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

305

Razvan A Lupusoru

2c498d1

2014-01-29 16:02:57 -0800

[diff] [blame]

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EXT_0F_ENCODING_MAP(Movups, 0x0, 0x10, REG_DEF0),

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{ kX86MovupsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovupsMR", "[!0r+!1d],!2r" },

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{ kX86MovupsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovupsAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movaps, 0x0, 0x28, REG_DEF0),

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{ kX86MovapsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0 }, "MovapsMR", "[!0r+!1d],!2r" },

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{ kX86MovapsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0 }, "MovapsAR", "[!0r+!1r<<!2d+!3d],!4r" },

313

314

{ kX86MovlpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0 }, "MovlpsRM", "!0r,[!1r+!2d]" },

315

{ kX86MovlpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0 }, "MovlpsRA", "!0r,[!1r+!2r<<!3d+!4d]" },

316

{ kX86MovlpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0 }, "MovlpsMR", "[!0r+!1d],!2r" },

317

{ kX86MovlpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0 }, "MovlpsAR", "[!0r+!1r<<!2d+!3d],!4r" },

318

319

{ kX86MovhpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0 }, "MovhpsRM", "!0r,[!1r+!2d]" },

320

{ kX86MovhpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0 }, "MovhpsRA", "!0r,[!1r+!2r<<!3d+!4d]" },

321

{ kX86MovhpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0 }, "MovhpsMR", "[!0r+!1d],!2r" },

322

{ kX86MovhpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0 }, "MovhpsAR", "[!0r+!1r<<!2d+!3d],!4r" },

323

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

324

EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),

325

{ kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" },

326

{ kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" },

327

{ kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },

328

329

{ kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

330

{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

331

{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

332

333

// TODO: load/store?

334

// Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.

335

{ kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },

336

337

EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES),

338

EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES),

339

340

{ kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" },

341

{ kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" },

342

{ kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

343

{ kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" },

344

{ kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Vladimir Marko

70b797d

2013-12-03 15:25:24 +0000

[diff] [blame]

345

{ kX86LockCmpxchg8bM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1d]" },

346

{ kX86LockCmpxchg8bA, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

347

348

EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),

349

EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),

350

EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),

351

EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),

352

#undef EXT_0F_ENCODING_MAP

353

354

{ kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },

355

{ kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },

356

{ kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },

357

{ kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },

358

{ kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" },

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

359

{ kX86Jecxz8, kJmp, NO_OPERAND | IS_BRANCH | NEEDS_FIXUP | REG_USEC, { 0, 0, 0xE3, 0, 0, 0, 0, 0 }, "Jecxz", "!0t" },

Brian Carlstrom

60d7a65

2014-03-13 18:10:08 -0700

[diff] [blame]

360

{ kX86JmpT, kJmp, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpT", "fs:[!0d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

361

{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

362

{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

363

{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

364

{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

365

{ kX86CallI, kCall, IS_UNARY_OP | IS_BRANCH, { 0, 0, 0xE8, 0, 0, 0, 0, 4 }, "CallI", "!0d" },

Brian Carlstrom

b1eba21

2013-07-17 18:07:19 -0700

[diff] [blame]

366

{ kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

367

368

{ kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" },

369

{ kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },

370

{ kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" },

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

371

{ kX86RepneScasw, kPrefix2Nullary, NO_OPERAND | SETS_CCODES, { 0x66, 0xF2, 0xAF, 0, 0, 0, 0, 0 }, "RepNE ScasW", "" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

372

};

373

374

static size_t ComputeSize(const X86EncodingMap* entry, int base, int displacement, bool has_sib) {

375

size_t size = 0;

376

if (entry->skeleton.prefix1 > 0) {

377

++size;

378

if (entry->skeleton.prefix2 > 0) {

++size;

}

}

++size; // opcode

if (entry->skeleton.opcode == 0x0F) {

384

++size;

385

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

if (has_sib || base == rX86_SP) {

391

// SP requires a SIB byte.

392

++size;

393

}

394

if (displacement != 0 || base == rBP) {

395

// BP requires an explicit displacement, even when it's 0.

396

if (entry->opcode != kX86Lea32RA) {

397

DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name;

398

}

399

size += IS_SIMM8(displacement) ? 1 : 4;

400

}

401

size += entry->skeleton.immediate_bytes;

return size;

}

int X86Mir2Lir::GetInsnSize(LIR* lir) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

406

DCHECK(!IsPseudoLirOp(lir->opcode));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

407

const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode];

408

switch (entry->kind) {

409

case kData:

410

return 4; // 4 bytes of data

411

case kNop:

412

return lir->operands[0]; // length of nop is sole operand

413

case kNullary:

414

return 1; // 1 byte of opcode

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

415

case kPrefix2Nullary:

416

return 3; // 1 byte of opcode + 2 prefixes

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

417

case kRegOpcode: // lir operands - 0: reg

418

return ComputeSize(entry, 0, 0, false) - 1; // substract 1 for modrm

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

419

case kReg: // lir operands - 0: reg

420

return ComputeSize(entry, 0, 0, false);

421

case kMem: // lir operands - 0: base, 1: disp

422

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

423

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

424

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

425

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

426

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

427

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

428

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

429

case kThreadReg: // lir operands - 0: disp, 1: reg

430

return ComputeSize(entry, 0, lir->operands[0], false);

431

case kRegReg:

432

return ComputeSize(entry, 0, 0, false);

433

case kRegRegStore:

434

return ComputeSize(entry, 0, 0, false);

435

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

436

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

437

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

438

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

439

case kRegThread: // lir operands - 0: reg, 1: disp

440

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

441

case kRegImm: { // lir operands - 0: reg, 1: immediate

442

size_t size = ComputeSize(entry, 0, 0, false);

443

if (entry->skeleton.ax_opcode == 0) {

444

return size;

445

} else {

446

// AX opcodes don't require the modrm byte.

447

int reg = lir->operands[0];

448

return size - (reg == rAX ? 1 : 0);

449

}

450

}

451

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

452

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

453

case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

454

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

455

case kThreadImm: // lir operands - 0: disp, 1: imm

456

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

457

case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

458

case kRegRegImmRev:

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

459

return ComputeSize(entry, 0, 0, false);

460

case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

461

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

462

case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

463

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

464

case kMovRegImm: // lir operands - 0: reg, 1: immediate

465

return 1 + entry->skeleton.immediate_bytes;

466

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

467

// Shift by immediate one has a shorter opcode.

468

return ComputeSize(entry, 0, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

469

case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

470

// Shift by immediate one has a shorter opcode.

471

return ComputeSize(entry, lir->operands[0], lir->operands[1], false) -

472

(lir->operands[2] == 1 ? 1 : 0);

473

case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

474

// Shift by immediate one has a shorter opcode.

475

return ComputeSize(entry, lir->operands[0], lir->operands[3], true) -

476

(lir->operands[4] == 1 ? 1 : 0);

477

case kShiftRegCl:

478

return ComputeSize(entry, 0, 0, false);

479

case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

480

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

481

case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

482

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

483

case kRegCond: // lir operands - 0: reg, 1: cond

484

return ComputeSize(entry, 0, 0, false);

485

case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

486

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

487

case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

488

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

489

case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: cond

490

return ComputeSize(entry, 0, 0, false);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

491

case kJcc:

492

if (lir->opcode == kX86Jcc8) {

493

return 2; // opcode + rel8

494

} else {

495

DCHECK(lir->opcode == kX86Jcc32);

496

return 6; // 2 byte opcode + rel32

497

}

498

case kJmp:

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

499

if (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jecxz8) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

500

return 2; // opcode + rel8

501

} else if (lir->opcode == kX86Jmp32) {

502

return 5; // opcode + rel32

Brian Carlstrom

60d7a65

2014-03-13 18:10:08 -0700

[diff] [blame]

503

} else if (lir->opcode == kX86JmpT) {

504

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

505

} else {

506

DCHECK(lir->opcode == kX86JmpR);

507

return 2; // opcode + modrm

508

}

509

case kCall:

510

switch (lir->opcode) {

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

511

case kX86CallI: return 5; // opcode 0:disp

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

512

case kX86CallR: return 2; // opcode modrm

513

case kX86CallM: // lir operands - 0: base, 1: disp

514

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

515

case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

516

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

517

case kX86CallT: // lir operands - 0: disp

518

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

default:

break;

}

break;

case kPcRel:

if (entry->opcode == kX86PcRelLoadRA) {

525

// lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

526

return ComputeSize(entry, lir->operands[1], 0x12345678, true);

527

} else {

528

DCHECK(entry->opcode == kX86PcRelAdr);

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

529

return 5; // opcode with reg + 4 byte immediate

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

530

}

531

case kMacro:

532

DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));

533

return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +

534

ComputeSize(&X86Mir2Lir::EncodingMap[kX86Sub32RI], 0, 0, false) -

535

(lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

return 0;

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

543

void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry) {

544

if (entry->skeleton.prefix1 != 0) {

545

code_buffer_.push_back(entry->skeleton.prefix1);

546

if (entry->skeleton.prefix2 != 0) {

547

code_buffer_.push_back(entry->skeleton.prefix2);

548

}

549

} else {

550

DCHECK_EQ(0, entry->skeleton.prefix2);

}

}

void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) {

555

code_buffer_.push_back(entry->skeleton.opcode);

556

if (entry->skeleton.opcode == 0x0F) {

557

code_buffer_.push_back(entry->skeleton.extra_opcode1);

558

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

559

code_buffer_.push_back(entry->skeleton.extra_opcode2);

560

} else {

561

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

562

}

563

} else {

564

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

565

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

}

}

void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry) {

EmitPrefix(entry);

EmitOpcode(entry);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

574

static uint8_t ModrmForDisp(int base, int disp) {

575

// BP requires an explicit disp, so do not omit it in the 0 case

576

if (disp == 0 && base != rBP) {

577

return 0;

578

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

585

void X86Mir2Lir::EmitDisp(uint8_t base, int disp) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

586

// BP requires an explicit disp, so do not omit it in the 0 case

587

if (disp == 0 && base != rBP) {

588

return;

589

} else if (IS_SIMM8(disp)) {

590

code_buffer_.push_back(disp & 0xFF);

591

} else {

592

code_buffer_.push_back(disp & 0xFF);

593

code_buffer_.push_back((disp >> 8) & 0xFF);

594

code_buffer_.push_back((disp >> 16) & 0xFF);

595

code_buffer_.push_back((disp >> 24) & 0xFF);

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

599

void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp) {

600

DCHECK_LT(reg_or_opcode, 8);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

601

DCHECK_LT(base, 8);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

602

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | base;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

603

code_buffer_.push_back(modrm);

604

if (base == rX86_SP) {

605

// Special SIB for SP base

606

code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);

607

}

608

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

609

}

610

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

611

void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index,

612

int scale, int disp) {

613

DCHECK_LT(reg_or_opcode, 8);

614

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | rX86_SP;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

615

code_buffer_.push_back(modrm);

DCHECK_LT(scale, 4);

DCHECK_LT(index, 8);

DCHECK_LT(base, 8);

uint8_t sib = (scale << 6) | (index << 3) | base;

620

code_buffer_.push_back(sib);

621

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

622

}

623

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

624

void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int imm) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

625

switch (entry->skeleton.immediate_bytes) {

626

case 1:

627

DCHECK(IS_SIMM8(imm));

628

code_buffer_.push_back(imm & 0xFF);

629

break;

630

case 2:

631

DCHECK(IS_SIMM16(imm));

632

code_buffer_.push_back(imm & 0xFF);

633

code_buffer_.push_back((imm >> 8) & 0xFF);

634

break;

635

case 4:

636

code_buffer_.push_back(imm & 0xFF);

637

code_buffer_.push_back((imm >> 8) & 0xFF);

638

code_buffer_.push_back((imm >> 16) & 0xFF);

639

code_buffer_.push_back((imm >> 24) & 0xFF);

640

break;

641

default:

642

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

643

<< ") for instruction: " << entry->name;

break;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

648

void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg) {

649

EmitPrefixAndOpcode(entry);

650

// There's no 3-byte instruction with +rd

651

DCHECK(entry->skeleton.opcode != 0x0F ||

652

(entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A));

653

DCHECK(!X86_FPREG(reg));

654

DCHECK_LT(reg, 8);

655

code_buffer_.back() += reg;

656

DCHECK_EQ(0, entry->skeleton.ax_opcode);

657

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

658

}

659

660

void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) {

661

EmitPrefixAndOpcode(entry);

662

if (X86_FPREG(reg)) {

663

reg = reg & X86_FP_REG_MASK;

664

}

665

if (reg >= 4) {

666

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

667

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

668

}

669

DCHECK_LT(reg, 8);

670

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

671

code_buffer_.push_back(modrm);

672

DCHECK_EQ(0, entry->skeleton.ax_opcode);

673

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

674

}

675

676

void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) {

677

EmitPrefix(entry);

678

code_buffer_.push_back(entry->skeleton.opcode);

679

DCHECK_NE(0x0F, entry->skeleton.opcode);

680

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

681

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

682

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

683

DCHECK_EQ(0, entry->skeleton.ax_opcode);

684

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

685

}

686

687

void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index,

688

int scale, int disp) {

689

EmitPrefixAndOpcode(entry);

690

EmitModrmSibDisp(entry->skeleton.modrm_opcode, base, index, scale, disp);

691

DCHECK_EQ(0, entry->skeleton.ax_opcode);

692

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

693

}

694

695

void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry,

696

uint8_t base, int disp, uint8_t reg) {

697

EmitPrefixAndOpcode(entry);

698

if (X86_FPREG(reg)) {

699

reg = reg & X86_FP_REG_MASK;

700

}

701

if (reg >= 4) {

702

DCHECK(strchr(entry->name, '8') == NULL ||

703

entry->opcode == kX86Movzx8RM || entry->opcode == kX86Movsx8RM)

704

<< entry->name << " " << static_cast<int>(reg)

705

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

706

}

707

EmitModrmDisp(reg, base, disp);

708

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

709

DCHECK_EQ(0, entry->skeleton.ax_opcode);

710

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

711

}

712

713

void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry,

714

uint8_t reg, uint8_t base, int disp) {

715

// Opcode will flip operands.

716

EmitMemReg(entry, base, disp, reg);

717

}

718

719

void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index,

720

int scale, int disp) {

721

EmitPrefixAndOpcode(entry);

722

if (X86_FPREG(reg)) {

723

reg = reg & X86_FP_REG_MASK;

724

}

725

EmitModrmSibDisp(reg, base, index, scale, disp);

726

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

727

DCHECK_EQ(0, entry->skeleton.ax_opcode);

728

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

729

}

730

731

void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp,

732

uint8_t reg) {

733

// Opcode will flip operands.

734

EmitRegArray(entry, reg, base, index, scale, disp);

735

}

736

737

void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) {

738

DCHECK_NE(entry->skeleton.prefix1, 0);

739

EmitPrefixAndOpcode(entry);

740

if (X86_FPREG(reg)) {

741

reg = reg & X86_FP_REG_MASK;

742

}

743

if (reg >= 4) {

744

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

745

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

746

}

747

DCHECK_LT(reg, 8);

748

uint8_t modrm = (0 << 6) | (reg << 3) | rBP;

749

code_buffer_.push_back(modrm);

750

code_buffer_.push_back(disp & 0xFF);

751

code_buffer_.push_back((disp >> 8) & 0xFF);

752

code_buffer_.push_back((disp >> 16) & 0xFF);

753

code_buffer_.push_back((disp >> 24) & 0xFF);

754

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

755

DCHECK_EQ(0, entry->skeleton.ax_opcode);

756

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

757

}

758

759

void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) {

760

EmitPrefixAndOpcode(entry);

761

if (X86_FPREG(reg1)) {

762

reg1 = reg1 & X86_FP_REG_MASK;

763

}

764

if (X86_FPREG(reg2)) {

765

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

770

code_buffer_.push_back(modrm);

771

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

772

DCHECK_EQ(0, entry->skeleton.ax_opcode);

773

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

774

}

775

776

void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry,

777

uint8_t reg1, uint8_t reg2, int32_t imm) {

778

EmitPrefixAndOpcode(entry);

779

if (X86_FPREG(reg1)) {

780

reg1 = reg1 & X86_FP_REG_MASK;

781

}

782

if (X86_FPREG(reg2)) {

783

reg2 = reg2 & X86_FP_REG_MASK;

}

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;

788

code_buffer_.push_back(modrm);

789

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

790

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

794

void X86Mir2Lir::EmitRegRegImmRev(const X86EncodingMap* entry,

795

uint8_t reg1, uint8_t reg2, int32_t imm) {

796

EmitRegRegImm(entry, reg2, reg1, imm);

797

}

798

799

void X86Mir2Lir::EmitRegMemImm(const X86EncodingMap* entry,

800

uint8_t reg, uint8_t base, int disp, int32_t imm) {

801

EmitPrefixAndOpcode(entry);

802

DCHECK(!X86_FPREG(reg));

803

DCHECK_LT(reg, 8);

804

EmitModrmDisp(reg, base, disp);

805

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

806

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

810

void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

811

if (entry->skeleton.prefix1 != 0) {

812

code_buffer_.push_back(entry->skeleton.prefix1);

813

if (entry->skeleton.prefix2 != 0) {

814

code_buffer_.push_back(entry->skeleton.prefix2);

815

}

816

} else {

817

DCHECK_EQ(0, entry->skeleton.prefix2);

818

}

819

if (reg == rAX && entry->skeleton.ax_opcode != 0) {

820

code_buffer_.push_back(entry->skeleton.ax_opcode);

821

} else {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

822

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

823

if (X86_FPREG(reg)) {

824

reg = reg & X86_FP_REG_MASK;

825

}

826

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

827

code_buffer_.push_back(modrm);

828

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

829

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

830

}

831

Mark Mendell

343adb5

2013-12-18 06:02:17 -0800

[diff] [blame]

832

void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm) {

833

EmitPrefixAndOpcode(entry);

834

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

835

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

839

void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

840

EmitPrefixAndOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

841

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

842

code_buffer_.push_back(modrm);

843

code_buffer_.push_back(disp & 0xFF);

844

code_buffer_.push_back((disp >> 8) & 0xFF);

845

code_buffer_.push_back((disp >> 16) & 0xFF);

846

code_buffer_.push_back((disp >> 24) & 0xFF);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

847

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

848

DCHECK_EQ(entry->skeleton.ax_opcode, 0);

849

}

850

851

void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

852

DCHECK_LT(reg, 8);

853

code_buffer_.push_back(0xB8 + reg);

854

code_buffer_.push_back(imm & 0xFF);

855

code_buffer_.push_back((imm >> 8) & 0xFF);

856

code_buffer_.push_back((imm >> 16) & 0xFF);

857

code_buffer_.push_back((imm >> 24) & 0xFF);

858

}

859

860

void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

861

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

862

if (imm != 1) {

863

code_buffer_.push_back(entry->skeleton.opcode);

864

} else {

865

// Shorter encoding for 1 bit shift

866

code_buffer_.push_back(entry->skeleton.ax_opcode);

867

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

868

DCHECK_NE(0x0F, entry->skeleton.opcode);

869

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

870

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

871

if (reg >= 4) {

872

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg)

873

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

874

}

875

DCHECK_LT(reg, 8);

876

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

877

code_buffer_.push_back(modrm);

878

if (imm != 1) {

879

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

880

DCHECK(IS_SIMM8(imm));

881

code_buffer_.push_back(imm & 0xFF);

}

}

void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl) {

886

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

887

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

888

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

889

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

890

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

891

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

892

DCHECK_LT(reg, 8);

893

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

894

code_buffer_.push_back(modrm);

895

DCHECK_EQ(0, entry->skeleton.ax_opcode);

896

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

897

}

898

Mark Mendell

feb2b4e

2014-01-28 12:59:49 -0800

[diff] [blame]

899

void X86Mir2Lir::EmitShiftMemCl(const X86EncodingMap* entry, uint8_t base,

900

int displacement, uint8_t cl) {

901

DCHECK_EQ(cl, static_cast<uint8_t>(rCX));

902

EmitPrefix(entry);

903

code_buffer_.push_back(entry->skeleton.opcode);

904

DCHECK_NE(0x0F, entry->skeleton.opcode);

905

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

906

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

907

DCHECK_LT(base, 8);

908

EmitModrmDisp(entry->skeleton.modrm_opcode, base, displacement);

909

DCHECK_EQ(0, entry->skeleton.ax_opcode);

910

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

911

}

912

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

913

void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) {

914

if (entry->skeleton.prefix1 != 0) {

915

code_buffer_.push_back(entry->skeleton.prefix1);

916

if (entry->skeleton.prefix2 != 0) {

917

code_buffer_.push_back(entry->skeleton.prefix2);

918

}

919

} else {

920

DCHECK_EQ(0, entry->skeleton.prefix2);

921

}

922

DCHECK_EQ(0, entry->skeleton.ax_opcode);

923

DCHECK_EQ(0x0F, entry->skeleton.opcode);

924

code_buffer_.push_back(0x0F);

925

DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);

926

code_buffer_.push_back(0x90 | condition);

927

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

928

DCHECK_LT(reg, 8);

929

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

930

code_buffer_.push_back(modrm);

931

DCHECK_EQ(entry->skeleton.immediate_bytes, 0);

932

}

933

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

934

void X86Mir2Lir::EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, uint8_t condition) {

935

// Generate prefix and opcode without the condition

936

EmitPrefixAndOpcode(entry);

937

938

// Now add the condition. The last byte of opcode is the one that receives it.

939

DCHECK_LE(condition, 0xF);

940

code_buffer_.back() += condition;

941

942

// Not expecting to have to encode immediate or do anything special for ModR/M since there are two registers.

943

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

944

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

945

946

// Check that registers requested for encoding are sane.

DCHECK_LT(reg1, 8);

DCHECK_LT(reg2, 8);

// For register to register encoding, the mod is 3.

951

const uint8_t mod = (3 << 6);

952

953

// Encode the ModR/M byte now.

954

const uint8_t modrm = mod | (reg1 << 3) | reg2;

955

code_buffer_.push_back(modrm);

956

}

957

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

958

void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int rel) {

959

if (entry->opcode == kX86Jmp8) {

960

DCHECK(IS_SIMM8(rel));

961

code_buffer_.push_back(0xEB);

962

code_buffer_.push_back(rel & 0xFF);

963

} else if (entry->opcode == kX86Jmp32) {

964

code_buffer_.push_back(0xE9);

965

code_buffer_.push_back(rel & 0xFF);

966

code_buffer_.push_back((rel >> 8) & 0xFF);

967

code_buffer_.push_back((rel >> 16) & 0xFF);

968

code_buffer_.push_back((rel >> 24) & 0xFF);

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

969

} else if (entry->opcode == kX86Jecxz8) {

970

DCHECK(IS_SIMM8(rel));

971

code_buffer_.push_back(0xE3);

972

code_buffer_.push_back(rel & 0xFF);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

973

} else {

974

DCHECK(entry->opcode == kX86JmpR);

975

code_buffer_.push_back(entry->skeleton.opcode);

976

uint8_t reg = static_cast<uint8_t>(rel);

977

DCHECK_LT(reg, 8);

978

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;

979

code_buffer_.push_back(modrm);

}

}

void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc) {

984

DCHECK_LT(cc, 16);

985

if (entry->opcode == kX86Jcc8) {

986

DCHECK(IS_SIMM8(rel));

987

code_buffer_.push_back(0x70 | cc);

988

code_buffer_.push_back(rel & 0xFF);

989

} else {

990

DCHECK(entry->opcode == kX86Jcc32);

991

code_buffer_.push_back(0x0F);

992

code_buffer_.push_back(0x80 | cc);

993

code_buffer_.push_back(rel & 0xFF);

994

code_buffer_.push_back((rel >> 8) & 0xFF);

995

code_buffer_.push_back((rel >> 16) & 0xFF);

996

code_buffer_.push_back((rel >> 24) & 0xFF);

}

}

void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1001

EmitPrefixAndOpcode(entry);

1002

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1003

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1004

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1005

}

1006

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

1007

void X86Mir2Lir::EmitCallImmediate(const X86EncodingMap* entry, int disp) {

1008

EmitPrefixAndOpcode(entry);

1009

DCHECK_EQ(4, entry->skeleton.immediate_bytes);

1010

code_buffer_.push_back(disp & 0xFF);

1011

code_buffer_.push_back((disp >> 8) & 0xFF);

1012

code_buffer_.push_back((disp >> 16) & 0xFF);

1013

code_buffer_.push_back((disp >> 24) & 0xFF);

1014

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1015

}

1016

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1017

void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int disp) {

1018

DCHECK_NE(entry->skeleton.prefix1, 0);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1019

EmitPrefixAndOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1020

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP;

1021

code_buffer_.push_back(modrm);

1022

code_buffer_.push_back(disp & 0xFF);

1023

code_buffer_.push_back((disp >> 8) & 0xFF);

1024

code_buffer_.push_back((disp >> 16) & 0xFF);

1025

code_buffer_.push_back((disp >> 24) & 0xFF);

1026

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1027

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1028

}

1029

1030

void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, uint8_t reg,

1031

int base_or_table, uint8_t index, int scale, int table_or_disp) {

1032

int disp;

1033

if (entry->opcode == kX86PcRelLoadRA) {

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1034

Mir2Lir::EmbeddedData *tab_rec =

1035

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1036

disp = tab_rec->offset;

1037

} else {

1038

DCHECK(entry->opcode == kX86PcRelAdr);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1039

Mir2Lir::EmbeddedData *tab_rec =

1040

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(base_or_table));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1041

disp = tab_rec->offset;

1042

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1043

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1044

if (X86_FPREG(reg)) {

1045

reg = reg & X86_FP_REG_MASK;

1046

}

1047

DCHECK_LT(reg, 8);

1048

if (entry->opcode == kX86PcRelLoadRA) {

1049

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1050

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1051

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1052

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

1053

uint8_t modrm = (2 << 6) | (reg << 3) | rX86_SP;

1054

code_buffer_.push_back(modrm);

1055

DCHECK_LT(scale, 4);

1056

DCHECK_LT(index, 8);

1057

DCHECK_LT(base_or_table, 8);

1058

uint8_t base = static_cast<uint8_t>(base_or_table);

1059

uint8_t sib = (scale << 6) | (index << 3) | base;

1060

code_buffer_.push_back(sib);

1061

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1062

} else {

1063

code_buffer_.push_back(entry->skeleton.opcode + reg);

1064

}

1065

code_buffer_.push_back(disp & 0xFF);

1066

code_buffer_.push_back((disp >> 8) & 0xFF);

1067

code_buffer_.push_back((disp >> 16) & 0xFF);

1068

code_buffer_.push_back((disp >> 24) & 0xFF);

1069

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1070

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1071

}

1072

1073

void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset) {

1074

DCHECK(entry->opcode == kX86StartOfMethod) << entry->name;

1075

code_buffer_.push_back(0xE8); // call +0

1076

code_buffer_.push_back(0);

1077

code_buffer_.push_back(0);

1078

code_buffer_.push_back(0);

1079

code_buffer_.push_back(0);

1080

1081

DCHECK_LT(reg, 8);

1082

code_buffer_.push_back(0x58 + reg); // pop reg

1083

1084

EmitRegImm(&X86Mir2Lir::EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */);

1085

}

1086

1087

void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) {

1088

UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " "

1089

<< BuildInsnString(entry->fmt, lir, 0);

1090

for (int i = 0; i < GetInsnSize(lir); ++i) {

1091

code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3

}

}

/*

* Assemble the LIR into binary instruction format. Note that we may

1097

* discover that pc-relative displacements may not fit the selected

1098

* instruction. In those cases we will try to substitute a new code

1099

* sequence or request that the trace be shortened and retried.

1100

*/

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1101

AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1102

LIR *lir;

1103

AssemblerStatus res = kSuccess; // Assume success

1104

1105

const bool kVerbosePcFixup = false;

1106

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1107

if (IsPseudoLirOp(lir->opcode)) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

continue;

}

if (lir->flags.is_nop) {

continue;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1115

if (lir->flags.fixup != kFixupNone) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1116

switch (lir->opcode) {

1117

case kX86Jcc8: {

1118

LIR *target_lir = lir->target;

1119

DCHECK(target_lir != NULL);

1120

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1121

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1122

if (IS_SIMM8(lir->operands[0])) {

1123

pc = lir->offset + 2 /* opcode + rel8 */;

1124

} else {

1125

pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1126

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1127

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1128

delta = target - pc;

1129

if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1130

if (kVerbosePcFixup) {

1131

LOG(INFO) << "Retry for JCC growth at " << lir->offset

1132

<< " delta: " << delta << " old delta: " << lir->operands[0];

1133

}

1134

lir->opcode = kX86Jcc32;

1135

SetupResourceMasks(lir);

1136

res = kRetryAll;

1137

}

1138

if (kVerbosePcFixup) {

1139

LOG(INFO) << "Source:";

1140

DumpLIRInsn(lir, 0);

1141

LOG(INFO) << "Target:";

1142

DumpLIRInsn(target_lir, 0);

1143

LOG(INFO) << "Delta " << delta;

1144

}

1145

lir->operands[0] = delta;

break;

}

case kX86Jcc32: {

LIR *target_lir = lir->target;

1150

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1151

CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1152

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1153

int delta = target - pc;

1154

if (kVerbosePcFixup) {

1155

LOG(INFO) << "Source:";

1156

DumpLIRInsn(lir, 0);

1157

LOG(INFO) << "Target:";

1158

DumpLIRInsn(target_lir, 0);

1159

LOG(INFO) << "Delta " << delta;

1160

}

1161

lir->operands[0] = delta;

1162

break;

1163

}

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

1164

case kX86Jecxz8: {

1165

LIR *target_lir = lir->target;

1166

DCHECK(target_lir != NULL);

1167

CodeOffset pc;

1168

pc = lir->offset + 2; // opcode + rel8

1169

CodeOffset target = target_lir->offset;

1170

int delta = target - pc;

1171

lir->operands[0] = delta;

1172

DCHECK(IS_SIMM8(delta));

1173

break;

1174

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1175

case kX86Jmp8: {

1176

LIR *target_lir = lir->target;

1177

DCHECK(target_lir != NULL);

1178

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1179

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1180

if (IS_SIMM8(lir->operands[0])) {

1181

pc = lir->offset + 2 /* opcode + rel8 */;

1182

} else {

1183

pc = lir->offset + 5 /* opcode + rel32 */;

1184

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1185

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1186

delta = target - pc;

1187

if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) {

1188

// Useless branch

buzbee

252254b

2013-09-08 16:20:53 -0700

[diff] [blame]

1189

NopLIR(lir);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1190

if (kVerbosePcFixup) {

1191

LOG(INFO) << "Retry for useless branch at " << lir->offset;

1192

}

1193

res = kRetryAll;

1194

} else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1195

if (kVerbosePcFixup) {

1196

LOG(INFO) << "Retry for JMP growth at " << lir->offset;

1197

}

1198

lir->opcode = kX86Jmp32;

1199

SetupResourceMasks(lir);

1200

res = kRetryAll;

1201

}

1202

lir->operands[0] = delta;

break;

}

case kX86Jmp32: {

LIR *target_lir = lir->target;

1207

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1208

CodeOffset pc = lir->offset + 5 /* opcode + rel32 */;

1209

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1210

int delta = target - pc;

1211

lir->operands[0] = delta;

1212

break;

1213

}

1214

default:

Mark Mendell

67c39c4

2014-01-31 17:28:00 -0800

[diff] [blame]

1215

if (lir->flags.fixup == kFixupLoad) {

1216

LIR *target_lir = lir->target;

1217

DCHECK(target_lir != NULL);

1218

CodeOffset target = target_lir->offset;

1219

lir->operands[2] = target;

1220

int newSize = GetInsnSize(lir);

1221

if (newSize != lir->flags.size) {

1222

lir->flags.size = newSize;

1223

res = kRetryAll;

1224

}

1225

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

break;

}

}

/*

* If one of the pc-relative instructions expanded we'll have

1232

* to make another pass. Don't bother to fully assemble the

1233

* instruction.

1234

*/

1235

if (res != kSuccess) {

1236

continue;

1237

}

1238

CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size());

1239

const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode];

1240

size_t starting_cbuf_size = code_buffer_.size();

1241

switch (entry->kind) {

1242

case kData: // 4 bytes of data

1243

code_buffer_.push_back(lir->operands[0]);

1244

break;

1245

case kNullary: // 1 byte of opcode

1246

DCHECK_EQ(0, entry->skeleton.prefix1);

1247

DCHECK_EQ(0, entry->skeleton.prefix2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1248

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1249

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1250

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1251

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1252

break;

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

1253

case kPrefix2Nullary: // 1 byte of opcode + 2 prefixes.

1254

DCHECK_NE(0, entry->skeleton.prefix1);

1255

DCHECK_NE(0, entry->skeleton.prefix2);

1256

EmitPrefixAndOpcode(entry);

1257

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1258

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1259

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1260

break;

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

1261

case kRegOpcode: // lir operands - 0: reg

1262

EmitOpRegOpcode(entry, lir->operands[0]);

1263

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1264

case kReg: // lir operands - 0: reg

1265

EmitOpReg(entry, lir->operands[0]);

1266

break;

1267

case kMem: // lir operands - 0: base, 1: disp

1268

EmitOpMem(entry, lir->operands[0], lir->operands[1]);

1269

break;

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1270

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

1271

EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]);

1272

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1273

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

1274

EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1275

break;

Mark Mendell

343adb5

2013-12-18 06:02:17 -0800

[diff] [blame]

1276

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

1277

EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1278

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1279

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

1280

EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1281

lir->operands[3], lir->operands[4]);

1282

break;

1283

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

1284

EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1285

break;

1286

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

1287

EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1288

lir->operands[3], lir->operands[4]);

1289

break;

1290

case kRegThread: // lir operands - 0: reg, 1: disp

1291

EmitRegThread(entry, lir->operands[0], lir->operands[1]);

1292

break;

1293

case kRegReg: // lir operands - 0: reg1, 1: reg2

1294

EmitRegReg(entry, lir->operands[0], lir->operands[1]);

1295

break;

1296

case kRegRegStore: // lir operands - 0: reg2, 1: reg1

1297

EmitRegReg(entry, lir->operands[1], lir->operands[0]);

1298

break;

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

1299

case kRegRegImmRev:

1300

EmitRegRegImmRev(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1301

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1302

case kRegRegImm:

1303

EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1304

break;

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

1305

case kRegMemImm:

1306

EmitRegMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1307

lir->operands[3]);

1308

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1309

case kRegImm: // lir operands - 0: reg, 1: immediate

1310

EmitRegImm(entry, lir->operands[0], lir->operands[1]);

1311

break;

1312

case kThreadImm: // lir operands - 0: disp, 1: immediate

1313

EmitThreadImm(entry, lir->operands[0], lir->operands[1]);

1314

break;

1315

case kMovRegImm: // lir operands - 0: reg, 1: immediate

1316

EmitMovRegImm(entry, lir->operands[0], lir->operands[1]);

1317

break;

1318

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

1319

EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]);

1320

break;

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

1321

case kShiftRegCl: // lir operands - 0: reg, 1: cl

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1322

EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]);

1323

break;

Mark Mendell

feb2b4e

2014-01-28 12:59:49 -0800

[diff] [blame]

1324

case kShiftMemCl: // lir operands - 0: base, 1:displacement, 2: cl

1325

EmitShiftMemCl(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1326

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1327

case kRegCond: // lir operands - 0: reg, 1: condition

1328

EmitRegCond(entry, lir->operands[0], lir->operands[1]);

1329

break;

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

1330

case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: condition

1331

EmitRegRegCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1332

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1333

case kJmp: // lir operands - 0: rel

Brian Carlstrom

60d7a65

2014-03-13 18:10:08 -0700

[diff] [blame]

1334

if (entry->opcode == kX86JmpT) {

1335

// This works since the instruction format for jmp and call is basically the same and

1336

// EmitCallThread loads opcode info.

1337

EmitCallThread(entry, lir->operands[0]);

1338

} else {

1339

EmitJmp(entry, lir->operands[0]);

1340

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1341

break;

1342

case kJcc: // lir operands - 0: rel, 1: CC, target assigned

1343

EmitJcc(entry, lir->operands[0], lir->operands[1]);

1344

break;

1345

case kCall:

1346

switch (entry->opcode) {

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

1347

case kX86CallI: // lir operands - 0: disp

1348

EmitCallImmediate(entry, lir->operands[0]);

1349

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1350

case kX86CallM: // lir operands - 0: base, 1: disp

1351

EmitCallMem(entry, lir->operands[0], lir->operands[1]);

1352

break;

1353

case kX86CallT: // lir operands - 0: disp

1354

EmitCallThread(entry, lir->operands[0]);

1355

break;

1356

default:

1357

EmitUnimplemented(entry, lir);

break;

}

break;

case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

1362

EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1363

lir->operands[3], lir->operands[4]);

1364

break;

1365

case kMacro:

1366

EmitMacro(entry, lir->operands[0], lir->offset);

1367

break;

1368

default:

1369

EmitUnimplemented(entry, lir);

1370

break;

1371

}

1372

CHECK_EQ(static_cast<size_t>(GetInsnSize(lir)),

1373

code_buffer_.size() - starting_cbuf_size)

1374

<< "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name;

}

return res;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1379

// LIR offset assignment.

1380

// TODO: consolidate w/ Arm assembly mechanism.

1381

int X86Mir2Lir::AssignInsnOffsets() {

LIR* lir;

int offset = 0;

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

1386

lir->offset = offset;

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1387

if (LIKELY(!IsPseudoLirOp(lir->opcode))) {

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1388

if (!lir->flags.is_nop) {

1389

offset += lir->flags.size;

1390

}

1391

} else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) {

1392

if (offset & 0x2) {

1393

offset += 2;

1394

lir->operands[0] = 1;

1395

} else {

1396

lir->operands[0] = 0;

1397

}

1398

}

1399

/* Pseudo opcodes don't consume space */

}

return offset;

}

/*

* Walk the compilation unit and assign offsets to instructions

1406

* and literals and compute the total size of the compiled unit.

1407

* TODO: consolidate w/ Arm assembly mechanism.

1408

*/

1409

void X86Mir2Lir::AssignOffsets() {

1410

int offset = AssignInsnOffsets();

1411

1412

/* Const values have to be word aligned */

1413

offset = (offset + 3) & ~3;

1414

1415

/* Set up offsets for literals */

1416

data_offset_ = offset;

1417

1418

offset = AssignLiteralOffset(offset);

1419

1420

offset = AssignSwitchTablesOffset(offset);

1421

1422

offset = AssignFillArrayDataOffset(offset);

1423

1424

total_size_ = offset;

}

/*

* Go over each instruction in the list and calculate the offset from the top

1429

* before sending them off to the assembler. If out-of-range branch distance is

1430

* seen rearrange the instructions a bit to correct it.

1431

* TODO: consolidate w/ Arm assembly mechanism.

1432

*/

1433

void X86Mir2Lir::AssembleLIR() {

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1434

cu_->NewTimingSplit("Assemble");

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

1435

1436

// We will remove the method address if we never ended up using it

1437

if (store_method_addr_ && !store_method_addr_used_) {

1438

setup_method_address_[0]->flags.is_nop = true;

1439

setup_method_address_[1]->flags.is_nop = true;

1440

}

1441

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1442

AssignOffsets();

1443

int assembler_retries = 0;

1444

/*

1445

* Assemble here. Note that we generate code with optimistic assumptions

1446

* and if found now to work, we'll have to redo the sequence and retry.

*/

while (true) {

AssemblerStatus res = AssembleInstructions(0);

1451

if (res == kSuccess) {

break;

} else {

assembler_retries++;

if (assembler_retries > MAX_ASSEMBLER_RETRIES) {

1456

CodegenDump();

1457

LOG(FATAL) << "Assembler error - too many retries";

1458

}

1459

// Redo offsets and try again

1460

AssignOffsets();

1461

code_buffer_.clear();

}

}

// Install literals

InstallLiteralPools();

1467

1468

// Install switch tables

1469

InstallSwitchTables();

1470

1471

// Install fill array data

1472

InstallFillArrayData();

1473

1474

// Create the mapping table and native offset to reference map.

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1475

cu_->NewTimingSplit("PcMappingTable");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1476

CreateMappingTables();

1477

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1478

cu_->NewTimingSplit("GcMap");

buzbee