Blame - compiler/dex/quick/x86/assemble_x86.cc - platform_art

2014-03-31 10:14:40 -0700

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{ kX86Lea32RM, kRegMem, IS_TERTIARY_OP | IS_LOAD | REG_DEF0_USE1, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RM", "!0r,[!1r+!2d]" },

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

179

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

180

{ kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

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Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

182

{ kX86Cmov32RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, {0, 0, 0x0F, 0x40, 0, 0, 0, 0}, "Cmovcc32RR", "!2c !0r,!1r" },

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Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \

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{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \

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{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \

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{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \

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\

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{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \

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{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \

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{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

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{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \

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{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \

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{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }

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SHIFT_ENCODING_MAP(Rol, 0x0),

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SHIFT_ENCODING_MAP(Ror, 0x1),

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SHIFT_ENCODING_MAP(Rcl, 0x2),

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SHIFT_ENCODING_MAP(Rcr, 0x3),

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SHIFT_ENCODING_MAP(Sal, 0x4),

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SHIFT_ENCODING_MAP(Shr, 0x5),

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SHIFT_ENCODING_MAP(Sar, 0x7),

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#undef SHIFT_ENCODING_MAP

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{ kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0}, "Cmc", "" },

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

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{ kX86Shld32RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1}, "Shld32", "!0r,!1r,!2d" },

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{ kX86Shrd32RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1}, "Shrd32", "!0r,!1r,!2d" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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{ kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" },

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{ kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" },

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{ kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" },

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{ kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" },

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{ kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" },

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{ kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" },

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{ kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" },

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{ kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0}, "Test32RR", "!0r,!1r" },

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#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \

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reg, reg_kind, reg_flags, \

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mem, mem_kind, mem_flags, \

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arr, arr_kind, arr_flags, imm, \

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b_flags, hw_flags, w_flags, \

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b_format, hw_format, w_format) \

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{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, #b_format "!0r" }, \

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{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, #b_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, #b_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, #hw_format "!0r" }, \

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{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, #hw_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, #hw_format "[!0r+!1r<<!2d+!3d]" }, \

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{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, #w_format "!0r" }, \

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{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, #w_format "[!0r+!1d]" }, \

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{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, #w_format "[!0r+!1r<<!2d+!3d]" }

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UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

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Mark Mendell

2bf31e6

2014-01-23 12:13:40 -0800

[diff] [blame]

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UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

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UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

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UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

Brian Carlstrom

2013-07-12 13:46:57 -0700

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#undef UNARY_ENCODING_MAP

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Mark Mendell

2bf31e6

2014-01-23 12:13:40 -0800

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{ kx86Cdq32Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { 0, 0, 0x99, 0, 0, 0, 0, 0 }, "Cdq", "" },

Vladimir Marko

a6fd8ba

2013-12-13 10:53:49 +0000

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256

{ kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0 }, "Bswap32R", "!0r" },

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{ kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0 }, "Push32R", "!0r" },

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{ kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0 }, "Pop32R", "!0r" },

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

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259

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \

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{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

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{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

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{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

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EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),

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{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

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{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),

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{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

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{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),

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EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES),

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EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0),

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EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0),

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EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0),

Razvan A Lupusoru

d3266bc

2014-01-24 12:55:31 -0800

[diff] [blame]

295

EXT_0F_ENCODING_MAP(Punpckldq, 0x66, 0x62, REG_DEF0),

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

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{ kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" },

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{ kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" },

Mark Mendell

bff1ef0

2013-12-13 13:47:34 -0800

[diff] [blame]

299

{ kX86SqrtsdRR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0xF2, 0, 0x0F, 0x51, 0, 0, 0, 0 }, "SqrtsdRR", "!0r,!1r" },

Razvan A Lupusoru

614c2b4

2014-01-28 17:05:21 -0800

[diff] [blame]

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Serguei Katkov

e90501d

2014-03-12 15:56:54 +0700

[diff] [blame]

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{ kX86Fild32M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDB, 0x00, 0, 0, 0, 0 }, "Fild32M", "[!0r,!1d]" },

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{ kX86Fild64M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDF, 0x00, 0, 5, 0, 0 }, "Fild64M", "[!0r,!1d]" },

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{ kX86Fstp32M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 3, 0, 0 }, "FstpsM", "[!0r,!1d]" },

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{ kX86Fstp64M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0 }, "FstpdM", "[!0r,!1d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

305

Razvan A Lupusoru

2c498d1

2014-01-29 16:02:57 -0800

[diff] [blame]

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EXT_0F_ENCODING_MAP(Movups, 0x0, 0x10, REG_DEF0),

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{ kX86MovupsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovupsMR", "[!0r+!1d],!2r" },

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{ kX86MovupsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovupsAR", "[!0r+!1r<<!2d+!3d],!4r" },

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EXT_0F_ENCODING_MAP(Movaps, 0x0, 0x28, REG_DEF0),

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{ kX86MovapsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0 }, "MovapsMR", "[!0r+!1d],!2r" },

312

{ kX86MovapsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0 }, "MovapsAR", "[!0r+!1r<<!2d+!3d],!4r" },

313

314

{ kX86MovlpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0 }, "MovlpsRM", "!0r,[!1r+!2d]" },

315

{ kX86MovlpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0 }, "MovlpsRA", "!0r,[!1r+!2r<<!3d+!4d]" },

316

{ kX86MovlpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0 }, "MovlpsMR", "[!0r+!1d],!2r" },

317

{ kX86MovlpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0 }, "MovlpsAR", "[!0r+!1r<<!2d+!3d],!4r" },

318

319

{ kX86MovhpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0 }, "MovhpsRM", "!0r,[!1r+!2d]" },

320

{ kX86MovhpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0 }, "MovhpsRA", "!0r,[!1r+!2r<<!3d+!4d]" },

321

{ kX86MovhpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0 }, "MovhpsMR", "[!0r+!1d],!2r" },

322

{ kX86MovhpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0 }, "MovhpsAR", "[!0r+!1r<<!2d+!3d],!4r" },

323

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

324

EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),

325

{ kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" },

326

{ kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" },

327

{ kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },

328

329

{ kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

330

{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

331

{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

332

333

// TODO: load/store?

334

// Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.

335

{ kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },

336

337

EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES),

338

EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES),

339

340

{ kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" },

341

{ kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" },

342

{ kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

343

{ kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" },

344

{ kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Vladimir Marko

70b797d

2013-12-03 15:25:24 +0000

[diff] [blame]

345

{ kX86LockCmpxchg8bM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1d]" },

346

{ kX86LockCmpxchg8bA, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" },

Razvan A Lupusoru

99ad723

2014-02-25 17:41:08 -0800

[diff] [blame]

347

{ kX86XchgMR, kMemReg, IS_STORE | IS_LOAD | IS_TERTIARY_OP | REG_DEF2 | REG_USE02, { 0, 0, 0x87, 0, 0, 0, 0, 0 }, "Xchg", "[!0r+!1d],!2r" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

348

349

EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),

350

EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),

351

EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),

352

EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),

353

#undef EXT_0F_ENCODING_MAP

354

355

{ kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },

356

{ kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },

357

{ kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },

358

{ kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },

359

{ kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" },

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

360

{ kX86Jecxz8, kJmp, NO_OPERAND | IS_BRANCH | NEEDS_FIXUP | REG_USEC, { 0, 0, 0xE3, 0, 0, 0, 0, 0 }, "Jecxz", "!0t" },

Brian Carlstrom

60d7a65

2014-03-13 18:10:08 -0700

[diff] [blame]

361

{ kX86JmpT, kJmp, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpT", "fs:[!0d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

362

{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

363

{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

364

{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

365

{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

366

{ kX86CallI, kCall, IS_UNARY_OP | IS_BRANCH, { 0, 0, 0xE8, 0, 0, 0, 0, 4 }, "CallI", "!0d" },

Brian Carlstrom

b1eba21

2013-07-17 18:07:19 -0700

[diff] [blame]

367

{ kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

368

369

{ kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" },

370

{ kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },

371

{ kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" },

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

372

{ kX86RepneScasw, kPrefix2Nullary, NO_OPERAND | SETS_CCODES, { 0x66, 0xF2, 0xAF, 0, 0, 0, 0, 0 }, "RepNE ScasW", "" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

373

};

374

375

static size_t ComputeSize(const X86EncodingMap* entry, int base, int displacement, bool has_sib) {

376

size_t size = 0;

377

if (entry->skeleton.prefix1 > 0) {

378

++size;

379

if (entry->skeleton.prefix2 > 0) {

++size;

}

}

++size; // opcode

if (entry->skeleton.opcode == 0x0F) {

385

++size;

386

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

391

if (has_sib || RegStorage::RegNum(base) == rs_rX86_SP.GetRegNum()) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

392

// SP requires a SIB byte.

393

++size;

394

}

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

395

if (displacement != 0 || RegStorage::RegNum(base) == rs_rBP.GetRegNum()) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

396

// BP requires an explicit displacement, even when it's 0.

397

if (entry->opcode != kX86Lea32RA) {

398

DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name;

399

}

400

size += IS_SIMM8(displacement) ? 1 : 4;

401

}

402

size += entry->skeleton.immediate_bytes;

return size;

}

int X86Mir2Lir::GetInsnSize(LIR* lir) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

407

DCHECK(!IsPseudoLirOp(lir->opcode));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

408

const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode];

409

switch (entry->kind) {

410

case kData:

411

return 4; // 4 bytes of data

412

case kNop:

413

return lir->operands[0]; // length of nop is sole operand

414

case kNullary:

415

return 1; // 1 byte of opcode

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

416

case kPrefix2Nullary:

417

return 3; // 1 byte of opcode + 2 prefixes

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

418

case kRegOpcode: // lir operands - 0: reg

419

return ComputeSize(entry, 0, 0, false) - 1; // substract 1 for modrm

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

420

case kReg: // lir operands - 0: reg

421

return ComputeSize(entry, 0, 0, false);

422

case kMem: // lir operands - 0: base, 1: disp

423

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

424

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

425

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

426

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

427

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

428

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

429

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

430

case kThreadReg: // lir operands - 0: disp, 1: reg

431

return ComputeSize(entry, 0, lir->operands[0], false);

432

case kRegReg:

433

return ComputeSize(entry, 0, 0, false);

434

case kRegRegStore:

435

return ComputeSize(entry, 0, 0, false);

436

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

437

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

438

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

439

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

440

case kRegThread: // lir operands - 0: reg, 1: disp

441

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

442

case kRegImm: { // lir operands - 0: reg, 1: immediate

443

size_t size = ComputeSize(entry, 0, 0, false);

444

if (entry->skeleton.ax_opcode == 0) {

445

return size;

446

} else {

447

// AX opcodes don't require the modrm byte.

448

int reg = lir->operands[0];

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

449

return size - (RegStorage::RegNum(reg) == rs_rAX.GetRegNum() ? 1 : 0);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

450

}

451

}

452

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

453

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

454

case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

455

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

456

case kThreadImm: // lir operands - 0: disp, 1: imm

457

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

458

case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

459

case kRegRegImmRev:

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

460

return ComputeSize(entry, 0, 0, false);

461

case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

462

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

463

case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

464

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

465

case kMovRegImm: // lir operands - 0: reg, 1: immediate

466

return 1 + entry->skeleton.immediate_bytes;

467

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

468

// Shift by immediate one has a shorter opcode.

469

return ComputeSize(entry, 0, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

470

case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

471

// Shift by immediate one has a shorter opcode.

472

return ComputeSize(entry, lir->operands[0], lir->operands[1], false) -

473

(lir->operands[2] == 1 ? 1 : 0);

474

case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

475

// Shift by immediate one has a shorter opcode.

476

return ComputeSize(entry, lir->operands[0], lir->operands[3], true) -

477

(lir->operands[4] == 1 ? 1 : 0);

478

case kShiftRegCl:

479

return ComputeSize(entry, 0, 0, false);

480

case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

481

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

482

case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

483

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

484

case kRegCond: // lir operands - 0: reg, 1: cond

485

return ComputeSize(entry, 0, 0, false);

486

case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

487

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

488

case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

489

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

490

case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: cond

491

return ComputeSize(entry, 0, 0, false);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

492

case kJcc:

493

if (lir->opcode == kX86Jcc8) {

494

return 2; // opcode + rel8

495

} else {

496

DCHECK(lir->opcode == kX86Jcc32);

497

return 6; // 2 byte opcode + rel32

498

}

499

case kJmp:

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

500

if (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jecxz8) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

501

return 2; // opcode + rel8

502

} else if (lir->opcode == kX86Jmp32) {

503

return 5; // opcode + rel32

Brian Carlstrom

60d7a65

2014-03-13 18:10:08 -0700

[diff] [blame]

504

} else if (lir->opcode == kX86JmpT) {

505

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

506

} else {

507

DCHECK(lir->opcode == kX86JmpR);

508

return 2; // opcode + modrm

509

}

510

case kCall:

511

switch (lir->opcode) {

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

512

case kX86CallI: return 5; // opcode 0:disp

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

513

case kX86CallR: return 2; // opcode modrm

514

case kX86CallM: // lir operands - 0: base, 1: disp

515

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

516

case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

517

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

518

case kX86CallT: // lir operands - 0: disp

519

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

default:

break;

}

break;

case kPcRel:

if (entry->opcode == kX86PcRelLoadRA) {

526

// lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

527

return ComputeSize(entry, lir->operands[1], 0x12345678, true);

528

} else {

529

DCHECK(entry->opcode == kX86PcRelAdr);

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

530

return 5; // opcode with reg + 4 byte immediate

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

531

}

532

case kMacro:

533

DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));

534

return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +

535

ComputeSize(&X86Mir2Lir::EncodingMap[kX86Sub32RI], 0, 0, false) -

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

536

(RegStorage::RegNum(lir->operands[0]) == rs_rAX.GetRegNum() ? 1 : 0); // shorter ax encoding

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

return 0;

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

544

void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry) {

545

if (entry->skeleton.prefix1 != 0) {

546

code_buffer_.push_back(entry->skeleton.prefix1);

547

if (entry->skeleton.prefix2 != 0) {

548

code_buffer_.push_back(entry->skeleton.prefix2);

549

}

550

} else {

551

DCHECK_EQ(0, entry->skeleton.prefix2);

}

}

void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) {

556

code_buffer_.push_back(entry->skeleton.opcode);

557

if (entry->skeleton.opcode == 0x0F) {

558

code_buffer_.push_back(entry->skeleton.extra_opcode1);

559

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

560

code_buffer_.push_back(entry->skeleton.extra_opcode2);

561

} else {

562

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

563

}

564

} else {

565

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

566

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

}

}

void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry) {

EmitPrefix(entry);

EmitOpcode(entry);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

575

static uint8_t ModrmForDisp(int base, int disp) {

576

// BP requires an explicit disp, so do not omit it in the 0 case

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

577

if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

578

return 0;

579

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

586

void X86Mir2Lir::EmitDisp(uint8_t base, int disp) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

587

// BP requires an explicit disp, so do not omit it in the 0 case

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

588

if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

589

return;

590

} else if (IS_SIMM8(disp)) {

591

code_buffer_.push_back(disp & 0xFF);

592

} else {

593

code_buffer_.push_back(disp & 0xFF);

594

code_buffer_.push_back((disp >> 8) & 0xFF);

595

code_buffer_.push_back((disp >> 16) & 0xFF);

596

code_buffer_.push_back((disp >> 24) & 0xFF);

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

600

void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp) {

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

601

DCHECK_LT(RegStorage::RegNum(reg_or_opcode), 8);

602

DCHECK_LT(RegStorage::RegNum(base), 8);

603

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (RegStorage::RegNum(reg_or_opcode) << 3) |

604

RegStorage::RegNum(base);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

605

code_buffer_.push_back(modrm);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

606

if (RegStorage::RegNum(base) == rs_rX86_SP.GetRegNum()) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

607

// Special SIB for SP base

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

608

code_buffer_.push_back(0 << 6 | rs_rX86_SP.GetRegNum() << 3 | rs_rX86_SP.GetRegNum());

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

609

}

610

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

611

}

612

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

613

void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index,

614

int scale, int disp) {

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

615

DCHECK_LT(RegStorage::RegNum(reg_or_opcode), 8);

616

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | RegStorage::RegNum(reg_or_opcode) << 3 |

617

rs_rX86_SP.GetRegNum();

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

618

code_buffer_.push_back(modrm);

619

DCHECK_LT(scale, 4);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

620

DCHECK_LT(RegStorage::RegNum(index), 8);

621

DCHECK_LT(RegStorage::RegNum(base), 8);

622

uint8_t sib = (scale << 6) | (RegStorage::RegNum(index) << 3) | RegStorage::RegNum(base);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

623

code_buffer_.push_back(sib);

624

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

625

}

626

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

627

void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int imm) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

628

switch (entry->skeleton.immediate_bytes) {

629

case 1:

630

DCHECK(IS_SIMM8(imm));

631

code_buffer_.push_back(imm & 0xFF);

632

break;

633

case 2:

634

DCHECK(IS_SIMM16(imm));

635

code_buffer_.push_back(imm & 0xFF);

636

code_buffer_.push_back((imm >> 8) & 0xFF);

637

break;

638

case 4:

639

code_buffer_.push_back(imm & 0xFF);

640

code_buffer_.push_back((imm >> 8) & 0xFF);

641

code_buffer_.push_back((imm >> 16) & 0xFF);

642

code_buffer_.push_back((imm >> 24) & 0xFF);

643

break;

644

default:

645

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

646

<< ") for instruction: " << entry->name;

break;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

651

void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg) {

652

EmitPrefixAndOpcode(entry);

653

// There's no 3-byte instruction with +rd

654

DCHECK(entry->skeleton.opcode != 0x0F ||

655

(entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A));

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

656

DCHECK(!RegStorage::IsFloat(reg));

657

DCHECK_LT(RegStorage::RegNum(reg), 8);

658

code_buffer_.back() += RegStorage::RegNum(reg);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

659

DCHECK_EQ(0, entry->skeleton.ax_opcode);

660

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

661

}

662

663

void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) {

664

EmitPrefixAndOpcode(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

665

if (RegStorage::RegNum(reg) >= 4) {

666

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " "

667

<< static_cast<int>(RegStorage::RegNum(reg))

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

668

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

669

}

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

670

DCHECK_LT(RegStorage::RegNum(reg), 8);

671

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | RegStorage::RegNum(reg);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

672

code_buffer_.push_back(modrm);

673

DCHECK_EQ(0, entry->skeleton.ax_opcode);

674

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

675

}

676

677

void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) {

678

EmitPrefix(entry);

679

code_buffer_.push_back(entry->skeleton.opcode);

680

DCHECK_NE(0x0F, entry->skeleton.opcode);

681

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

682

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

683

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

684

DCHECK_EQ(0, entry->skeleton.ax_opcode);

685

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

686

}

687

688

void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index,

689

int scale, int disp) {

690

EmitPrefixAndOpcode(entry);

691

EmitModrmSibDisp(entry->skeleton.modrm_opcode, base, index, scale, disp);

692

DCHECK_EQ(0, entry->skeleton.ax_opcode);

693

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

694

}

695

696

void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry,

697

uint8_t base, int disp, uint8_t reg) {

698

EmitPrefixAndOpcode(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

699

if (RegStorage::RegNum(reg) >= 4) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

700

DCHECK(strchr(entry->name, '8') == NULL ||

701

entry->opcode == kX86Movzx8RM || entry->opcode == kX86Movsx8RM)

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

702

<< entry->name << " " << static_cast<int>(RegStorage::RegNum(reg))

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

703

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

704

}

705

EmitModrmDisp(reg, base, disp);

706

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

707

DCHECK_EQ(0, entry->skeleton.ax_opcode);

708

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

709

}

710

711

void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry,

712

uint8_t reg, uint8_t base, int disp) {

713

// Opcode will flip operands.

714

EmitMemReg(entry, base, disp, reg);

715

}

716

717

void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index,

718

int scale, int disp) {

719

EmitPrefixAndOpcode(entry);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

720

EmitModrmSibDisp(reg, base, index, scale, disp);

721

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

722

DCHECK_EQ(0, entry->skeleton.ax_opcode);

723

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

724

}

725

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

726

void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale,

727

int disp, uint8_t reg) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

728

// Opcode will flip operands.

729

EmitRegArray(entry, reg, base, index, scale, disp);

730

}

731

732

void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) {

733

DCHECK_NE(entry->skeleton.prefix1, 0);

734

EmitPrefixAndOpcode(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

735

if (RegStorage::RegNum(reg) >= 4) {

736

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " "

737

<< static_cast<int>(RegStorage::RegNum(reg))

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

738

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

739

}

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

740

DCHECK_LT(RegStorage::RegNum(reg), 8);

741

uint8_t modrm = (0 << 6) | (RegStorage::RegNum(reg) << 3) | rs_rBP.GetRegNum();

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

742

code_buffer_.push_back(modrm);

743

code_buffer_.push_back(disp & 0xFF);

744

code_buffer_.push_back((disp >> 8) & 0xFF);

745

code_buffer_.push_back((disp >> 16) & 0xFF);

746

code_buffer_.push_back((disp >> 24) & 0xFF);

747

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

748

DCHECK_EQ(0, entry->skeleton.ax_opcode);

749

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

750

}

751

752

void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) {

753

EmitPrefixAndOpcode(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

754

DCHECK_LT(RegStorage::RegNum(reg1), 8);

755

DCHECK_LT(RegStorage::RegNum(reg2), 8);

756

uint8_t modrm = (3 << 6) | (RegStorage::RegNum(reg1) << 3) | RegStorage::RegNum(reg2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

757

code_buffer_.push_back(modrm);

758

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

759

DCHECK_EQ(0, entry->skeleton.ax_opcode);

760

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

761

}

762

763

void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry,

764

uint8_t reg1, uint8_t reg2, int32_t imm) {

765

EmitPrefixAndOpcode(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

766

DCHECK_LT(RegStorage::RegNum(reg1), 8);

767

DCHECK_LT(RegStorage::RegNum(reg2), 8);

768

uint8_t modrm = (3 << 6) | (RegStorage::RegNum(reg1) << 3) | RegStorage::RegNum(reg2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

769

code_buffer_.push_back(modrm);

770

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

771

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

775

void X86Mir2Lir::EmitRegRegImmRev(const X86EncodingMap* entry,

776

uint8_t reg1, uint8_t reg2, int32_t imm) {

777

EmitRegRegImm(entry, reg2, reg1, imm);

778

}

779

780

void X86Mir2Lir::EmitRegMemImm(const X86EncodingMap* entry,

781

uint8_t reg, uint8_t base, int disp, int32_t imm) {

782

EmitPrefixAndOpcode(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

783

DCHECK(!RegStorage::IsFloat(reg));

784

DCHECK_LT(RegStorage::RegNum(reg), 8);

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

785

EmitModrmDisp(reg, base, disp);

786

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

787

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

791

void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

792

if (entry->skeleton.prefix1 != 0) {

793

code_buffer_.push_back(entry->skeleton.prefix1);

794

if (entry->skeleton.prefix2 != 0) {

795

code_buffer_.push_back(entry->skeleton.prefix2);

796

}

797

} else {

798

DCHECK_EQ(0, entry->skeleton.prefix2);

799

}

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

800

if (RegStorage::RegNum(reg) == rs_rAX.GetRegNum() && entry->skeleton.ax_opcode != 0) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

801

code_buffer_.push_back(entry->skeleton.ax_opcode);

802

} else {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

803

EmitOpcode(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

804

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | RegStorage::RegNum(reg);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

805

code_buffer_.push_back(modrm);

806

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

807

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

808

}

809

Mark Mendell

343adb5

2013-12-18 06:02:17 -0800

[diff] [blame]

810

void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm) {

811

EmitPrefixAndOpcode(entry);

812

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

813

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

817

void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

818

EmitPrefixAndOpcode(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

819

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rs_rBP.GetRegNum();

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

820

code_buffer_.push_back(modrm);

821

code_buffer_.push_back(disp & 0xFF);

822

code_buffer_.push_back((disp >> 8) & 0xFF);

823

code_buffer_.push_back((disp >> 16) & 0xFF);

824

code_buffer_.push_back((disp >> 24) & 0xFF);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

825

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

826

DCHECK_EQ(entry->skeleton.ax_opcode, 0);

827

}

828

829

void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

830

DCHECK_LT(RegStorage::RegNum(reg), 8);

831

code_buffer_.push_back(0xB8 + RegStorage::RegNum(reg));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

832

code_buffer_.push_back(imm & 0xFF);

833

code_buffer_.push_back((imm >> 8) & 0xFF);

834

code_buffer_.push_back((imm >> 16) & 0xFF);

835

code_buffer_.push_back((imm >> 24) & 0xFF);

836

}

837

838

void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

839

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

840

if (imm != 1) {

841

code_buffer_.push_back(entry->skeleton.opcode);

842

} else {

843

// Shorter encoding for 1 bit shift

844

code_buffer_.push_back(entry->skeleton.ax_opcode);

845

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

846

DCHECK_NE(0x0F, entry->skeleton.opcode);

847

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

848

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

849

if (RegStorage::RegNum(reg) >= 4) {

850

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " "

851

<< static_cast<int>(RegStorage::RegNum(reg))

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

852

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

853

}

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

854

DCHECK_LT(RegStorage::RegNum(reg), 8);

855

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | RegStorage::RegNum(reg);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

856

code_buffer_.push_back(modrm);

857

if (imm != 1) {

858

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

859

DCHECK(IS_SIMM8(imm));

860

code_buffer_.push_back(imm & 0xFF);

}

}

void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl) {

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

865

DCHECK_EQ(cl, static_cast<uint8_t>(rs_rCX.GetReg()));

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

866

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

867

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

868

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

869

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

870

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

871

DCHECK_LT(RegStorage::RegNum(reg), 8);

872

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | RegStorage::RegNum(reg);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

873

code_buffer_.push_back(modrm);

874

DCHECK_EQ(0, entry->skeleton.ax_opcode);

875

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

876

}

877

Mark Mendell

2014-01-28 12:59:49 -0800

[diff] [blame]

878

void X86Mir2Lir::EmitShiftMemCl(const X86EncodingMap* entry, uint8_t base,

879

int displacement, uint8_t cl) {

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

880

DCHECK_EQ(cl, static_cast<uint8_t>(rs_rCX.GetReg()));

Mark Mendell

2014-01-28 12:59:49 -0800

[diff] [blame]

881

EmitPrefix(entry);

882

code_buffer_.push_back(entry->skeleton.opcode);

883

DCHECK_NE(0x0F, entry->skeleton.opcode);

884

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

885

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

886

DCHECK_LT(RegStorage::RegNum(base), 8);

Mark Mendell

2014-01-28 12:59:49 -0800

[diff] [blame]

887

EmitModrmDisp(entry->skeleton.modrm_opcode, base, displacement);

888

DCHECK_EQ(0, entry->skeleton.ax_opcode);

889

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

890

}

891

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

892

void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) {

893

if (entry->skeleton.prefix1 != 0) {

894

code_buffer_.push_back(entry->skeleton.prefix1);

895

if (entry->skeleton.prefix2 != 0) {

896

code_buffer_.push_back(entry->skeleton.prefix2);

897

}

898

} else {

899

DCHECK_EQ(0, entry->skeleton.prefix2);

900

}

901

DCHECK_EQ(0, entry->skeleton.ax_opcode);

902

DCHECK_EQ(0x0F, entry->skeleton.opcode);

903

code_buffer_.push_back(0x0F);

904

DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);

905

code_buffer_.push_back(0x90 | condition);

906

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

907

DCHECK_LT(RegStorage::RegNum(reg), 8);

908

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | RegStorage::RegNum(reg);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

909

code_buffer_.push_back(modrm);

910

DCHECK_EQ(entry->skeleton.immediate_bytes, 0);

911

}

912

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

913

void X86Mir2Lir::EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2,

914

uint8_t condition) {

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

915

// Generate prefix and opcode without the condition

916

EmitPrefixAndOpcode(entry);

917

918

// Now add the condition. The last byte of opcode is the one that receives it.

919

DCHECK_LE(condition, 0xF);

920

code_buffer_.back() += condition;

921

922

// Not expecting to have to encode immediate or do anything special for ModR/M since there are two registers.

923

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

924

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

925

926

// Check that registers requested for encoding are sane.

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

927

DCHECK_LT(RegStorage::RegNum(reg1), 8);

928

DCHECK_LT(RegStorage::RegNum(reg2), 8);

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

929

930

// For register to register encoding, the mod is 3.

931

const uint8_t mod = (3 << 6);

932

933

// Encode the ModR/M byte now.

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

934

const uint8_t modrm = mod | (RegStorage::RegNum(reg1) << 3) | RegStorage::RegNum(reg2);

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

935

code_buffer_.push_back(modrm);

936

}

937

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

938

void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int rel) {

939

if (entry->opcode == kX86Jmp8) {

940

DCHECK(IS_SIMM8(rel));

941

code_buffer_.push_back(0xEB);

942

code_buffer_.push_back(rel & 0xFF);

943

} else if (entry->opcode == kX86Jmp32) {

944

code_buffer_.push_back(0xE9);

945

code_buffer_.push_back(rel & 0xFF);

946

code_buffer_.push_back((rel >> 8) & 0xFF);

947

code_buffer_.push_back((rel >> 16) & 0xFF);

948

code_buffer_.push_back((rel >> 24) & 0xFF);

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

949

} else if (entry->opcode == kX86Jecxz8) {

950

DCHECK(IS_SIMM8(rel));

951

code_buffer_.push_back(0xE3);

952

code_buffer_.push_back(rel & 0xFF);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

953

} else {

954

DCHECK(entry->opcode == kX86JmpR);

955

code_buffer_.push_back(entry->skeleton.opcode);

956

uint8_t reg = static_cast<uint8_t>(rel);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

957

DCHECK_LT(RegStorage::RegNum(reg), 8);

958

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | RegStorage::RegNum(reg);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

959

code_buffer_.push_back(modrm);

}

}

void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc) {

964

DCHECK_LT(cc, 16);

965

if (entry->opcode == kX86Jcc8) {

966

DCHECK(IS_SIMM8(rel));

967

code_buffer_.push_back(0x70 | cc);

968

code_buffer_.push_back(rel & 0xFF);

969

} else {

970

DCHECK(entry->opcode == kX86Jcc32);

971

code_buffer_.push_back(0x0F);

972

code_buffer_.push_back(0x80 | cc);

973

code_buffer_.push_back(rel & 0xFF);

974

code_buffer_.push_back((rel >> 8) & 0xFF);

975

code_buffer_.push_back((rel >> 16) & 0xFF);

976

code_buffer_.push_back((rel >> 24) & 0xFF);

}

}

void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

981

EmitPrefixAndOpcode(entry);

982

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

983

DCHECK_EQ(0, entry->skeleton.ax_opcode);

984

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

985

}

986

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

987

void X86Mir2Lir::EmitCallImmediate(const X86EncodingMap* entry, int disp) {

988

EmitPrefixAndOpcode(entry);

989

DCHECK_EQ(4, entry->skeleton.immediate_bytes);

990

code_buffer_.push_back(disp & 0xFF);

991

code_buffer_.push_back((disp >> 8) & 0xFF);

992

code_buffer_.push_back((disp >> 16) & 0xFF);

993

code_buffer_.push_back((disp >> 24) & 0xFF);

994

DCHECK_EQ(0, entry->skeleton.ax_opcode);

995

}

996

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

997

void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int disp) {

998

DCHECK_NE(entry->skeleton.prefix1, 0);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

999

EmitPrefixAndOpcode(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

1000

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rs_rBP.GetRegNum();

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1001

code_buffer_.push_back(modrm);

1002

code_buffer_.push_back(disp & 0xFF);

1003

code_buffer_.push_back((disp >> 8) & 0xFF);

1004

code_buffer_.push_back((disp >> 16) & 0xFF);

1005

code_buffer_.push_back((disp >> 24) & 0xFF);

1006

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1007

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1008

}

1009

1010

void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, uint8_t reg,

1011

int base_or_table, uint8_t index, int scale, int table_or_disp) {

1012

int disp;

1013

if (entry->opcode == kX86PcRelLoadRA) {

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1014

Mir2Lir::EmbeddedData *tab_rec =

1015

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1016

disp = tab_rec->offset;

1017

} else {

1018

DCHECK(entry->opcode == kX86PcRelAdr);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1019

Mir2Lir::EmbeddedData *tab_rec =

1020

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(base_or_table));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1021

disp = tab_rec->offset;

1022

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1023

EmitPrefix(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

1024

DCHECK_LT(RegStorage::RegNum(reg), 8);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1025

if (entry->opcode == kX86PcRelLoadRA) {

1026

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1027

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1028

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1029

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

1030

uint8_t modrm = (2 << 6) | (RegStorage::RegNum(reg) << 3) | rs_rX86_SP.GetRegNum();

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1031

code_buffer_.push_back(modrm);

1032

DCHECK_LT(scale, 4);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

1033

DCHECK_LT(RegStorage::RegNum(index), 8);

1034

DCHECK_LT(RegStorage::RegNum(base_or_table), 8);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1035

uint8_t base = static_cast<uint8_t>(base_or_table);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

1036

uint8_t sib = (scale << 6) | (RegStorage::RegNum(index) << 3) | RegStorage::RegNum(base);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1037

code_buffer_.push_back(sib);

1038

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1039

} else {

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

1040

code_buffer_.push_back(entry->skeleton.opcode + RegStorage::RegNum(reg));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1041

}

1042

code_buffer_.push_back(disp & 0xFF);

1043

code_buffer_.push_back((disp >> 8) & 0xFF);

1044

code_buffer_.push_back((disp >> 16) & 0xFF);

1045

code_buffer_.push_back((disp >> 24) & 0xFF);

1046

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1047

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1048

}

1049

1050

void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset) {

1051

DCHECK(entry->opcode == kX86StartOfMethod) << entry->name;

1052

code_buffer_.push_back(0xE8); // call +0

1053

code_buffer_.push_back(0);

1054

code_buffer_.push_back(0);

1055

code_buffer_.push_back(0);

1056

code_buffer_.push_back(0);

1057

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

1058

DCHECK_LT(RegStorage::RegNum(reg), 8);

1059

code_buffer_.push_back(0x58 + RegStorage::RegNum(reg)); // pop reg

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1060

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

1061

EmitRegImm(&X86Mir2Lir::EncodingMap[kX86Sub32RI], RegStorage::RegNum(reg),

1062

offset + 5 /* size of call +0 */);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1063

}

1064

1065

void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) {

1066

UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " "

1067

<< BuildInsnString(entry->fmt, lir, 0);

1068

for (int i = 0; i < GetInsnSize(lir); ++i) {

1069

code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3

}

}

/*

* Assemble the LIR into binary instruction format. Note that we may

1075

* discover that pc-relative displacements may not fit the selected

1076

* instruction. In those cases we will try to substitute a new code

1077

* sequence or request that the trace be shortened and retried.

1078

*/

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1079

AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1080

LIR *lir;

1081

AssemblerStatus res = kSuccess; // Assume success

1082

1083

const bool kVerbosePcFixup = false;

1084

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1085

if (IsPseudoLirOp(lir->opcode)) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

continue;

}

if (lir->flags.is_nop) {

continue;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1093

if (lir->flags.fixup != kFixupNone) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1094

switch (lir->opcode) {

1095

case kX86Jcc8: {

1096

LIR *target_lir = lir->target;

1097

DCHECK(target_lir != NULL);

1098

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1099

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1100

if (IS_SIMM8(lir->operands[0])) {

1101

pc = lir->offset + 2 /* opcode + rel8 */;

1102

} else {

1103

pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1104

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1105

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1106

delta = target - pc;

1107

if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1108

if (kVerbosePcFixup) {

1109

LOG(INFO) << "Retry for JCC growth at " << lir->offset

1110

<< " delta: " << delta << " old delta: " << lir->operands[0];

1111

}

1112

lir->opcode = kX86Jcc32;

1113

SetupResourceMasks(lir);

1114

res = kRetryAll;

1115

}

1116

if (kVerbosePcFixup) {

1117

LOG(INFO) << "Source:";

1118

DumpLIRInsn(lir, 0);

1119

LOG(INFO) << "Target:";

1120

DumpLIRInsn(target_lir, 0);

1121

LOG(INFO) << "Delta " << delta;

1122

}

1123

lir->operands[0] = delta;

break;

}

case kX86Jcc32: {

LIR *target_lir = lir->target;

1128

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1129

CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1130

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1131

int delta = target - pc;

1132

if (kVerbosePcFixup) {

1133

LOG(INFO) << "Source:";

1134

DumpLIRInsn(lir, 0);

1135

LOG(INFO) << "Target:";

1136

DumpLIRInsn(target_lir, 0);

1137

LOG(INFO) << "Delta " << delta;

1138

}

1139

lir->operands[0] = delta;

1140

break;

1141

}

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

1142

case kX86Jecxz8: {

1143

LIR *target_lir = lir->target;

1144

DCHECK(target_lir != NULL);

1145

CodeOffset pc;

1146

pc = lir->offset + 2; // opcode + rel8

1147

CodeOffset target = target_lir->offset;

1148

int delta = target - pc;

1149

lir->operands[0] = delta;

1150

DCHECK(IS_SIMM8(delta));

1151

break;

1152

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1153

case kX86Jmp8: {

1154

LIR *target_lir = lir->target;

1155

DCHECK(target_lir != NULL);

1156

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1157

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1158

if (IS_SIMM8(lir->operands[0])) {

1159

pc = lir->offset + 2 /* opcode + rel8 */;

1160

} else {

1161

pc = lir->offset + 5 /* opcode + rel32 */;

1162

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1163

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1164

delta = target - pc;

1165

if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) {

1166

// Useless branch

buzbee

252254b

2013-09-08 16:20:53 -0700

[diff] [blame]

1167

NopLIR(lir);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1168

if (kVerbosePcFixup) {

1169

LOG(INFO) << "Retry for useless branch at " << lir->offset;

1170

}

1171

res = kRetryAll;

1172

} else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1173

if (kVerbosePcFixup) {

1174

LOG(INFO) << "Retry for JMP growth at " << lir->offset;

1175

}

1176

lir->opcode = kX86Jmp32;

1177

SetupResourceMasks(lir);

1178

res = kRetryAll;

1179

}

1180

lir->operands[0] = delta;

break;

}

case kX86Jmp32: {

LIR *target_lir = lir->target;

1185

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1186

CodeOffset pc = lir->offset + 5 /* opcode + rel32 */;

1187

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1188

int delta = target - pc;

1189

lir->operands[0] = delta;

1190

break;

1191

}

1192

default:

Mark Mendell

67c39c4

2014-01-31 17:28:00 -0800

[diff] [blame]

1193

if (lir->flags.fixup == kFixupLoad) {

1194

LIR *target_lir = lir->target;

1195

DCHECK(target_lir != NULL);

1196

CodeOffset target = target_lir->offset;

1197

lir->operands[2] = target;

1198

int newSize = GetInsnSize(lir);

1199

if (newSize != lir->flags.size) {

1200

lir->flags.size = newSize;

1201

res = kRetryAll;

1202

}

1203

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

break;

}

}

/*

* If one of the pc-relative instructions expanded we'll have

1210

* to make another pass. Don't bother to fully assemble the

1211

* instruction.

1212

*/

1213

if (res != kSuccess) {

1214

continue;

1215

}

1216

CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size());

1217

const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode];

1218

size_t starting_cbuf_size = code_buffer_.size();

1219

switch (entry->kind) {

1220

case kData: // 4 bytes of data

1221

code_buffer_.push_back(lir->operands[0]);

1222

break;

1223

case kNullary: // 1 byte of opcode

1224

DCHECK_EQ(0, entry->skeleton.prefix1);

1225

DCHECK_EQ(0, entry->skeleton.prefix2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1226

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1227

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1228

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1229

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1230

break;

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

1231

case kPrefix2Nullary: // 1 byte of opcode + 2 prefixes.

1232

DCHECK_NE(0, entry->skeleton.prefix1);

1233

DCHECK_NE(0, entry->skeleton.prefix2);

1234

EmitPrefixAndOpcode(entry);

1235

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1236

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1237

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1238

break;

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

1239

case kRegOpcode: // lir operands - 0: reg

1240

EmitOpRegOpcode(entry, lir->operands[0]);

1241

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1242

case kReg: // lir operands - 0: reg

1243

EmitOpReg(entry, lir->operands[0]);

1244

break;

1245

case kMem: // lir operands - 0: base, 1: disp

1246

EmitOpMem(entry, lir->operands[0], lir->operands[1]);

1247

break;

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1248

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

1249

EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]);

1250

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1251

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

1252

EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1253

break;

Mark Mendell

343adb5

2013-12-18 06:02:17 -0800

[diff] [blame]

1254

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

1255

EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1256

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1257

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

1258

EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1259

lir->operands[3], lir->operands[4]);

1260

break;

1261

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

1262

EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1263

break;

1264

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

1265

EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1266

lir->operands[3], lir->operands[4]);

1267

break;

1268

case kRegThread: // lir operands - 0: reg, 1: disp

1269

EmitRegThread(entry, lir->operands[0], lir->operands[1]);

1270

break;

1271

case kRegReg: // lir operands - 0: reg1, 1: reg2

1272

EmitRegReg(entry, lir->operands[0], lir->operands[1]);

1273

break;

1274

case kRegRegStore: // lir operands - 0: reg2, 1: reg1

1275

EmitRegReg(entry, lir->operands[1], lir->operands[0]);

1276

break;

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

1277

case kRegRegImmRev:

1278

EmitRegRegImmRev(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1279

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1280

case kRegRegImm:

1281

EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1282

break;

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

1283

case kRegMemImm:

1284

EmitRegMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1285

lir->operands[3]);

1286

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1287

case kRegImm: // lir operands - 0: reg, 1: immediate

1288

EmitRegImm(entry, lir->operands[0], lir->operands[1]);

1289

break;

1290

case kThreadImm: // lir operands - 0: disp, 1: immediate

1291

EmitThreadImm(entry, lir->operands[0], lir->operands[1]);

1292

break;

1293

case kMovRegImm: // lir operands - 0: reg, 1: immediate

1294

EmitMovRegImm(entry, lir->operands[0], lir->operands[1]);

1295

break;

1296

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

1297

EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]);

1298

break;

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

1299

case kShiftRegCl: // lir operands - 0: reg, 1: cl

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1300

EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]);

1301

break;

Mark Mendell

2014-01-28 12:59:49 -0800

[diff] [blame]

1302

case kShiftMemCl: // lir operands - 0: base, 1:displacement, 2: cl

1303

EmitShiftMemCl(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1304

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1305

case kRegCond: // lir operands - 0: reg, 1: condition

1306

EmitRegCond(entry, lir->operands[0], lir->operands[1]);

1307

break;

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

1308

case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: condition

1309

EmitRegRegCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1310

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1311

case kJmp: // lir operands - 0: rel

Brian Carlstrom

60d7a65

2014-03-13 18:10:08 -0700

[diff] [blame]

1312

if (entry->opcode == kX86JmpT) {

1313

// This works since the instruction format for jmp and call is basically the same and

1314

// EmitCallThread loads opcode info.

1315

EmitCallThread(entry, lir->operands[0]);

1316

} else {

1317

EmitJmp(entry, lir->operands[0]);

1318

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1319

break;

1320

case kJcc: // lir operands - 0: rel, 1: CC, target assigned

1321

EmitJcc(entry, lir->operands[0], lir->operands[1]);

1322

break;

1323

case kCall:

1324

switch (entry->opcode) {

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

1325

case kX86CallI: // lir operands - 0: disp

1326

EmitCallImmediate(entry, lir->operands[0]);

1327

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1328

case kX86CallM: // lir operands - 0: base, 1: disp

1329

EmitCallMem(entry, lir->operands[0], lir->operands[1]);

1330

break;

1331

case kX86CallT: // lir operands - 0: disp

1332

EmitCallThread(entry, lir->operands[0]);

1333

break;

1334

default:

1335

EmitUnimplemented(entry, lir);

break;

}

break;

case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

1340

EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1341

lir->operands[3], lir->operands[4]);

1342

break;

1343

case kMacro:

1344

EmitMacro(entry, lir->operands[0], lir->offset);

1345

break;

1346

default:

1347

EmitUnimplemented(entry, lir);

1348

break;

1349

}

1350

CHECK_EQ(static_cast<size_t>(GetInsnSize(lir)),

1351

code_buffer_.size() - starting_cbuf_size)

1352

<< "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name;

}

return res;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1357

// LIR offset assignment.

1358

// TODO: consolidate w/ Arm assembly mechanism.

1359

int X86Mir2Lir::AssignInsnOffsets() {

LIR* lir;

int offset = 0;

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

1364

lir->offset = offset;

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1365

if (LIKELY(!IsPseudoLirOp(lir->opcode))) {

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1366

if (!lir->flags.is_nop) {

1367

offset += lir->flags.size;

1368

}

1369

} else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) {

1370

if (offset & 0x2) {

1371

offset += 2;

1372

lir->operands[0] = 1;

1373

} else {

1374

lir->operands[0] = 0;

1375

}

1376

}

1377

/* Pseudo opcodes don't consume space */

}

return offset;

}

/*

* Walk the compilation unit and assign offsets to instructions

1384

* and literals and compute the total size of the compiled unit.

1385

* TODO: consolidate w/ Arm assembly mechanism.

1386

*/

1387

void X86Mir2Lir::AssignOffsets() {

1388

int offset = AssignInsnOffsets();

1389

1390

/* Const values have to be word aligned */

Andreas Gampe

6601882

2014-05-05 20:47:19 -0700

[diff] [blame^]

1391

offset = RoundUp(offset, 4);

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1392

1393

/* Set up offsets for literals */

1394

data_offset_ = offset;

1395

1396

offset = AssignLiteralOffset(offset);

1397

1398

offset = AssignSwitchTablesOffset(offset);

1399

1400

offset = AssignFillArrayDataOffset(offset);

1401

1402

total_size_ = offset;

}

/*

* Go over each instruction in the list and calculate the offset from the top

1407

* before sending them off to the assembler. If out-of-range branch distance is

1408

* seen rearrange the instructions a bit to correct it.

1409

* TODO: consolidate w/ Arm assembly mechanism.

1410

*/

1411

void X86Mir2Lir::AssembleLIR() {

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1412

cu_->NewTimingSplit("Assemble");

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

1413

1414

// We will remove the method address if we never ended up using it

1415

if (store_method_addr_ && !store_method_addr_used_) {

1416

setup_method_address_[0]->flags.is_nop = true;

1417

setup_method_address_[1]->flags.is_nop = true;

1418

}

1419

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1420

AssignOffsets();

1421

int assembler_retries = 0;

1422

/*

1423

* Assemble here. Note that we generate code with optimistic assumptions

1424

* and if found now to work, we'll have to redo the sequence and retry.

*/

while (true) {

AssemblerStatus res = AssembleInstructions(0);

1429

if (res == kSuccess) {

break;

} else {

assembler_retries++;

if (assembler_retries > MAX_ASSEMBLER_RETRIES) {

1434

CodegenDump();

1435

LOG(FATAL) << "Assembler error - too many retries";

1436

}

1437

// Redo offsets and try again

1438

AssignOffsets();

1439

code_buffer_.clear();

}

}

// Install literals

InstallLiteralPools();

1445

1446

// Install switch tables

1447

InstallSwitchTables();

1448

1449

// Install fill array data

1450

InstallFillArrayData();

1451

1452

// Create the mapping table and native offset to reference map.

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1453

cu_->NewTimingSplit("PcMappingTable");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1454

CreateMappingTables();

1455

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1456

cu_->NewTimingSplit("GcMap");

buzbee