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Saurabh Shah66c941b2016-07-06 17:34:05 -07001/*
Rohit Kulkarni21649ef2018-02-08 14:39:40 -08002* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
Saurabh Shah66c941b2016-07-06 17:34:05 -07003*
4* Redistribution and use in source and binary forms, with or without
5* modification, are permitted provided that the following conditions are
6* met:
7* * Redistributions of source code must retain the above copyright
8* notice, this list of conditions and the following disclaimer.
9* * Redistributions in binary form must reproduce the above
10* copyright notice, this list of conditions and the following
11* disclaimer in the documentation and/or other materials provided
12* with the distribution.
13* * Neither the name of The Linux Foundation nor the names of its
14* contributors may be used to endorse or promote products derived
15* from this software without specific prior written permission.
16*
17* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
18* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
20* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
21* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
24* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
25* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
26* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
27* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28*/
29
30#ifndef __DRM_INTERFACE_H__
31#define __DRM_INTERFACE_H__
32
33#include <map>
34#include <string>
35#include <utility>
36#include <vector>
37
38#include "xf86drm.h"
39#include "xf86drmMode.h"
Sushil Chauhan80e58432017-07-06 11:39:17 -070040#include <drm/msm_drm.h>
Saurabh Shah66c941b2016-07-06 17:34:05 -070041
42namespace sde_drm {
Ramkumar Radhakrishnan9ed1fd82017-03-09 18:46:41 -080043
44typedef std::map<std::pair<uint32_t, uint64_t>, float> CompRatioMap;
45
Saurabh Shah66c941b2016-07-06 17:34:05 -070046/*
47 * Drm Atomic Operation Codes
48 */
49enum struct DRMOps {
50 /*
51 * Op: Sets plane source crop
52 * Arg: uint32_t - Plane ID
53 * DRMRect - Source Rectangle
54 */
55 PLANE_SET_SRC_RECT,
56 /*
57 * Op: Sets plane destination rect
58 * Arg: uint32_t - Plane ID
59 * DRMRect - Dst Rectangle
60 */
61 PLANE_SET_DST_RECT,
62 /*
Namit Solanki6d0d8062017-11-30 17:29:48 +053063 * Op: Sets plane exclusion rect
64 * Arg: uint32_t - Plane ID
65 * drm_clip_rect - Exclusion Rectangle
66 */
67 PLANE_SET_EXCL_RECT,
68 /*
Saurabh Shah66c941b2016-07-06 17:34:05 -070069 * Op: Sets plane zorder
70 * Arg: uint32_t - Plane ID
71 * uint32_t - zorder
72 */
73 PLANE_SET_ZORDER,
74 /*
75 * Op: Sets plane rotation flags
76 * Arg: uint32_t - Plane ID
77 * uint32_t - bit mask of rotation flags (See drm_mode.h for enums)
78 */
79 PLANE_SET_ROTATION,
80 /*
81 * Op: Sets plane alpha
82 * Arg: uint32_t - Plane ID
83 * uint32_t - alpha value
84 */
85 PLANE_SET_ALPHA,
86 /*
87 * Op: Sets the blend type
88 * Arg: uint32_t - Plane ID
89 * uint32_t - blend type (see DRMBlendType)
90 */
91 PLANE_SET_BLEND_TYPE,
92 /*
93 * Op: Sets horizontal decimation
94 * Arg: uint32_t - Plane ID
95 * uint32_t - decimation factor
96 */
97 PLANE_SET_H_DECIMATION,
98 /*
99 * Op: Sets vertical decimation
100 * Arg: uint32_t - Plane ID
101 * uint32_t - decimation factor
102 */
103 PLANE_SET_V_DECIMATION,
104 /*
Prabhanjan Kandula585aa652017-01-26 18:39:11 -0800105 * Op: Sets source config flags
106 * Arg: uint32_t - Plane ID
107 * uint32_t - flags to enable or disable a specific op. E.g. deinterlacing
108 */
109 PLANE_SET_SRC_CONFIG,
110 /*
Saurabh Shah66c941b2016-07-06 17:34:05 -0700111 * Op: Sets frame buffer ID for plane. Set together with CRTC.
112 * Arg: uint32_t - Plane ID
113 * uint32_t - Framebuffer ID
114 */
115 PLANE_SET_FB_ID,
116 /*
117 * Op: Sets the crtc for this plane. Set together with FB_ID.
118 * Arg: uint32_t - Plane ID
119 * uint32_t - CRTC ID
120 */
121 PLANE_SET_CRTC,
122 /*
123 * Op: Sets acquire fence for this plane's buffer. Set together with FB_ID, CRTC.
124 * Arg: uint32_t - Plane ID
125 * uint32_t - Input fence
126 */
127 PLANE_SET_INPUT_FENCE,
128 /*
Saurabh Shah0ffee302016-11-22 10:42:11 -0800129 * Op: Sets scaler config on this plane.
130 * Arg: uint32_t - Plane ID
131 * uint64_t - Address of the scaler config object (version based)
132 */
133 PLANE_SET_SCALER_CONFIG,
134 /*
Rohit Kulkarni8622e362017-01-30 18:14:10 -0800135 * Op: Sets plane rotation destination rect
136 * Arg: uint32_t - Plane ID
137 * DRMRect - rotator dst Rectangle
138 */
139 PLANE_SET_ROTATION_DST_RECT,
140 /*
Sushil Chauhan1021cc02017-05-03 15:11:43 -0700141 * Op: Sets FB Secure mode for this plane.
142 * Arg: uint32_t - Plane ID
143 * uint32_t - Value of the FB Secure mode.
144 */
145 PLANE_SET_FB_SECURE_MODE,
146 /*
Ping Li8d6dd622017-07-03 12:05:15 -0700147 * Op: Sets csc config on this plane.
148 * Arg: uint32_t - Plane ID
149 * uint32_t* - pointer to csc type
150 */
151 PLANE_SET_CSC_CONFIG,
152 /*
Ramkumar Radhakrishnan07254302017-11-13 16:18:22 -0800153 * Op: Sets multirect mode on this plane.
154 * Arg: uint32_t - Plane ID
155 * uint32_t - multirect mode
156 */
157 PLANE_SET_MULTIRECT_MODE,
158 /*
Rohit Kulkarni2d7151c2017-12-14 22:17:49 -0800159 * Op: Sets rotator output frame buffer ID for plane.
160 * Arg: uint32_t - Plane ID
161 * uint32_t - Framebuffer ID
162 */
163 PLANE_SET_ROT_FB_ID,
164 /*
Arun Kumar K.R5d30ab52017-12-28 09:05:36 +0530165 * Op: Sets inverse pma mode on this plane.
166 * Arg: uint32_t - Plane ID
167 * uint32_t - enable/disable inverse pma.
168 */
169 PLANE_SET_INVERSE_PMA,
170 /*
171 * Op: Sets csc config on this plane.
172 * Arg: uint32_t - Plane ID
173 * uint64_t - Address of the csc config object(version based)
174 */
175 PLANE_SET_DGM_CSC_CONFIG,
176 /*
177 * Op: Sets SSPP Feature
178 * Arg: uint32_t - Plane ID
179 * DRMPPFeatureInfo * - PP feature data pointer
180 */
181 PLANE_SET_POST_PROC,
182 /*
Saurabh Shah66c941b2016-07-06 17:34:05 -0700183 * Op: Activate or deactivate a CRTC
184 * Arg: uint32_t - CRTC ID
185 * uint32_t - 1 to enable, 0 to disable
186 */
187 CRTC_SET_ACTIVE,
188 /*
189 * Op: Sets display mode
190 * Arg: uint32_t - CRTC ID
191 * drmModeModeInfo* - Pointer to display mode
192 */
193 CRTC_SET_MODE,
194 /*
195 * Op: Sets an offset indicating when a release fence should be signalled.
196 * Arg: uint32_t - offset
197 * 0: non-speculative, default
198 * 1: speculative
199 */
200 CRTC_SET_OUTPUT_FENCE_OFFSET,
201 /*
Ramkumar Radhakrishnan9ed1fd82017-03-09 18:46:41 -0800202 * Op: Sets overall SDE core clock
203 * Arg: uint32_t - CRTC ID
204 * uint32_t - core_clk
205 */
206 CRTC_SET_CORE_CLK,
Ramkumar Radhakrishnan3c4de112017-05-24 22:38:30 -0700207 /*
208 * Op: Sets MNOC bus average bandwidth
Ramkumar Radhakrishnan9ed1fd82017-03-09 18:46:41 -0800209 * Arg: uint32_t - CRTC ID
210 * uint32_t - core_ab
211 */
212 CRTC_SET_CORE_AB,
213 /*
Ramkumar Radhakrishnan3c4de112017-05-24 22:38:30 -0700214 * Op: Sets MNOC bus instantaneous bandwidth
Ramkumar Radhakrishnan9ed1fd82017-03-09 18:46:41 -0800215 * Arg: uint32_t - CRTC ID
216 * uint32_t - core_ib
217 */
218 CRTC_SET_CORE_IB,
219 /*
Ramkumar Radhakrishnan3c4de112017-05-24 22:38:30 -0700220 * Op: Sets LLCC Bus average bandwidth
221 * Arg: uint32_t - CRTC ID
222 * uint32_t - llcc_ab
223 */
224 CRTC_SET_LLCC_AB,
225 /*
226 * Op: Sets LLCC Bus instantaneous bandwidth
227 * Arg: uint32_t - CRTC ID
228 * uint32_t - llcc_ib
229 */
230 CRTC_SET_LLCC_IB,
231 /*
232 * Op: Sets DRAM bus average bandwidth
233 * Arg: uint32_t - CRTC ID
234 * uint32_t - dram_ab
235 */
236 CRTC_SET_DRAM_AB,
237 /*
238 * Op: Sets DRAM bus instantaneous bandwidth
239 * Arg: uint32_t - CRTC ID
240 * uint32_t - dram_ib
241 */
242 CRTC_SET_DRAM_IB,
243 /*
Ramkumar Radhakrishnanb7910442017-12-11 13:32:47 -0800244 * Op: Sets Rotator BW for inline rotation
245 * Arg: uint32_t - CRTC ID
246 * uint32_t - rot_bw
247 */
248 CRTC_SET_ROT_PREFILL_BW,
249 /*
Ramkumar Radhakrishnan3c4de112017-05-24 22:38:30 -0700250 * Op: Sets rotator clock for inline rotation
251 * Arg: uint32_t - CRTC ID
252 * uint32_t - rot_clk
253 */
Namit Solanki24921ab2017-05-23 20:16:25 +0530254 CRTC_SET_ROT_CLK,
255 /*
256 * Op: Sets destination scalar data
257 * Arg: uint32_t - CRTC ID
258 * uint64_t - Pointer to destination scalar data
259 */
260 CRTC_SET_DEST_SCALER_CONFIG,
261 /*
Saurabh Shah66c941b2016-07-06 17:34:05 -0700262 * Op: Returns release fence for this frame. Should be called after Commit() on
263 * DRMAtomicReqInterface.
264 * Arg: uint32_t - CRTC ID
265 * int * - Pointer to an integer that will hold the returned fence
266 */
267 CRTC_GET_RELEASE_FENCE,
268 /*
Ping Li281f48d2017-01-16 12:45:40 -0800269 * Op: Sets PP feature
270 * Arg: uint32_t - CRTC ID
271 * DRMPPFeatureInfo * - PP feature data pointer
272 */
273 CRTC_SET_POST_PROC,
274 /*
Saurabh Shahe9f55d72017-03-03 15:14:13 -0800275 * Op: Sets CRTC ROIs.
276 * Arg: uint32_t - CRTC ID
277 * uint32_t - number of ROIs
278 * DRMRect * - Array of CRTC ROIs
279 */
280 CRTC_SET_ROI,
281 /*
Sushil Chauhan1021cc02017-05-03 15:11:43 -0700282 * Op: Sets Security level for CRTC.
283 * Arg: uint32_t - CRTC ID
284 * uint32_t - Security level
285 */
286 CRTC_SET_SECURITY_LEVEL,
287 /*
Prabhanjan Kanduladbc8aed2017-03-24 14:43:16 -0700288 * Op: sets solid fill stages
289 * Arg: uint32_t - CRTC ID
290 * Vector of DRMSolidfillStage
291 */
292 CRTC_SET_SOLIDFILL_STAGES,
293 /*
Anjaneya Prasad Musunurie8c67f22017-07-01 16:16:13 +0530294 * Op: Sets idle timeout.
295 * Arg: uint32_t - CRTC ID
296 * uint32_t - idle timeout in ms
297 */
298 CRTC_SET_IDLE_TIMEOUT,
299 /*
Sushil Chauhan741ac312018-04-02 12:22:16 -0700300 * Op: Sets Capture mode for Concurrent Writeback feature.
301 * Arg: uint32_t - CRTC ID
302 * uint32_t - Capture mode
303 */
304 CRTC_SET_CAPTURE_MODE,
305 /*
Saurabh Shah66c941b2016-07-06 17:34:05 -0700306 * Op: Returns retire fence for this commit. Should be called after Commit() on
307 * DRMAtomicReqInterface.
308 * Arg: uint32_t - Connector ID
309 * int * - Pointer to an integer that will hold the returned fence
310 */
311 CONNECTOR_GET_RETIRE_FENCE,
312 /*
313 * Op: Sets writeback connector destination rect
314 * Arg: uint32_t - Connector ID
315 * DRMRect - Dst Rectangle
316 */
317 CONNECTOR_SET_OUTPUT_RECT,
318 /*
319 * Op: Sets frame buffer ID for writeback connector.
320 * Arg: uint32_t - Connector ID
321 * uint32_t - Framebuffer ID
322 */
323 CONNECTOR_SET_OUTPUT_FB_ID,
Sushil Chauhan3396e202017-04-14 18:34:22 -0700324 /*
325 * Op: Sets power mode for connector.
326 * Arg: uint32_t - Connector ID
327 * uint32_t - Power Mode
328 */
329 CONNECTOR_SET_POWER_MODE,
Saurabh Shahe9f55d72017-03-03 15:14:13 -0800330 /*
331 * Op: Sets panel ROIs.
332 * Arg: uint32_t - Connector ID
333 * uint32_t - number of ROIs
334 * DRMRect * - Array of Connector ROIs
335 */
336 CONNECTOR_SET_ROI,
Sushil Chauhane2f89c92017-08-23 11:30:34 -0700337 /*
Saurabh Shahf3635952017-10-16 17:08:18 -0700338 * Op: Sets the connector to autorefresh mode.
339 * Arg: uint32_t - Connector ID
340 * uint32_t - Enable-1, Disable-0
341 */
342 CONNECTOR_SET_AUTOREFRESH,
343 /*
Sushil Chauhane2f89c92017-08-23 11:30:34 -0700344 * Op: Set FB secure mode for Writeback connector.
345 * Arg: uint32_t - Connector ID
346 * uint32_t - FB Secure mode
347 */
348 CONNECTOR_SET_FB_SECURE_MODE,
Saurabh Shah82b06f42017-09-06 16:43:49 -0700349 /*
350 * Op: Sets a crtc id to this connector
351 * Arg: uint32_t - Connector ID
352 * uint32_t - CRTC ID
353 */
354 CONNECTOR_SET_CRTC,
Srikanth Rajagopalan7a09b2e2017-06-19 18:41:03 -0700355 /*
Gopikrishnaiah Anandan739faf92017-07-21 12:32:00 -0700356 * Op: Sets PP feature
357 * Arg: uint32_t - Connector ID
358 * DRMPPFeatureInfo * - PP feature data pointer
359 */
Xu Yang32e58c22017-11-20 09:58:11 +0800360 CONNECTOR_SET_POST_PROC,
Gopikrishnaiah Anandan739faf92017-07-21 12:32:00 -0700361 /*
Srikanth Rajagopalan7a09b2e2017-06-19 18:41:03 -0700362 * Op: Sets connector hdr metadata
363 * Arg: uint32_t - Connector ID
364 * drm_msm_ext_hdr_metadata - hdr_metadata
365 */
366 CONNECTOR_SET_HDR_METADATA,
Xu Yang32e58c22017-11-20 09:58:11 +0800367 /*
368 * Op: Cache Dpps features.
369 * Arg: uint32_t - Object ID
370 uint32_t - Feature ID
371 * uint64_t - Pointer to feature config data
372 */
373 DPPS_CACHE_FEATURE,
Xu Yangda642222018-06-12 10:32:33 +0800374 /*
375 * Op: Commit Dpps features.
376 * Arg: drmModeAtomicReq - Atomic request
377 */
378 DPPS_COMMIT_FEATURE,
Saurabh Shah66c941b2016-07-06 17:34:05 -0700379};
380
Saurabh Shahf9266ee2017-04-19 15:25:46 -0700381enum struct DRMRotation {
382 FLIP_H = 0x1,
383 FLIP_V = 0x2,
Prabhanjan Kandula5bc7f8b2017-05-23 12:24:57 -0700384 ROT_180 = FLIP_H | FLIP_V,
Saurabh Shahf9266ee2017-04-19 15:25:46 -0700385 ROT_90 = 0x4,
386};
387
Sushil Chauhan3396e202017-04-14 18:34:22 -0700388enum struct DRMPowerMode {
389 ON,
390 DOZE,
391 DOZE_SUSPEND,
392 OFF,
393};
394
Saurabh Shah66c941b2016-07-06 17:34:05 -0700395enum struct DRMBlendType {
396 UNDEFINED = 0,
397 OPAQUE = 1,
398 PREMULTIPLIED = 2,
399 COVERAGE = 3,
400};
401
Prabhanjan Kandula585aa652017-01-26 18:39:11 -0800402enum struct DRMSrcConfig {
403 DEINTERLACE = 0,
404};
405
Saurabh Shah66c941b2016-07-06 17:34:05 -0700406/* Display type to identify a suitable connector */
407enum struct DRMDisplayType {
408 PERIPHERAL,
409 TV,
410 VIRTUAL,
411};
412
413struct DRMRect {
414 uint32_t left; // Left-most pixel coordinate.
415 uint32_t top; // Top-most pixel coordinate.
416 uint32_t right; // Right-most pixel coordinate.
417 uint32_t bottom; // Bottom-most pixel coordinate.
418};
419
420//------------------------------------------------------------------------
421// DRM Info Query Types
422//------------------------------------------------------------------------
423
424enum struct QSEEDVersion {
425 V1,
426 V2,
427 V3,
428};
429
Rohit Kulkarnibfa855c2017-06-29 17:52:10 -0700430/* QSEED3 Step version */
431enum struct QSEEDStepVersion {
432 V2,
433 V3,
434 V4,
435};
436
Prabhanjan Kandulae6dfab92017-03-14 11:02:49 -0700437enum struct SmartDMARevision {
438 V1,
439 V2,
Mathew Joseph Karimpanal1f8a21c2017-10-20 20:47:42 +0530440 V2p5
Prabhanjan Kandulae6dfab92017-03-14 11:02:49 -0700441};
442
Rohit Kulkarni2d7151c2017-12-14 22:17:49 -0800443/* Inline Rotation version */
444enum struct InlineRotationVersion {
445 UNKNOWN,
446 V1,
447 V1p1, // Rotator FB ID needs to be set
448};
449
Saurabh Shah66c941b2016-07-06 17:34:05 -0700450/* Per CRTC Resource Info*/
451struct DRMCrtcInfo {
452 bool has_src_split;
Srikanth Rajagopalan49380782017-07-06 15:23:12 -0700453 bool has_hdr;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700454 uint32_t max_blend_stages;
Prabhanjan Kanduladbc8aed2017-03-24 14:43:16 -0700455 uint32_t max_solidfill_stages;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700456 QSEEDVersion qseed_version;
Prabhanjan Kandulae6dfab92017-03-14 11:02:49 -0700457 SmartDMARevision smart_dma_rev;
Ramkumar Radhakrishnan9ed1fd82017-03-09 18:46:41 -0800458 float ib_fudge_factor;
459 float clk_fudge_factor;
460 uint32_t dest_scale_prefill_lines;
461 uint32_t undersized_prefill_lines;
462 uint32_t macrotile_prefill_lines;
463 uint32_t nv12_prefill_lines;
464 uint32_t linear_prefill_lines;
465 uint32_t downscale_prefill_lines;
466 uint32_t extra_prefill_lines;
467 uint32_t amortized_threshold;
468 uint64_t max_bandwidth_low;
469 uint64_t max_bandwidth_high;
470 uint32_t max_sde_clk;
471 CompRatioMap comp_ratio_rt_map;
472 CompRatioMap comp_ratio_nrt_map;
Gopikrishnaiah Anandan76815522017-06-27 15:18:04 -0700473 uint32_t hw_version;
Namit Solanki24921ab2017-05-23 20:16:25 +0530474 uint32_t dest_scaler_count = 0;
475 uint32_t max_dest_scaler_input_width = 0;
476 uint32_t max_dest_scaler_output_width = 0;
477 uint32_t max_dest_scale_up = 1;
Pullakavi Srinivas3e2c0402017-12-05 17:50:15 +0530478 uint32_t min_prefill_lines = 0;
Ramkumar Radhakrishnana38b7602018-03-15 14:49:52 -0700479 int secure_disp_blend_stage = -1;
Sushil Chauhanc75358e2018-04-24 14:36:38 -0700480 bool concurrent_writeback = false;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700481};
482
483enum struct DRMPlaneType {
484 // Has CSC and scaling capability
485 VIG = 0,
486 // Has scaling capability but no CSC
487 RGB,
488 // No scaling support
489 DMA,
490 // Supports a small dimension and doesn't use a CRTC stage
491 CURSOR,
492 MAX,
493};
494
Arun Kumar K.R5d30ab52017-12-28 09:05:36 +0530495enum struct DRMTonemapLutType {
496 DMA_1D_GC,
497 DMA_1D_IGC,
498 VIG_1D_IGC,
499 VIG_3D_GAMUT,
500};
501
Saurabh Shah66c941b2016-07-06 17:34:05 -0700502struct DRMPlaneTypeInfo {
Prabhanjan Kandulae6dfab92017-03-14 11:02:49 -0700503 DRMPlaneType type;
504 uint32_t master_plane_id;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700505 // FourCC format enum and modifier
506 std::vector<std::pair<uint32_t, uint64_t>> formats_supported;
507 uint32_t max_linewidth;
Mathew Joseph Karimpanal1f8a21c2017-10-20 20:47:42 +0530508 uint32_t max_scaler_linewidth;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700509 uint32_t max_upscale;
510 uint32_t max_downscale;
511 uint32_t max_horizontal_deci;
512 uint32_t max_vertical_deci;
Ramkumar Radhakrishnan9ed1fd82017-03-09 18:46:41 -0800513 uint64_t max_pipe_bandwidth;
Rohit Kulkarni8622e362017-01-30 18:14:10 -0800514 uint32_t cache_size; // cache size in bytes for inline rotation support.
Namit Solanki6d0d8062017-11-30 17:29:48 +0530515 bool has_excl_rect = false;
Rohit Kulkarnibfa855c2017-06-29 17:52:10 -0700516 QSEEDStepVersion qseed3_version;
Ramkumar Radhakrishnan07254302017-11-13 16:18:22 -0800517 bool multirect_prop_present = false;
Rohit Kulkarni2d7151c2017-12-14 22:17:49 -0800518 InlineRotationVersion inrot_version; // inline rotation version
Arun Kumar K.R5d30ab52017-12-28 09:05:36 +0530519 bool inverse_pma = false;
520 uint32_t dgm_csc_version = 0; // csc used with DMA
521 std::map<DRMTonemapLutType, uint32_t> tonemap_lut_version_map = {};
Ramkumar Radhakrishnan4a269752018-03-08 14:53:15 -0800522 bool block_sec_ui = false;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700523};
524
Prabhanjan Kandulae6dfab92017-03-14 11:02:49 -0700525// All DRM Planes as map<Plane_id , plane_type_info> listed from highest to lowest priority
526typedef std::vector<std::pair<uint32_t, DRMPlaneTypeInfo>> DRMPlanesInfo;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700527
528enum struct DRMTopology {
Rohit Kulkarni2faa91c2017-06-05 15:43:48 -0700529 UNKNOWN, // To be compat with driver defs in sde_rm.h
Saurabh Shah66c941b2016-07-06 17:34:05 -0700530 SINGLE_LM,
Rohit Kulkarni2faa91c2017-06-05 15:43:48 -0700531 SINGLE_LM_DSC,
Saurabh Shah66c941b2016-07-06 17:34:05 -0700532 DUAL_LM,
Rohit Kulkarni2faa91c2017-06-05 15:43:48 -0700533 DUAL_LM_DSC,
Saurabh Shah66c941b2016-07-06 17:34:05 -0700534 DUAL_LM_MERGE,
Rohit Kulkarni2faa91c2017-06-05 15:43:48 -0700535 DUAL_LM_MERGE_DSC,
536 DUAL_LM_DSCMERGE,
537 PPSPLIT,
Saurabh Shah66c941b2016-07-06 17:34:05 -0700538};
539
540enum struct DRMPanelMode {
541 VIDEO,
542 COMMAND,
543};
544
Saurabh Shah7e16c932017-11-03 17:55:36 -0700545/* Per mode info */
546struct DRMModeInfo {
547 drmModeModeInfo mode;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700548 DRMTopology topology;
Saurabh Shahe9f55d72017-03-03 15:14:13 -0800549 // Valid only if mode is command
550 int num_roi;
551 int xstart;
552 int ystart;
553 int walign;
554 int halign;
555 int wmin;
556 int hmin;
557 bool roi_merge;
Saurabh Shah7e16c932017-11-03 17:55:36 -0700558};
559
560/* Per Connector Info*/
561struct DRMConnectorInfo {
562 uint32_t mmWidth;
563 uint32_t mmHeight;
564 uint32_t type;
565 std::vector<DRMModeInfo> modes;
566 std::string panel_name;
567 DRMPanelMode panel_mode;
568 bool is_primary;
569 // Valid only if DRMPanelMode is VIDEO
570 bool dynamic_fps;
571 // FourCC format enum and modifier
572 std::vector<std::pair<uint32_t, uint64_t>> formats_supported;
573 // Valid only if type is DRM_MODE_CONNECTOR_VIRTUAL
574 uint32_t max_linewidth;
Prabhanjan Kandula5bc7f8b2017-05-23 12:24:57 -0700575 DRMRotation panel_orientation;
Sushil Chauhan80e58432017-07-06 11:39:17 -0700576 drm_panel_hdr_properties panel_hdr_prop;
Ramkumar Radhakrishnan5c94f052017-07-06 11:59:14 -0700577 uint32_t transfer_time_us;
Srikanth Rajagopalance0f7cb2017-06-12 15:14:26 -0700578 drm_msm_ext_hdr_properties ext_hdr_prop;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700579};
580
581/* Identifier token for a display */
582struct DRMDisplayToken {
583 uint32_t conn_id;
584 uint32_t crtc_id;
Saurabh Shahf8226712018-02-05 15:51:53 -0800585 uint32_t crtc_index;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700586};
587
Ping Li281f48d2017-01-16 12:45:40 -0800588enum DRMPPFeatureID {
589 kFeaturePcc,
590 kFeatureIgc,
591 kFeaturePgc,
592 kFeatureMixerGc,
593 kFeaturePaV2,
594 kFeatureDither,
595 kFeatureGamut,
596 kFeaturePADither,
Rajesh Yadavd30b0cc2017-09-22 00:26:54 +0530597 kFeaturePAHsic,
598 kFeaturePASixZone,
Rajesh Yadav99535ac2017-08-28 16:33:04 +0530599 kFeaturePAMemColSkin,
600 kFeaturePAMemColSky,
601 kFeaturePAMemColFoliage,
602 kFeaturePAMemColProt,
Rajesh Yadavc4f67b82017-11-15 20:37:13 +0530603 kFeatureDgmIgc,
604 kFeatureDgmGc,
605 kFeatureVigIgc,
606 kFeatureVigGamut,
Ping Li281f48d2017-01-16 12:45:40 -0800607 kPPFeaturesMax,
608};
609
610enum DRMPPPropType {
611 kPropEnum,
612 kPropRange,
613 kPropBlob,
614 kPropTypeMax,
615};
616
617struct DRMPPFeatureInfo {
618 DRMPPFeatureID id;
619 DRMPPPropType type;
620 uint32_t version;
621 uint32_t payload_size;
622 void *payload;
Gopikrishnaiah Anandan739faf92017-07-21 12:32:00 -0700623 uint32_t object_type;
Ping Li281f48d2017-01-16 12:45:40 -0800624};
625
Xu Yang32e58c22017-11-20 09:58:11 +0800626enum DRMDPPSFeatureID {
627 // Ad4 properties
628 kFeatureAd4Mode,
629 kFeatureAd4Init,
630 kFeatureAd4Cfg,
631 kFeatureAd4Input,
632 kFeatureAd4Backlight,
633 kFeatureAd4Assertiveness,
634 kFeatureAd4ManualStrength,
635 // ABA properties
636 kFeatureAbaHistCtrl,
637 kFeatureAbaHistIRQ,
638 kFeatureAbaLut,
639 // BL scale properties
640 kFeatureAd4BlScale,
641 kFeatureBacklightScale,
642 // Events
643 kFeaturePowerEvent,
644 kFeatureAbaHistEvent,
645 kFeatureBackLightEvent,
646 kFeatureAdAttBlEvent,
647 // Insert features above
648 kDppsFeaturesMax,
649};
650
Ping Li6a74d892018-05-02 15:54:58 -0700651struct DppsFeaturePayload {
652 uint32_t object_type;
653 uint32_t feature_id;
654 uint64_t value;
655};
656
Xu Yang32e58c22017-11-20 09:58:11 +0800657struct DRMDppsFeatureInfo {
658 DRMDPPSFeatureID id;
659 uint32_t version;
660};
661
662enum AD4Modes {
663 kAd4Off,
664 kAd4AutoStrength,
665 kAd4Calibration,
666 kAd4Manual,
667 kAd4ModeMax,
668};
669
670enum HistModes {
671 kHistDisabled,
672 kHistEnabled,
673};
674
675struct DRMDppsEventInfo {
676 uint32_t object_type;
677 uint32_t event_type;
678 int drm_fd;
679 bool enable;
680};
681
Ping Li8d6dd622017-07-03 12:05:15 -0700682enum DRMCscType {
683 kCscYuv2Rgb601L,
684 kCscYuv2Rgb601FR,
685 kCscYuv2Rgb709L,
686 kCscYuv2Rgb2020L,
687 kCscYuv2Rgb2020FR,
688 kCscTypeMax,
689};
690
Saurabh Shah0ffee302016-11-22 10:42:11 -0800691struct DRMScalerLUTInfo {
692 uint32_t dir_lut_size = 0;
693 uint32_t cir_lut_size = 0;
694 uint32_t sep_lut_size = 0;
695 uint64_t dir_lut = 0;
696 uint64_t cir_lut = 0;
697 uint64_t sep_lut = 0;
698};
699
Sushil Chauhan1021cc02017-05-03 15:11:43 -0700700enum struct DRMSecureMode {
701 NON_SECURE,
702 SECURE,
703 NON_SECURE_DIR_TRANSLATION,
704 SECURE_DIR_TRANSLATION,
705};
706
707enum struct DRMSecurityLevel {
708 SECURE_NON_SECURE,
709 SECURE_ONLY,
710};
711
Ramkumar Radhakrishnan07254302017-11-13 16:18:22 -0800712enum struct DRMMultiRectMode {
713 NONE = 0,
714 PARALLEL = 1,
715 SERIAL = 2,
716};
717
Sushil Chauhan741ac312018-04-02 12:22:16 -0700718enum struct DRMCWbCaptureMode {
719 MIXER_OUT = 0,
720 DSPP_OUT = 1,
721};
722
Prabhanjan Kanduladbc8aed2017-03-24 14:43:16 -0700723struct DRMSolidfillStage {
Xu Yang32e58c22017-11-20 09:58:11 +0800724 DRMRect bounding_rect {};
725 bool is_exclusion_rect = false;
726 uint32_t color = 0xff000000; // in 8bit argb
727 uint32_t red = 0;
728 uint32_t blue = 0;
729 uint32_t green = 0;
730 uint32_t alpha = 0xff;
731 uint32_t color_bit_depth = 0;
732 uint32_t z_order = 0;
733 uint32_t plane_alpha = 0xff;
Prabhanjan Kanduladbc8aed2017-03-24 14:43:16 -0700734};
735
Saurabh Shah66c941b2016-07-06 17:34:05 -0700736/* DRM Atomic Request Property Set.
737 *
738 * Helper class to create and populate atomic properties of DRM components
739 * when rendered in DRM atomic mode */
740class DRMAtomicReqInterface {
741 public:
742 virtual ~DRMAtomicReqInterface() {}
743 /* Perform request operation.
744 *
745 * [input]: opcode: operation code from DRMOps list.
Saurabh Shah1abcdf62017-11-21 14:03:22 -0800746 * obj_id: Relevant crtc, connector, plane id
Saurabh Shah66c941b2016-07-06 17:34:05 -0700747 * var_arg: arguments for DRMOps's can differ in number and
748 * data type. Refer above DRMOps to details.
749 * [return]: Error code if the API fails, 0 on success.
750 */
Saurabh Shah1abcdf62017-11-21 14:03:22 -0800751 virtual int Perform(DRMOps opcode, uint32_t obj_id, ...) = 0;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700752
753 /*
754 * Commit the params set via Perform(). Also resets the properties after commit. Needs to be
755 * called every frame.
756 * [input]: synchronous: Determines if the call should block until a h/w flip
Saurabh Shaha917aa72017-09-15 13:27:24 -0700757 * [input]: retain_planes: Retains already staged planes. Useful when not explicitly programming
758 * planes but still need the previously staged ones to not be unstaged
Saurabh Shah66c941b2016-07-06 17:34:05 -0700759 * [return]: Error code if the API fails, 0 on success.
760 */
Saurabh Shaha917aa72017-09-15 13:27:24 -0700761 virtual int Commit(bool synchronous, bool retain_planes) = 0;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700762 /*
763 * Validate the params set via Perform().
764 * [return]: Error code if the API fails, 0 on success.
765 */
766 virtual int Validate() = 0;
767};
768
769class DRMManagerInterface;
770
771/* Populates a singleton instance of DRMManager */
772typedef int (*GetDRMManager)(int fd, DRMManagerInterface **intf);
773
774/* Destroy DRMManager instance */
Saurabh Shahab7807c2017-02-08 15:41:08 -0800775typedef int (*DestroyDRMManager)();
Saurabh Shah66c941b2016-07-06 17:34:05 -0700776
777/*
778 * DRM Manager Interface - Any class which plans to implement helper function for vendor
779 * specific DRM driver implementation must implement the below interface routines to work
780 * with SDM.
781 */
782
783class DRMManagerInterface {
784 public:
785 virtual ~DRMManagerInterface() {}
786
787 /*
788 * Since SDM completely manages the planes. GetPlanesInfo will provide all
789 * the plane information.
790 * [output]: DRMPlanesInfo: Resource Info for planes.
791 */
792 virtual void GetPlanesInfo(DRMPlanesInfo *info) = 0;
793
794 /*
795 * Will provide all the information of a selected crtc.
796 * [input]: Use crtc id 0 to obtain system wide info
797 * [output]: DRMCrtcInfo: Resource Info for the given CRTC id.
798 */
799 virtual void GetCrtcInfo(uint32_t crtc_id, DRMCrtcInfo *info) = 0;
800
801 /*
802 * Will provide all the information of a selected connector.
803 * [output]: DRMConnectorInfo: Resource Info for the given connector id
804 */
805 virtual void GetConnectorInfo(uint32_t conn_id, DRMConnectorInfo *info) = 0;
806
807 /*
Ping Li281f48d2017-01-16 12:45:40 -0800808 * Will query post propcessing feature info of a CRTC.
809 * [output]: DRMPPFeatureInfo: CRTC post processing feature info
810 */
Namit Solanki24921ab2017-05-23 20:16:25 +0530811 virtual void GetCrtcPPInfo(uint32_t crtc_id, DRMPPFeatureInfo *info) = 0;
Ping Li281f48d2017-01-16 12:45:40 -0800812 /*
Saurabh Shah66c941b2016-07-06 17:34:05 -0700813 * Register a logical display to receive a token.
814 * Each display pipeline in DRM is identified by its CRTC and Connector(s).
815 * On display connect(bootup or hotplug), clients should invoke this interface to
816 * establish the pipeline for the display and should get a DisplayToken
817 * populated with crtc and connnector(s) id's. Here onwards, Client should
818 * use this token to represent the display for any Perform operations if
819 * needed.
820 *
821 * [input]: disp_type - Peripheral / TV / Virtual
822 * [output]: DRMDisplayToken - CRTC and Connector id's for the display
823 * [return]: 0 on success, a negative error value otherwise
824 */
825 virtual int RegisterDisplay(DRMDisplayType disp_type, DRMDisplayToken *tok) = 0;
826
827 /* Client should invoke this interface on display disconnect.
828 * [input]: DRMDisplayToken - identifier for the display.
829 */
830 virtual void UnregisterDisplay(const DRMDisplayToken &token) = 0;
831
832 /*
833 * Creates and returns an instance of DRMAtomicReqInterface corresponding to a display token
834 * returned as part of RegisterDisplay API. Needs to be called per display.
835 * [input]: DRMDisplayToken that identifies a display pipeline
836 * [output]: Pointer to an instance of DRMAtomicReqInterface.
837 * [return]: Error code if the API fails, 0 on success.
838 */
839 virtual int CreateAtomicReq(const DRMDisplayToken &token, DRMAtomicReqInterface **intf) = 0;
840
841 /*
842 * Destroys the instance of DRMAtomicReqInterface
843 * [input]: Pointer to a DRMAtomicReqInterface
844 * [return]: Error code if the API fails, 0 on success.
845 */
846 virtual int DestroyAtomicReq(DRMAtomicReqInterface *intf) = 0;
Saurabh Shah0ffee302016-11-22 10:42:11 -0800847 /*
848 * Sets the global scaler LUT
849 * [input]: LUT Info
850 * [return]: Error code if the API fails, 0 on success.
851 */
852 virtual int SetScalerLUT(const DRMScalerLUTInfo &lut_info) = 0;
Xu Yang32e58c22017-11-20 09:58:11 +0800853
854 /*
855 * Get the DPPS feature info
856 * [input]: Dpps feature id, info->id
857 * [output]: Dpps feature version, info->version
858 */
859 virtual void GetDppsFeatureInfo(DRMDppsFeatureInfo *info) = 0;
Saurabh Shah66c941b2016-07-06 17:34:05 -0700860};
Saurabh Shah0ffee302016-11-22 10:42:11 -0800861
Saurabh Shah66c941b2016-07-06 17:34:05 -0700862} // namespace sde_drm
863#endif // __DRM_INTERFACE_H__