blob: 1c2a619020352102fccf825124ebb2ac91fe4db2 [file] [log] [blame]
Brian Carlstrom7940e442013-07-12 13:46:57 -07001/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "codegen_x86.h"
Andreas Gampe0b9203e2015-01-22 20:39:27 -080018
Vladimir Marko80afd022015-05-19 18:08:00 +010019#include "base/bit_utils.h"
Andreas Gampe0b9203e2015-01-22 20:39:27 -080020#include "base/logging.h"
21#include "dex/compiler_ir.h"
22#include "dex/quick/mir_to_lir.h"
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -070023#include "oat.h"
Nicolas Geoffray524e7ea2015-10-16 17:13:34 +010024#include "oat_quick_method_header.h"
Vladimir Marko80afd022015-05-19 18:08:00 +010025#include "utils.h"
Brian Carlstrom7940e442013-07-12 13:46:57 -070026#include "x86_lir.h"
27
28namespace art {
29
30#define MAX_ASSEMBLER_RETRIES 50
31
32const X86EncodingMap X86Mir2Lir::EncodingMap[kX86Last] = {
Ian Rogers0f9b9c52014-06-09 01:32:12 -070033 { kX8632BitData, kData, IS_UNARY_OP, { 0, 0, 0x00, 0, 0, 0, 0, 4, false }, "data", "0x!0d" },
34 { kX86Bkpt, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xCC, 0, 0, 0, 0, 0, false }, "int 3", "" },
35 { kX86Nop, kNop, NO_OPERAND, { 0, 0, 0x90, 0, 0, 0, 0, 0, false }, "nop", "" },
Brian Carlstrom7940e442013-07-12 13:46:57 -070036
37#define ENCODING_MAP(opname, mem_use, reg_def, uses_ccodes, \
38 rm8_r8, rm32_r32, \
39 r8_rm8, r32_rm32, \
40 ax8_i8, ax32_i32, \
41 rm8_i8, rm8_i8_modrm, \
42 rm32_i32, rm32_i32_modrm, \
43 rm32_i8, rm32_i8_modrm) \
Ian Rogers0f9b9c52014-06-09 01:32:12 -070044{ kX86 ## opname ## 8MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8MR", "[!0r+!1d],!2r" }, \
Mark Mendell2bc47702014-07-31 14:36:54 -040045{ kX86 ## opname ## 8AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8AR", "[!0r+!1r<<!2d+!3d],!4r" }, \
Ian Rogers0f9b9c52014-06-09 01:32:12 -070046{ kX86 ## opname ## 8TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8TR", "fs:[!0d],!1r" }, \
47{ kX86 ## opname ## 8RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RR", "!0r,!1r" }, \
48{ kX86 ## opname ## 8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RM", "!0r,[!1r+!2d]" }, \
49{ kX86 ## opname ## 8RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \
50{ kX86 ## opname ## 8RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RT", "!0r,fs:[!1d]" }, \
51{ kX86 ## opname ## 8RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, ax8_i8, 1, true }, #opname "8RI", "!0r,!1d" }, \
Mark Mendellfd0c2372014-07-31 13:20:21 -040052{ kX86 ## opname ## 8MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, false}, #opname "8MI", "[!0r+!1d],!2d" }, \
53{ kX86 ## opname ## 8AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, false}, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
54{ kX86 ## opname ## 8TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, false}, #opname "8TI", "fs:[!0d],!1d" }, \
Brian Carlstrom7940e442013-07-12 13:46:57 -070055 \
Ian Rogers0f9b9c52014-06-09 01:32:12 -070056{ kX86 ## opname ## 16MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16MR", "[!0r+!1d],!2r" }, \
57{ kX86 ## opname ## 16AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \
58{ kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16TR", "fs:[!0d],!1r" }, \
59{ kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RR", "!0r,!1r" }, \
60{ kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RM", "!0r,[!1r+!2d]" }, \
61{ kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \
62{ kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RT", "!0r,fs:[!1d]" }, \
63{ kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2, false }, #opname "16RI", "!0r,!1d" }, \
64{ kX86 ## opname ## 16MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16MI", "[!0r+!1d],!2d" }, \
65{ kX86 ## opname ## 16AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
66{ kX86 ## opname ## 16TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16TI", "fs:[!0d],!1d" }, \
67{ kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16RI8", "!0r,!1d" }, \
68{ kX86 ## opname ## 16MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16MI8", "[!0r+!1d],!2d" }, \
69{ kX86 ## opname ## 16AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \
70{ kX86 ## opname ## 16TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16TI8", "fs:[!0d],!1d" }, \
Brian Carlstrom7940e442013-07-12 13:46:57 -070071 \
Ian Rogers0f9b9c52014-06-09 01:32:12 -070072{ kX86 ## opname ## 32MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32MR", "[!0r+!1d],!2r" }, \
73{ kX86 ## opname ## 32AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \
74{ kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32TR", "fs:[!0d],!1r" }, \
75{ kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RR", "!0r,!1r" }, \
76{ kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RM", "!0r,[!1r+!2d]" }, \
77{ kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \
78{ kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RT", "!0r,fs:[!1d]" }, \
79{ kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4, false }, #opname "32RI", "!0r,!1d" }, \
80{ kX86 ## opname ## 32MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32MI", "[!0r+!1d],!2d" }, \
81{ kX86 ## opname ## 32AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
82{ kX86 ## opname ## 32TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32TI", "fs:[!0d],!1d" }, \
83{ kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32RI8", "!0r,!1d" }, \
84{ kX86 ## opname ## 32MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32MI8", "[!0r+!1d],!2d" }, \
85{ kX86 ## opname ## 32AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \
86{ kX86 ## opname ## 32TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32TI8", "fs:[!0d],!1d" }, \
Dmitry Petrochenko96992e82014-05-20 04:03:46 +070087 \
Ian Rogers0f9b9c52014-06-09 01:32:12 -070088{ kX86 ## opname ## 64MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64MR", "[!0r+!1d],!2r" }, \
89{ kX86 ## opname ## 64AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64AR", "[!0r+!1r<<!2d+!3d],!4r" }, \
90{ kX86 ## opname ## 64TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64TR", "fs:[!0d],!1r" }, \
91{ kX86 ## opname ## 64RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RR", "!0r,!1r" }, \
92{ kX86 ## opname ## 64RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RM", "!0r,[!1r+!2d]" }, \
93{ kX86 ## opname ## 64RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \
94{ kX86 ## opname ## 64RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RT", "!0r,fs:[!1d]" }, \
95{ kX86 ## opname ## 64RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4, false }, #opname "64RI", "!0r,!1d" }, \
96{ kX86 ## opname ## 64MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64MI", "[!0r+!1d],!2d" }, \
97{ kX86 ## opname ## 64AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
98{ kX86 ## opname ## 64TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64TI", "fs:[!0d],!1d" }, \
99{ kX86 ## opname ## 64RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64RI8", "!0r,!1d" }, \
100{ kX86 ## opname ## 64MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64MI8", "[!0r+!1d],!2d" }, \
101{ kX86 ## opname ## 64AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \
102{ kX86 ## opname ## 64TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64TI8", "fs:[!0d],!1d" }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700103
104ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0,
105 0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */,
106 0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */,
107 0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */,
108 0x80, 0x0 /* RegMem8/imm8 */,
109 0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */),
110ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0,
111 0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */,
112 0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */,
113 0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */,
114 0x80, 0x1 /* RegMem8/imm8 */,
115 0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */),
116ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,
117 0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */,
118 0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */,
119 0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */,
120 0x80, 0x2 /* RegMem8/imm8 */,
121 0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */),
122ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,
123 0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */,
124 0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */,
125 0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */,
126 0x80, 0x3 /* RegMem8/imm8 */,
127 0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */),
128ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0,
129 0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */,
130 0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */,
131 0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */,
132 0x80, 0x4 /* RegMem8/imm8 */,
133 0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */),
134ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0,
135 0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */,
136 0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */,
137 0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */,
138 0x80, 0x5 /* RegMem8/imm8 */,
139 0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */),
140ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0,
141 0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */,
142 0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */,
143 0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */,
144 0x80, 0x6 /* RegMem8/imm8 */,
145 0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */),
146ENCODING_MAP(Cmp, IS_LOAD, 0, 0,
147 0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */,
148 0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */,
149 0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */,
150 0x80, 0x7 /* RegMem8/imm8 */,
151 0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */),
152#undef ENCODING_MAP
153
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700154 { kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RRI", "!0r,!1r,!2d" },
155 { kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RMI", "!0r,[!1r+!2d],!3d" },
156 { kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },
Brian Carlstrom7940e442013-07-12 13:46:57 -0700157
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700158 { kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RRI", "!0r,!1r,!2d" },
159 { kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RMI", "!0r,[!1r+!2d],!3d" },
160 { kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },
161 { kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RRI8", "!0r,!1r,!2d" },
162 { kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" },
163 { kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" },
Brian Carlstrom7940e442013-07-12 13:46:57 -0700164
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700165 { kX86Imul64RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RRI", "!0r,!1r,!2d" },
166 { kX86Imul64RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RMI", "!0r,[!1r+!2d],!3d" },
167 { kX86Imul64RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },
168 { kX86Imul64RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RRI8", "!0r,!1r,!2d" },
169 { kX86Imul64RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RMI8", "!0r,[!1r+!2d],!3d" },
170 { kX86Imul64RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" },
Dmitry Petrochenko96992e82014-05-20 04:03:46 +0700171
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700172 { kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8MR", "[!0r+!1d],!2r" },
173 { kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" },
174 { kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8TR", "fs:[!0d],!1r" },
175 { kX86Mov8RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RR", "!0r,!1r" },
176 { kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RM", "!0r,[!1r+!2d]" },
177 { kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" },
178 { kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RT", "!0r,fs:[!1d]" },
179 { kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1, true }, "Mov8RI", "!0r,!1d" },
Mark Mendellfd0c2372014-07-31 13:20:21 -0400180 { kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC6, 0, 0, 0, 0, 1, false}, "Mov8MI", "[!0r+!1d],!2d" },
181 { kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC6, 0, 0, 0, 0, 1, false}, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" },
182 { kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1, false}, "Mov8TI", "fs:[!0d],!1d" },
Brian Carlstrom7940e442013-07-12 13:46:57 -0700183
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700184 { kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov16MR", "[!0r+!1d],!2r" },
185 { kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" },
186 { kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0, false }, "Mov16TR", "fs:[!0d],!1r" },
187 { kX86Mov16RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RR", "!0r,!1r" },
188 { kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RM", "!0r,[!1r+!2d]" },
189 { kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" },
190 { kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RT", "!0r,fs:[!1d]" },
191 { kX86Mov16RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2, false }, "Mov16RI", "!0r,!1d" },
192 { kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16MI", "[!0r+!1d],!2d" },
193 { kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" },
194 { kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16TI", "fs:[!0d],!1d" },
Brian Carlstrom7940e442013-07-12 13:46:57 -0700195
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700196 { kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32MR", "[!0r+!1d],!2r" },
197 { kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" },
Razvan A Lupusoruae9f3e62014-09-23 14:54:32 -0700198 { kX86Movnti32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x0F, 0xC3, 0, 0, 0, 0, false }, "Movnti32MR", "[!0r+!1d],!2r" },
199 { kX86Movnti32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x0F, 0xC3, 0, 0, 0, 0, false }, "Movnti32AR", "[!0r+!1r<<!2d+!3d],!4r" },
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700200 { kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32TR", "fs:[!0d],!1r" },
Haitao Fenga870bc52014-09-09 15:52:34 +0800201 { kX86Mov32RR, kRegReg, IS_MOVE | IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RR", "!0r,!1r" },
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700202 { kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RM", "!0r,[!1r+!2d]" },
203 { kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" },
204 { kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RT", "!0r,fs:[!1d]" },
205 { kX86Mov32RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4, false }, "Mov32RI", "!0r,!1d" },
206 { kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32MI", "[!0r+!1d],!2d" },
207 { kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" },
208 { kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32TI", "fs:[!0d],!1d" },
Brian Carlstrom7940e442013-07-12 13:46:57 -0700209
Haitao Fenga870bc52014-09-09 15:52:34 +0800210 { kX86Lea32RM, kRegMem, IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea32RM", "!0r,[!1r+!2d]" },
211 { kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" },
Mark Mendell4028a6c2014-02-19 20:06:20 -0800212
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700213 { kX86Mov64MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { REX_W, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov64MR", "[!0r+!1d],!2r" },
214 { kX86Mov64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { REX_W, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov64AR", "[!0r+!1r<<!2d+!3d],!4r" },
Razvan A Lupusoruae9f3e62014-09-23 14:54:32 -0700215 { kX86Movnti64MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { REX_W, 0, 0x0F, 0xC3, 0, 0, 0, 0, false }, "Movnti64MR", "[!0r+!1d],!2r" },
216 { kX86Movnti64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { REX_W, 0, 0x0F, 0xC3, 0, 0, 0, 0, false }, "Movnti64AR", "[!0r+!1r<<!2d+!3d],!4r" },
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700217 { kX86Mov64TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, REX_W, 0x89, 0, 0, 0, 0, 0, false }, "Mov64TR", "fs:[!0d],!1r" },
Haitao Fenga870bc52014-09-09 15:52:34 +0800218 { kX86Mov64RR, kRegReg, IS_MOVE | IS_BINARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RR", "!0r,!1r" },
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700219 { kX86Mov64RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RM", "!0r,[!1r+!2d]" },
220 { kX86Mov64RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RA", "!0r,[!1r+!2r<<!3d+!4d]" },
221 { kX86Mov64RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, REX_W, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RT", "!0r,fs:[!1d]" },
Yixin Shou5192cbb2014-07-01 13:48:17 -0400222 { kX86Mov64RI32, kRegImm, IS_BINARY_OP | REG_DEF0, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64RI32", "!0r,!1d" },
223 { kX86Mov64RI64, kMovRegQuadImm, IS_TERTIARY_OP | REG_DEF0, { REX_W, 0, 0xB8, 0, 0, 0, 0, 8, false }, "Mov64RI64", "!0r,!1q" },
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700224 { kX86Mov64MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64MI", "[!0r+!1d],!2d" },
225 { kX86Mov64AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64AI", "[!0r+!1r<<!2d+!3d],!4d" },
226 { kX86Mov64TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, REX_W, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64TI", "fs:[!0d],!1d" },
Brian Carlstrom7940e442013-07-12 13:46:57 -0700227
Haitao Fenga870bc52014-09-09 15:52:34 +0800228 { kX86Lea64RM, kRegMem, IS_TERTIARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea64RM", "!0r,[!1r+!2d]" },
229 { kX86Lea64RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { REX_W, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea64RA", "!0r,[!1r+!2r<<!3d+!4d]" },
Razvan A Lupusorubd288c22013-12-20 17:27:23 -0800230
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700231 { kX86Cmov32RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc32RR", "!2c !0r,!1r" },
232 { kX86Cmov64RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, { REX_W, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc64RR", "!2c !0r,!1r" },
Dmitry Petrochenko96992e82014-05-20 04:03:46 +0700233
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700234 { kX86Cmov32RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc32RM", "!3c !0r,[!1r+!2d]" },
235 { kX86Cmov64RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, { REX_W, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc64RM", "!3c !0r,[!1r+!2d]" },
Mark Mendell2637f2e2014-04-30 10:10:47 -0400236
Brian Carlstrom7940e442013-07-12 13:46:57 -0700237#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700238{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8RI", "!0r,!1d" }, \
239{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8MI", "[!0r+!1d],!2d" }, \
240{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
241{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8RC", "!0r,cl" }, \
242{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8MC", "[!0r+!1d],cl" }, \
243{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \
Brian Carlstrom7940e442013-07-12 13:46:57 -0700244 \
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700245{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16RI", "!0r,!1d" }, \
246{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16MI", "[!0r+!1d],!2d" }, \
247{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
248{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16RC", "!0r,cl" }, \
249{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16MC", "[!0r+!1d],cl" }, \
250{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \
Brian Carlstrom7940e442013-07-12 13:46:57 -0700251 \
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700252{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32RI", "!0r,!1d" }, \
253{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32MI", "[!0r+!1d],!2d" }, \
254{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
255{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32RC", "!0r,cl" }, \
256{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32MC", "[!0r+!1d],cl" }, \
257{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }, \
Dmitry Petrochenko96992e82014-05-20 04:03:46 +0700258 \
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700259{ kX86 ## opname ## 64RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64RI", "!0r,!1d" }, \
260{ kX86 ## opname ## 64MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64MI", "[!0r+!1d],!2d" }, \
261{ kX86 ## opname ## 64AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
262{ kX86 ## opname ## 64RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64RC", "!0r,cl" }, \
263{ kX86 ## opname ## 64MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64MC", "[!0r+!1d],cl" }, \
264{ kX86 ## opname ## 64AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64AC", "[!0r+!1r<<!2d+!3d],cl" }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700265
266 SHIFT_ENCODING_MAP(Rol, 0x0),
267 SHIFT_ENCODING_MAP(Ror, 0x1),
268 SHIFT_ENCODING_MAP(Rcl, 0x2),
269 SHIFT_ENCODING_MAP(Rcr, 0x3),
270 SHIFT_ENCODING_MAP(Sal, 0x4),
271 SHIFT_ENCODING_MAP(Shr, 0x5),
272 SHIFT_ENCODING_MAP(Sar, 0x7),
273#undef SHIFT_ENCODING_MAP
274
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700275 { kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0, false }, "Cmc", "" },
276 { kX86Shld32RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld32RRI", "!0r,!1r,!2d" },
Yixin Shouf40f8902014-08-14 14:10:32 -0400277 { kX86Shld32RRC, kShiftRegRegCl, IS_TERTIARY_OP | REG_DEF0_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0x0F, 0xA5, 0, 0, 0, 0, false }, "Shld32RRC", "!0r,!1r,cl" },
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700278 { kX86Shld32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld32MRI", "[!0r+!1d],!2r,!3d" },
279 { kX86Shrd32RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd32RRI", "!0r,!1r,!2d" },
Yixin Shouf40f8902014-08-14 14:10:32 -0400280 { kX86Shrd32RRC, kShiftRegRegCl, IS_TERTIARY_OP | REG_DEF0_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0x0F, 0xAD, 0, 0, 0, 0, false }, "Shrd32RRC", "!0r,!1r,cl" },
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700281 { kX86Shrd32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd32MRI", "[!0r+!1d],!2r,!3d" },
282 { kX86Shld64RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { REX_W, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld64RRI", "!0r,!1r,!2d" },
283 { kX86Shld64MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { REX_W, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld64MRI", "[!0r+!1d],!2r,!3d" },
284 { kX86Shrd64RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { REX_W, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd64RRI", "!0r,!1r,!2d" },
285 { kX86Shrd64MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { REX_W, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd64MRI", "[!0r+!1d],!2r,!3d" },
Brian Carlstrom7940e442013-07-12 13:46:57 -0700286
Dave Allison69dfe512014-07-11 17:11:58 +0000287 { kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8RI", "!0r,!1d" },
288 { kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8MI", "[!0r+!1d],!2d" },
289 { kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" },
290 { kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16RI", "!0r,!1d" },
291 { kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16MI", "[!0r+!1d],!2d" },
292 { kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" },
293 { kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32RI", "!0r,!1d" },
294 { kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32MI", "[!0r+!1d],!2d" },
295 { kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" },
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700296 { kX86Test64RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64RI", "!0r,!1d" },
297 { kX86Test64MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64MI", "[!0r+!1d],!2d" },
298 { kX86Test64AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64AI", "[!0r+!1r<<!2d+!3d],!4d" },
Dmitry Petrochenko96992e82014-05-20 04:03:46 +0700299
Dave Allison69dfe512014-07-11 17:11:58 +0000300 { kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test32RR", "!0r,!1r" },
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700301 { kX86Test64RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test64RR", "!0r,!1r" },
Chao-ying Fucf818412014-07-24 12:08:28 -0700302 { kX86Test32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test32RM", "!0r,[!1r+!2d]" },
Brian Carlstrom7940e442013-07-12 13:46:57 -0700303
304#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \
305 reg, reg_kind, reg_flags, \
306 mem, mem_kind, mem_flags, \
307 arr, arr_kind, arr_flags, imm, \
308 b_flags, hw_flags, w_flags, \
309 b_format, hw_format, w_format) \
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700310{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #reg, b_format "!0r" }, \
311{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #mem, b_format "[!0r+!1d]" }, \
312{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #arr, b_format "[!0r+!1r<<!2d+!3d]" }, \
313{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #reg, hw_format "!0r" }, \
314{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #mem, hw_format "[!0r+!1d]" }, \
315{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #arr, hw_format "[!0r+!1r<<!2d+!3d]" }, \
316{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #reg, w_format "!0r" }, \
317{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #mem, w_format "[!0r+!1d]" }, \
318{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #arr, w_format "[!0r+!1r<<!2d+!3d]" }, \
319{ kX86 ## opname ## 64 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #reg, w_format "!0r" }, \
320{ kX86 ## opname ## 64 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #mem, w_format "[!0r+!1d]" }, \
321{ kX86 ## opname ## 64 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #arr, w_format "[!0r+!1r<<!2d+!3d]" }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700322
323 UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),
324 UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),
325
Mark Mendell2bf31e62014-01-23 12:13:40 -0800326 UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),
327 UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),
328 UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),
329 UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),
Brian Carlstrom7940e442013-07-12 13:46:57 -0700330#undef UNARY_ENCODING_MAP
331
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700332 { kx86Cdq32Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { 0, 0, 0x99, 0, 0, 0, 0, 0, false }, "Cdq", "" },
333 { kx86Cqo64Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { REX_W, 0, 0x99, 0, 0, 0, 0, 0, false }, "Cqo", "" },
334 { kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0, false }, "Bswap32R", "!0r" },
nikolay serdjukc5e4ce12014-06-10 17:07:10 +0700335 { kX86Bswap64R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { REX_W, 0, 0x0F, 0xC8, 0, 0, 0, 0, false }, "Bswap64R", "!0r" },
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700336 { kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0, false }, "Push32R", "!0r" },
337 { kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0, false }, "Pop32R", "!0r" },
Vladimir Markoa8b4caf2013-10-24 15:08:57 +0100338
Brian Carlstrom7940e442013-07-12 13:46:57 -0700339#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700340{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \
341{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \
342{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700343
Chao-ying Fu021b60f2014-07-09 11:32:31 -0700344// This is a special encoding with r8_form on the second register only
345// for Movzx8 and Movsx8.
346#define EXT_0F_R8_FORM_ENCODING_MAP(opname, prefix, opcode, reg_def) \
347{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, true }, #opname "RR", "!0r,!1r" }, \
348{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \
349{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }
350
Chao-ying Fue0ccdc02014-06-06 17:32:37 -0700351#define EXT_0F_REX_W_ENCODING_MAP(opname, prefix, opcode, reg_def) \
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700352{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \
353{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \
354{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }
Chao-ying Fue0ccdc02014-06-06 17:32:37 -0700355
Mark Mendellfe945782014-05-22 09:52:36 -0400356#define EXT_0F_ENCODING2_MAP(opname, prefix, opcode, opcode2, reg_def) \
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700357{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \
358{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \
359{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }
Mark Mendellfe945782014-05-22 09:52:36 -0400360
Brian Carlstrom7940e442013-07-12 13:46:57 -0700361 EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700362 { kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovsdMR", "[!0r+!1d],!2r" },
363 { kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },
Brian Carlstrom7940e442013-07-12 13:46:57 -0700364
365 EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700366 { kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovssMR", "[!0r+!1d],!2r" },
367 { kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },
Brian Carlstrom7940e442013-07-12 13:46:57 -0700368
369 EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),
370 EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),
Chao-ying Fue0ccdc02014-06-06 17:32:37 -0700371 EXT_0F_REX_W_ENCODING_MAP(Cvtsqi2sd, 0xF2, 0x2A, REG_DEF0),
372 EXT_0F_REX_W_ENCODING_MAP(Cvtsqi2ss, 0xF3, 0x2A, REG_DEF0),
Brian Carlstrom7940e442013-07-12 13:46:57 -0700373 EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),
374 EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),
Chao-ying Fue0ccdc02014-06-06 17:32:37 -0700375 EXT_0F_REX_W_ENCODING_MAP(Cvttsd2sqi, 0xF2, 0x2C, REG_DEF0),
376 EXT_0F_REX_W_ENCODING_MAP(Cvttss2sqi, 0xF3, 0x2C, REG_DEF0),
Brian Carlstrom7940e442013-07-12 13:46:57 -0700377 EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),
378 EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),
Mark Mendell2637f2e2014-04-30 10:10:47 -0400379 EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES|REG_USE0),
380 EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES|REG_USE0),
381 EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES|REG_USE0),
382 EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES|REG_USE0),
Alexei Zavjalov1222c962014-07-16 00:54:13 +0700383 EXT_0F_ENCODING_MAP(Orpd, 0x66, 0x56, REG_DEF0_USE0),
Mark Mendell2637f2e2014-04-30 10:10:47 -0400384 EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0_USE0),
Alexei Zavjalov1222c962014-07-16 00:54:13 +0700385 EXT_0F_ENCODING_MAP(Andpd, 0x66, 0x54, REG_DEF0_USE0),
386 EXT_0F_ENCODING_MAP(Andps, 0x00, 0x54, REG_DEF0_USE0),
387 EXT_0F_ENCODING_MAP(Xorpd, 0x66, 0x57, REG_DEF0_USE0),
Mark Mendell2637f2e2014-04-30 10:10:47 -0400388 EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0_USE0),
389 EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0_USE0),
390 EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0_USE0),
391 EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0_USE0),
392 EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0_USE0),
Brian Carlstrom7940e442013-07-12 13:46:57 -0700393 EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),
394 EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),
Mark Mendell2637f2e2014-04-30 10:10:47 -0400395 EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0_USE0),
396 EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0_USE0),
397 EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0_USE0),
398 EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0_USE0),
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700399 EXT_0F_ENCODING_MAP(Punpcklbw, 0x66, 0x60, REG_DEF0_USE0),
400 EXT_0F_ENCODING_MAP(Punpcklwd, 0x66, 0x61, REG_DEF0_USE0),
Mark Mendell2637f2e2014-04-30 10:10:47 -0400401 EXT_0F_ENCODING_MAP(Punpckldq, 0x66, 0x62, REG_DEF0_USE0),
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700402 EXT_0F_ENCODING_MAP(Punpcklqdq, 0x66, 0x6C, REG_DEF0_USE0),
Mark Mendellfe945782014-05-22 09:52:36 -0400403 EXT_0F_ENCODING_MAP(Sqrtsd, 0xF2, 0x51, REG_DEF0_USE0),
404 EXT_0F_ENCODING2_MAP(Pmulld, 0x66, 0x38, 0x40, REG_DEF0_USE0),
405 EXT_0F_ENCODING_MAP(Pmullw, 0x66, 0xD5, REG_DEF0_USE0),
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700406 EXT_0F_ENCODING_MAP(Pmuludq, 0x66, 0xF4, REG_DEF0_USE0),
Mark Mendellfe945782014-05-22 09:52:36 -0400407 EXT_0F_ENCODING_MAP(Mulps, 0x00, 0x59, REG_DEF0_USE0),
408 EXT_0F_ENCODING_MAP(Mulpd, 0x66, 0x59, REG_DEF0_USE0),
409 EXT_0F_ENCODING_MAP(Paddb, 0x66, 0xFC, REG_DEF0_USE0),
410 EXT_0F_ENCODING_MAP(Paddw, 0x66, 0xFD, REG_DEF0_USE0),
411 EXT_0F_ENCODING_MAP(Paddd, 0x66, 0xFE, REG_DEF0_USE0),
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700412 EXT_0F_ENCODING_MAP(Paddq, 0x66, 0xD4, REG_DEF0_USE0),
413 EXT_0F_ENCODING_MAP(Psadbw, 0x66, 0xF6, REG_DEF0_USE0),
Mark Mendellfe945782014-05-22 09:52:36 -0400414 EXT_0F_ENCODING_MAP(Addps, 0x00, 0x58, REG_DEF0_USE0),
Chao-ying Fuc4013ea2015-04-22 10:51:21 -0700415 EXT_0F_ENCODING_MAP(Addpd, 0x66, 0x58, REG_DEF0_USE0),
Mark Mendellfe945782014-05-22 09:52:36 -0400416 EXT_0F_ENCODING_MAP(Psubb, 0x66, 0xF8, REG_DEF0_USE0),
417 EXT_0F_ENCODING_MAP(Psubw, 0x66, 0xF9, REG_DEF0_USE0),
418 EXT_0F_ENCODING_MAP(Psubd, 0x66, 0xFA, REG_DEF0_USE0),
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700419 EXT_0F_ENCODING_MAP(Psubq, 0x66, 0xFB, REG_DEF0_USE0),
Mark Mendellfe945782014-05-22 09:52:36 -0400420 EXT_0F_ENCODING_MAP(Subps, 0x00, 0x5C, REG_DEF0_USE0),
421 EXT_0F_ENCODING_MAP(Subpd, 0x66, 0x5C, REG_DEF0_USE0),
422 EXT_0F_ENCODING_MAP(Pand, 0x66, 0xDB, REG_DEF0_USE0),
423 EXT_0F_ENCODING_MAP(Por, 0x66, 0xEB, REG_DEF0_USE0),
424 EXT_0F_ENCODING_MAP(Pxor, 0x66, 0xEF, REG_DEF0_USE0),
425 EXT_0F_ENCODING2_MAP(Phaddw, 0x66, 0x38, 0x01, REG_DEF0_USE0),
426 EXT_0F_ENCODING2_MAP(Phaddd, 0x66, 0x38, 0x02, REG_DEF0_USE0),
Olivier Comefb0fecf2014-06-20 11:46:16 +0200427 EXT_0F_ENCODING_MAP(Haddpd, 0x66, 0x7C, REG_DEF0_USE0),
428 EXT_0F_ENCODING_MAP(Haddps, 0xF2, 0x7C, REG_DEF0_USE0),
Brian Carlstrom7940e442013-07-12 13:46:57 -0700429
Serguei Katkov35690632014-07-16 15:52:59 +0700430 { kX86PextrbRRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x3A, 0x14, 0, 0, 1, false }, "PextbRRI", "!0r,!1r,!2d" },
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700431 { kX86PextrwRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0xC5, 0x00, 0, 0, 1, false }, "PextwRRI", "!0r,!1r,!2d" },
Serguei Katkov35690632014-07-16 15:52:59 +0700432 { kX86PextrdRRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "PextdRRI", "!0r,!1r,!2d" },
Dmitry Petrochenkof18b92f2014-11-14 17:32:56 +0600433 { kX86PextrbMRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_STORE, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "PextrbMRI", "[!0r+!1d],!2r,!3d" },
nikolay serdjuke0705f52015-04-27 17:52:57 +0600434 { kX86PextrwMRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_STORE, { 0x66, 0, 0x0F, 0x3A, 0x15, 0, 0, 1, false }, "PextrwMRI", "[!0r+!1d],!2r,!3d" },
Dmitry Petrochenkof18b92f2014-11-14 17:32:56 +0600435 { kX86PextrdMRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_STORE, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "PextrdMRI", "[!0r+!1d],!2r,!3d" },
Mark Mendellfe945782014-05-22 09:52:36 -0400436
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700437 { kX86PshuflwRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0xF2, 0, 0x0F, 0x70, 0, 0, 0, 1, false }, "PshuflwRRI", "!0r,!1r,!2d" },
438 { kX86PshufdRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x70, 0, 0, 0, 1, false }, "PshuffRRI", "!0r,!1r,!2d" },
Mark Mendellfe945782014-05-22 09:52:36 -0400439
Dmitry Petrochenkof18b92f2014-11-14 17:32:56 +0600440 { kX86ShufpsRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE0 | REG_USE1, { 0x00, 0, 0x0F, 0xC6, 0, 0, 0, 1, false }, "ShufpsRRI", "!0r,!1r,!2d" },
441 { kX86ShufpdRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE0 | REG_USE1, { 0x66, 0, 0x0F, 0xC6, 0, 0, 0, 1, false }, "ShufpdRRI", "!0r,!1r,!2d" },
Olivier Comefb0fecf2014-06-20 11:46:16 +0200442
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700443 { kX86PsrawRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 4, 0, 1, false }, "PsrawRI", "!0r,!1d" },
444 { kX86PsradRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 4, 0, 1, false }, "PsradRI", "!0r,!1d" },
445 { kX86PsrlwRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 2, 0, 1, false }, "PsrlwRI", "!0r,!1d" },
446 { kX86PsrldRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 2, 0, 1, false }, "PsrldRI", "!0r,!1d" },
447 { kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1, false }, "PsrlqRI", "!0r,!1d" },
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700448 { kX86PsrldqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 3, 0, 1, false }, "PsrldqRI", "!0r,!1d" },
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700449 { kX86PsllwRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 6, 0, 1, false }, "PsllwRI", "!0r,!1d" },
450 { kX86PslldRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 6, 0, 1, false }, "PslldRI", "!0r,!1d" },
451 { kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1, false }, "PsllqRI", "!0r,!1d" },
Razvan A Lupusoru614c2b42014-01-28 17:05:21 -0800452
Haitao Fenga870bc52014-09-09 15:52:34 +0800453 { kX86Fild32M, kMem, IS_LOAD | IS_BINARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDB, 0x00, 0, 0, 0, 0, false }, "Fild32M", "[!0r,!1d]" },
454 { kX86Fild64M, kMem, IS_LOAD | IS_BINARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDF, 0x00, 0, 5, 0, 0, false }, "Fild64M", "[!0r,!1d]" },
455 { kX86Fld32M, kMem, IS_LOAD | IS_BINARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 0, 0, 0, false }, "Fld32M", "[!0r,!1d]" },
456 { kX86Fld64M, kMem, IS_LOAD | IS_BINARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 0, 0, 0, false }, "Fld64M", "[!0r,!1d]" },
457 { kX86Fstp32M, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 3, 0, 0, false }, "Fstps32M", "[!0r,!1d]" },
458 { kX86Fstp64M, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0, false }, "Fstpd64M", "[!0r,!1d]" },
459 { kX86Fst32M, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 2, 0, 0, false }, "Fsts32M", "[!0r,!1d]" },
460 { kX86Fst64M, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 2, 0, 0, false }, "Fstd64M", "[!0r,!1d]" },
Alexei Zavjalovbd3682e2014-06-12 03:08:01 +0700461 { kX86Fprem, kNullary, NO_OPERAND | USE_FP_STACK, { 0xD9, 0, 0xF8, 0, 0, 0, 0, 0, false }, "Fprem64", "" },
462 { kX86Fucompp, kNullary, NO_OPERAND | USE_FP_STACK, { 0xDA, 0, 0xE9, 0, 0, 0, 0, 0, false }, "Fucompp", "" },
Mark Mendell01a50d62014-07-06 12:24:40 -0400463 { kX86Fstsw16R, kNullary, NO_OPERAND | REG_DEFA | USE_FP_STACK, { 0x9B, 0xDF, 0xE0, 0, 0, 0, 0, 0, false }, "Fstsw16R", "ax" },
Brian Carlstrom7940e442013-07-12 13:46:57 -0700464
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700465 EXT_0F_ENCODING_MAP(Movdqa, 0x66, 0x6F, REG_DEF0),
466 { kX86MovdqaMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x6F, 0, 0, 0, 0, false }, "MovdqaMR", "[!0r+!1d],!2r" },
467 { kX86MovdqaAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x6F, 0, 0, 0, 0, false }, "MovdqaAR", "[!0r+!1r<<!2d+!3d],!4r" },
Mark Mendelld65c51a2014-04-29 16:55:20 -0400468
469
Razvan A Lupusoru2c498d12014-01-29 16:02:57 -0800470 EXT_0F_ENCODING_MAP(Movups, 0x0, 0x10, REG_DEF0),
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700471 { kX86MovupsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovupsMR", "[!0r+!1d],!2r" },
472 { kX86MovupsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovupsAR", "[!0r+!1r<<!2d+!3d],!4r" },
Razvan A Lupusoru2c498d12014-01-29 16:02:57 -0800473
474 EXT_0F_ENCODING_MAP(Movaps, 0x0, 0x28, REG_DEF0),
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700475 { kX86MovapsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0, false }, "MovapsMR", "[!0r+!1d],!2r" },
476 { kX86MovapsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0, false }, "MovapsAR", "[!0r+!1r<<!2d+!3d],!4r" },
Razvan A Lupusoru2c498d12014-01-29 16:02:57 -0800477
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700478 { kX86MovlpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0, false }, "MovlpsRM", "!0r,[!1r+!2d]" },
479 { kX86MovlpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0, false }, "MovlpsRA", "!0r,[!1r+!2r<<!3d+!4d]" },
480 { kX86MovlpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0, false }, "MovlpsMR", "[!0r+!1d],!2r" },
481 { kX86MovlpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0, false }, "MovlpsAR", "[!0r+!1r<<!2d+!3d],!4r" },
Razvan A Lupusoru2c498d12014-01-29 16:02:57 -0800482
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700483 { kX86MovhpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0, false }, "MovhpsRM", "!0r,[!1r+!2d]" },
484 { kX86MovhpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0, false }, "MovhpsRA", "!0r,[!1r+!2r<<!3d+!4d]" },
485 { kX86MovhpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0, false }, "MovhpsMR", "[!0r+!1d],!2r" },
486 { kX86MovhpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0, false }, "MovhpsAR", "[!0r+!1r<<!2d+!3d],!4r" },
Razvan A Lupusoru2c498d12014-01-29 16:02:57 -0800487
Brian Carlstrom7940e442013-07-12 13:46:57 -0700488 EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),
Chao-ying Fue0ccdc02014-06-06 17:32:37 -0700489 EXT_0F_REX_W_ENCODING_MAP(Movqxr, 0x66, 0x6E, REG_DEF0),
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700490 { kX86MovqrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE1, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxRR", "!0r,!1r" },
491 { kX86MovqrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxMR", "[!0r+!1d],!2r" },
492 { kX86MovqrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxAR", "[!0r+!1r<<!2d+!3d],!4r" },
Chao-ying Fue0ccdc02014-06-06 17:32:37 -0700493
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700494 { kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxRR", "!0r,!1r" },
495 { kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxMR", "[!0r+!1d],!2r" },
496 { kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },
Brian Carlstrom7940e442013-07-12 13:46:57 -0700497
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700498 { kX86MovsxdRR, kRegReg, IS_BINARY_OP | REG_DEF0 | REG_USE1, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRR", "!0r,!1r" },
499 { kX86MovsxdRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRM", "!0r,[!1r+!2d]" },
500 { kX86MovsxdRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE12, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRA", "!0r,[!1r+!2r<<!3d+!4d]" },
Chao-ying Fue0ccdc02014-06-06 17:32:37 -0700501
Mark Mendell2bc47702014-07-31 14:36:54 -0400502 { kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, true }, "Set8R", "!1c !0r" },
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700503 { kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, false }, "Set8M", "!2c [!0r+!1d]" },
504 { kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, false }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },
Brian Carlstrom7940e442013-07-12 13:46:57 -0700505
506 // TODO: load/store?
507 // Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.
Jean Christophe Beylerb5bce7c2014-07-25 12:32:18 -0700508 { kX86Lfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 5, 0, 0, false }, "Lfence", "" },
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700509 { kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0, false }, "Mfence", "" },
Jean Christophe Beylerb5bce7c2014-07-25 12:32:18 -0700510 { kX86Sfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 7, 0, 0, false }, "Sfence", "" },
Mark P Mendell17077d82015-12-16 19:15:59 +0000511 { kX86LockAdd32MI8, kMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0xF0, 0, 0x83, 0x0, 0x0, 0, 0, 1, false }, "LockAdd32MI8", "[!0r+!1d],!2d" },
Brian Carlstrom7940e442013-07-12 13:46:57 -0700512
Mark Mendell2637f2e2014-04-30 10:10:47 -0400513 EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES),
514 EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES),
Chao-ying Fue0ccdc02014-06-06 17:32:37 -0700515 EXT_0F_ENCODING_MAP(Imul64, REX_W, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES),
Brian Carlstrom7940e442013-07-12 13:46:57 -0700516
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700517 { kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "!0r,!1r" },
518 { kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "[!0r+!1d],!2r" },
519 { kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },
520 { kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1d],!2r" },
521 { kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },
nikolay serdjukc5e4ce12014-06-10 17:07:10 +0700522 { kX86LockCmpxchg64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, REX_W, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700523 { kX86LockCmpxchg64M, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0, false }, "Lock Cmpxchg8b", "[!0r+!1d]" },
524 { kX86LockCmpxchg64A, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0, false }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" },
525 { kX86XchgMR, kMemReg, IS_STORE | IS_LOAD | IS_TERTIARY_OP | REG_DEF2 | REG_USE02, { 0, 0, 0x87, 0, 0, 0, 0, 0, false }, "Xchg", "[!0r+!1d],!2r" },
Brian Carlstrom7940e442013-07-12 13:46:57 -0700526
Chao-ying Fu021b60f2014-07-09 11:32:31 -0700527 EXT_0F_R8_FORM_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),
Brian Carlstrom7940e442013-07-12 13:46:57 -0700528 EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),
Chao-ying Fu021b60f2014-07-09 11:32:31 -0700529 EXT_0F_R8_FORM_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),
Brian Carlstrom7940e442013-07-12 13:46:57 -0700530 EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),
Serguei Katkov94f3eb02014-06-24 13:23:17 +0700531 EXT_0F_ENCODING_MAP(Movzx8q, REX_W, 0xB6, REG_DEF0),
532 EXT_0F_ENCODING_MAP(Movzx16q, REX_W, 0xB7, REG_DEF0),
533 EXT_0F_ENCODING_MAP(Movsx8q, REX, 0xBE, REG_DEF0),
534 EXT_0F_ENCODING_MAP(Movsx16q, REX_W, 0xBF, REG_DEF0),
Brian Carlstrom7940e442013-07-12 13:46:57 -0700535#undef EXT_0F_ENCODING_MAP
536
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700537 { kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0, false }, "Jcc8", "!1c !0t" },
538 { kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0, false }, "Jcc32", "!1c !0t" },
539 { kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0, false }, "Jmp8", "!0t" },
540 { kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0, false }, "Jmp32", "!0t" },
541 { kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0, false }, "JmpR", "!0r" },
542 { kX86Jecxz8, kJmp, NO_OPERAND | IS_BRANCH | NEEDS_FIXUP | REG_USEC, { 0, 0, 0xE3, 0, 0, 0, 0, 0, false }, "Jecxz", "!0t" },
543 { kX86JmpT, kJmp, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 4, 0, 0, false }, "JmpT", "fs:[!0d]" },
544 { kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0, false }, "CallR", "!0r" },
545 { kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallM", "[!0r+!1d]" },
546 { kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallA", "[!0r+!1r<<!2d+!3d]" },
547 { kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallT", "fs:[!0d]" },
548 { kX86CallI, kCall, IS_UNARY_OP | IS_BRANCH, { 0, 0, 0xE8, 0, 0, 0, 0, 4, false }, "CallI", "!0d" },
549 { kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0, false }, "Ret", "" },
Brian Carlstrom7940e442013-07-12 13:46:57 -0700550
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700551 { kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },
Haitao Fenge70f1792014-08-09 08:31:02 +0800552 { kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4, false }, "PcRelAdr", "!0r,!1p" },
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700553 { kX86RepneScasw, kNullary, NO_OPERAND | REG_USEA | REG_USEC | SETS_CCODES, { 0x66, 0xF2, 0xAF, 0, 0, 0, 0, 0, false }, "RepNE ScasW", "" },
Brian Carlstrom7940e442013-07-12 13:46:57 -0700554};
555
Ian Rogers6a3c1fc2014-10-31 00:33:20 -0700556std::ostream& operator<<(std::ostream& os, const X86OpCode& rhs) {
557 os << X86Mir2Lir::EncodingMap[rhs].name;
558 return os;
559}
560
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700561static bool NeedsRex(int32_t raw_reg) {
Mark Mendell27dee8b2014-12-01 19:06:12 -0500562 return raw_reg != kRIPReg && RegStorage::RegNum(raw_reg) > 7;
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700563}
564
565static uint8_t LowRegisterBits(int32_t raw_reg) {
566 uint8_t low_reg = RegStorage::RegNum(raw_reg) & kRegNumMask32; // 3 bits
567 DCHECK_LT(low_reg, 8);
568 return low_reg;
569}
570
Ian Rogers5aa6e042014-06-13 16:38:24 -0700571static bool HasModrm(const X86EncodingMap* entry) {
572 switch (entry->kind) {
573 case kNullary: return false;
574 case kRegOpcode: return false;
575 default: return true;
576 }
577}
578
579static bool HasSib(const X86EncodingMap* entry) {
580 switch (entry->kind) {
581 case kArray: return true;
582 case kArrayReg: return true;
583 case kRegArray: return true;
584 case kArrayImm: return true;
585 case kRegArrayImm: return true;
586 case kShiftArrayImm: return true;
587 case kShiftArrayCl: return true;
588 case kArrayCond: return true;
589 case kCall:
590 switch (entry->opcode) {
591 case kX86CallA: return true;
592 default: return false;
593 }
Ian Rogers07140832014-09-30 15:43:59 -0700594 case kPcRel:
Ian Rogers5aa6e042014-06-13 16:38:24 -0700595 switch (entry->opcode) {
596 case kX86PcRelLoadRA: return true;
597 default: return false;
598 }
599 default: return false;
600 }
601}
602
603static bool ModrmIsRegReg(const X86EncodingMap* entry) {
604 switch (entry->kind) {
605 // There is no modrm for this kind of instruction, therefore the reg doesn't form part of the
606 // modrm:
607 case kNullary: return true;
608 case kRegOpcode: return true;
609 case kMovRegImm: return true;
610 // Regular modrm value of 3 cases, when there is one register the other register holds an
611 // opcode so the base register is special.
612 case kReg: return true;
613 case kRegReg: return true;
614 case kRegRegStore: return true;
615 case kRegImm: return true;
616 case kRegRegImm: return true;
617 case kRegRegImmStore: return true;
618 case kShiftRegImm: return true;
619 case kShiftRegCl: return true;
620 case kRegCond: return true;
621 case kRegRegCond: return true;
Yixin Shouf40f8902014-08-14 14:10:32 -0400622 case kShiftRegRegCl: return true;
Ian Rogers5aa6e042014-06-13 16:38:24 -0700623 case kJmp:
624 switch (entry->opcode) {
625 case kX86JmpR: return true;
626 default: return false;
627 }
628 case kCall:
629 switch (entry->opcode) {
630 case kX86CallR: return true;
631 default: return false;
632 }
633 default: return false;
634 }
635}
636
Chao-ying Fu021b60f2014-07-09 11:32:31 -0700637static bool IsByteSecondOperand(const X86EncodingMap* entry) {
638 return StartsWith(entry->name, "Movzx8") || StartsWith(entry->name, "Movsx8");
639}
640
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700641size_t X86Mir2Lir::ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index,
Ian Rogers5aa6e042014-06-13 16:38:24 -0700642 int32_t raw_base, int32_t displacement) {
643 bool has_modrm = HasModrm(entry);
644 bool has_sib = HasSib(entry);
645 bool r8_form = entry->skeleton.r8_form;
646 bool modrm_is_reg_reg = ModrmIsRegReg(entry);
647 if (has_sib) {
648 DCHECK(!modrm_is_reg_reg);
649 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700650 size_t size = 0;
651 if (entry->skeleton.prefix1 > 0) {
652 ++size;
653 if (entry->skeleton.prefix2 > 0) {
654 ++size;
655 }
656 }
Elena Sayapinadd644502014-07-01 18:39:52 +0700657 if (cu_->target64 || kIsDebugBuild) {
Ian Rogers5aa6e042014-06-13 16:38:24 -0700658 bool registers_need_rex_prefix = NeedsRex(raw_reg) || NeedsRex(raw_index) || NeedsRex(raw_base);
659 if (r8_form) {
660 // Do we need an empty REX prefix to normalize byte registers?
Chao-ying Fu021b60f2014-07-09 11:32:31 -0700661 registers_need_rex_prefix = registers_need_rex_prefix ||
662 (RegStorage::RegNum(raw_reg) >= 4 && !IsByteSecondOperand(entry));
Ian Rogers5aa6e042014-06-13 16:38:24 -0700663 registers_need_rex_prefix = registers_need_rex_prefix ||
664 (modrm_is_reg_reg && (RegStorage::RegNum(raw_base) >= 4));
665 }
666 if (registers_need_rex_prefix) {
Elena Sayapinadd644502014-07-01 18:39:52 +0700667 DCHECK(cu_->target64) << "Attempt to use a 64-bit only addressable register "
Ian Rogers5aa6e042014-06-13 16:38:24 -0700668 << RegStorage::RegNum(raw_reg) << " with instruction " << entry->name;
Serguei Katkov94f3eb02014-06-24 13:23:17 +0700669 if (entry->skeleton.prefix1 != REX_W && entry->skeleton.prefix2 != REX_W
670 && entry->skeleton.prefix1 != REX && entry->skeleton.prefix2 != REX) {
Ian Rogers5aa6e042014-06-13 16:38:24 -0700671 ++size; // rex
672 }
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700673 }
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +0700674 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700675 ++size; // opcode
676 if (entry->skeleton.opcode == 0x0F) {
677 ++size;
678 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {
679 ++size;
680 }
681 }
Ian Rogers5aa6e042014-06-13 16:38:24 -0700682 if (has_modrm) {
683 ++size; // modrm
Brian Carlstrom7940e442013-07-12 13:46:57 -0700684 }
Ian Rogers5aa6e042014-06-13 16:38:24 -0700685 if (!modrm_is_reg_reg) {
Ian Rogersb28c1c02014-11-08 11:21:21 -0800686 if (has_sib || (LowRegisterBits(raw_base) == rs_rX86_SP_32.GetRegNum())
Elena Sayapinadd644502014-07-01 18:39:52 +0700687 || (cu_->target64 && entry->skeleton.prefix1 == THREAD_PREFIX)) {
Ian Rogers5aa6e042014-06-13 16:38:24 -0700688 // SP requires a SIB byte.
689 // GS access also needs a SIB byte for absolute adressing in 64-bit mode.
690 ++size;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700691 }
Ian Rogers5aa6e042014-06-13 16:38:24 -0700692 if (displacement != 0 || LowRegisterBits(raw_base) == rs_rBP.GetRegNum()) {
693 // BP requires an explicit displacement, even when it's 0.
Haitao Fenga870bc52014-09-09 15:52:34 +0800694 if (entry->opcode != kX86Lea32RA && entry->opcode != kX86Lea64RA &&
695 entry->opcode != kX86Lea32RM && entry->opcode != kX86Lea64RM) {
Ian Rogers5aa6e042014-06-13 16:38:24 -0700696 DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), UINT64_C(0)) << entry->name;
697 }
Mark Mendell27dee8b2014-12-01 19:06:12 -0500698 if (raw_base == kRIPReg) {
699 DCHECK(cu_->target64) <<
700 "Attempt to use a 64-bit RIP adressing with instruction " << entry->name;
701 size += 4;
702 } else {
703 size += IS_SIMM8(displacement) ? 1 : 4;
704 }
Ian Rogers5aa6e042014-06-13 16:38:24 -0700705 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700706 }
707 size += entry->skeleton.immediate_bytes;
708 return size;
709}
710
Ian Rogers5aa6e042014-06-13 16:38:24 -0700711size_t X86Mir2Lir::GetInsnSize(LIR* lir) {
buzbee409fe942013-10-11 10:49:56 -0700712 DCHECK(!IsPseudoLirOp(lir->opcode));
Brian Carlstrom7940e442013-07-12 13:46:57 -0700713 const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode];
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700714 DCHECK_EQ(entry->opcode, lir->opcode) << entry->name;
Ian Rogers5aa6e042014-06-13 16:38:24 -0700715
Brian Carlstrom7940e442013-07-12 13:46:57 -0700716 switch (entry->kind) {
717 case kData:
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700718 return 4; // 4 bytes of data.
Brian Carlstrom7940e442013-07-12 13:46:57 -0700719 case kNop:
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700720 return lir->operands[0]; // Length of nop is sole operand.
Brian Carlstrom7940e442013-07-12 13:46:57 -0700721 case kNullary:
Ian Rogers5aa6e042014-06-13 16:38:24 -0700722 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0);
Vladimir Markoa8b4caf2013-10-24 15:08:57 +0100723 case kRegOpcode: // lir operands - 0: reg
Ian Rogers5aa6e042014-06-13 16:38:24 -0700724 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700725 case kReg: // lir operands - 0: reg
Ian Rogers5aa6e042014-06-13 16:38:24 -0700726 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700727 case kMem: // lir operands - 0: base, 1: disp
Ian Rogers5aa6e042014-06-13 16:38:24 -0700728 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700729 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp
Ian Rogers5aa6e042014-06-13 16:38:24 -0700730 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700731 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg
Ian Rogers5aa6e042014-06-13 16:38:24 -0700732 return ComputeSize(entry, lir->operands[2], NO_REG, lir->operands[0], lir->operands[1]);
Mark Mendell2637f2e2014-04-30 10:10:47 -0400733 case kMemRegImm: // lir operands - 0: base, 1: disp, 2: reg 3: immediate
Ian Rogers5aa6e042014-06-13 16:38:24 -0700734 return ComputeSize(entry, lir->operands[2], NO_REG, lir->operands[0], lir->operands[1]);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700735 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700736 return ComputeSize(entry, lir->operands[4], lir->operands[1], lir->operands[0],
Ian Rogers5aa6e042014-06-13 16:38:24 -0700737 lir->operands[3]);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700738 case kThreadReg: // lir operands - 0: disp, 1: reg
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700739 // Thread displacement size is always 32bit.
Ian Rogers5aa6e042014-06-13 16:38:24 -0700740 return ComputeSize(entry, lir->operands[1], NO_REG, NO_REG, 0x12345678);
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +0700741 case kRegReg: // lir operands - 0: reg1, 1: reg2
Ian Rogers5aa6e042014-06-13 16:38:24 -0700742 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], 0);
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +0700743 case kRegRegStore: // lir operands - 0: reg2, 1: reg1
Ian Rogers5aa6e042014-06-13 16:38:24 -0700744 return ComputeSize(entry, lir->operands[1], NO_REG, lir->operands[0], 0);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700745 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp
Ian Rogers5aa6e042014-06-13 16:38:24 -0700746 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], lir->operands[2]);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700747 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700748 return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1],
Ian Rogers5aa6e042014-06-13 16:38:24 -0700749 lir->operands[4]);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700750 case kRegThread: // lir operands - 0: reg, 1: disp
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700751 // Thread displacement size is always 32bit.
Ian Rogers5aa6e042014-06-13 16:38:24 -0700752 return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0x12345678);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700753 case kRegImm: { // lir operands - 0: reg, 1: immediate
Ian Rogers5aa6e042014-06-13 16:38:24 -0700754 size_t size = ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0);
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700755 // AX opcodes don't require the modrm byte.
Brian Carlstrom7940e442013-07-12 13:46:57 -0700756 if (entry->skeleton.ax_opcode == 0) {
757 return size;
758 } else {
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700759 return size - (RegStorage::RegNum(lir->operands[0]) == rs_rAX.GetRegNum() ? 1 : 0);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700760 }
761 }
762 case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate
Ian Rogers5aa6e042014-06-13 16:38:24 -0700763 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700764 case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate
Ian Rogers5aa6e042014-06-13 16:38:24 -0700765 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700766 case kThreadImm: // lir operands - 0: disp, 1: imm
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700767 // Thread displacement size is always 32bit.
Ian Rogers5aa6e042014-06-13 16:38:24 -0700768 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0x12345678);
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700769 case kRegRegImm: // lir operands - 0: reg1, 1: reg2, 2: imm
770 // Note: RegRegImm form passes reg2 as index but encodes it using base.
Ian Rogers5aa6e042014-06-13 16:38:24 -0700771 return ComputeSize(entry, lir->operands[0], lir->operands[1], NO_REG, 0);
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700772 case kRegRegImmStore: // lir operands - 0: reg2, 1: reg1, 2: imm
773 // Note: RegRegImmStore form passes reg1 as index but encodes it using base.
Ian Rogers5aa6e042014-06-13 16:38:24 -0700774 return ComputeSize(entry, lir->operands[1], lir->operands[0], NO_REG, 0);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700775 case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm
Ian Rogers5aa6e042014-06-13 16:38:24 -0700776 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], lir->operands[2]);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700777 case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700778 return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1],
Ian Rogers5aa6e042014-06-13 16:38:24 -0700779 lir->operands[4]);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700780 case kMovRegImm: // lir operands - 0: reg, 1: immediate
Yixin Shou5192cbb2014-07-01 13:48:17 -0400781 case kMovRegQuadImm:
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700782 return ((entry->skeleton.prefix1 != 0 || NeedsRex(lir->operands[0])) ? 1 : 0) + 1 +
783 entry->skeleton.immediate_bytes;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700784 case kShiftRegImm: // lir operands - 0: reg, 1: immediate
785 // Shift by immediate one has a shorter opcode.
Ian Rogers5aa6e042014-06-13 16:38:24 -0700786 return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0) -
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700787 (lir->operands[1] == 1 ? 1 : 0);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700788 case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate
789 // Shift by immediate one has a shorter opcode.
Ian Rogers5aa6e042014-06-13 16:38:24 -0700790 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]) -
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700791 (lir->operands[2] == 1 ? 1 : 0);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700792 case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate
793 // Shift by immediate one has a shorter opcode.
Ian Rogers5aa6e042014-06-13 16:38:24 -0700794 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]) -
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700795 (lir->operands[4] == 1 ? 1 : 0);
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +0700796 case kShiftRegCl: // lir operands - 0: reg, 1: cl
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700797 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[1]));
798 // Note: ShiftRegCl form passes reg as reg but encodes it using base.
Ian Rogers5aa6e042014-06-13 16:38:24 -0700799 return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700800 case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700801 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[2]));
Ian Rogers5aa6e042014-06-13 16:38:24 -0700802 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]);
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700803 case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cl
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700804 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[4]));
805 return ComputeSize(entry, lir->operands[4], lir->operands[1], lir->operands[0],
Ian Rogers5aa6e042014-06-13 16:38:24 -0700806 lir->operands[3]);
Yixin Shouf40f8902014-08-14 14:10:32 -0400807 case kShiftRegRegCl: // lir operands - 0: reg1, 1: reg2, 2: cl
808 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[2]));
809 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], 0);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700810 case kRegCond: // lir operands - 0: reg, 1: cond
Ian Rogers5aa6e042014-06-13 16:38:24 -0700811 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700812 case kMemCond: // lir operands - 0: base, 1: disp, 2: cond
Ian Rogers5aa6e042014-06-13 16:38:24 -0700813 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700814 case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700815 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -0700816 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]);
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700817 case kRegRegCond: // lir operands - 0: reg1, 1: reg2, 2: cond
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700818 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -0700819 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], 0);
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700820 case kRegMemCond: // lir operands - 0: reg, 1: base, 2: disp, 3:cond
821 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -0700822 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], lir->operands[2]);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700823 case kJcc:
824 if (lir->opcode == kX86Jcc8) {
825 return 2; // opcode + rel8
826 } else {
827 DCHECK(lir->opcode == kX86Jcc32);
828 return 6; // 2 byte opcode + rel32
829 }
830 case kJmp:
Mark Mendell4028a6c2014-02-19 20:06:20 -0800831 if (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jecxz8) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700832 return 2; // opcode + rel8
833 } else if (lir->opcode == kX86Jmp32) {
834 return 5; // opcode + rel32
Brian Carlstrom60d7a652014-03-13 18:10:08 -0700835 } else if (lir->opcode == kX86JmpT) {
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700836 // Thread displacement size is always 32bit.
Ian Rogers5aa6e042014-06-13 16:38:24 -0700837 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0x12345678);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700838 } else {
839 DCHECK(lir->opcode == kX86JmpR);
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +0700840 if (NeedsRex(lir->operands[0])) {
841 return 3; // REX.B + opcode + modrm
842 } else {
843 return 2; // opcode + modrm
844 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700845 }
846 case kCall:
847 switch (lir->opcode) {
Mark Mendell55d0eac2014-02-06 11:02:52 -0800848 case kX86CallI: return 5; // opcode 0:disp
Brian Carlstrom7940e442013-07-12 13:46:57 -0700849 case kX86CallR: return 2; // opcode modrm
850 case kX86CallM: // lir operands - 0: base, 1: disp
Ian Rogers5aa6e042014-06-13 16:38:24 -0700851 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700852 case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp
Ian Rogers5aa6e042014-06-13 16:38:24 -0700853 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700854 case kX86CallT: // lir operands - 0: disp
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700855 // Thread displacement size is always 32bit.
Ian Rogers5aa6e042014-06-13 16:38:24 -0700856 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0x12345678);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700857 default:
858 break;
859 }
860 break;
861 case kPcRel:
862 if (entry->opcode == kX86PcRelLoadRA) {
863 // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700864 // Force the displacement size to 32bit, it will hold a computed offset later.
865 return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1],
Ian Rogers5aa6e042014-06-13 16:38:24 -0700866 0x12345678);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700867 } else {
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700868 DCHECK_EQ(entry->opcode, kX86PcRelAdr);
Brian Carlstrom7934ac22013-07-26 10:54:15 -0700869 return 5; // opcode with reg + 4 byte immediate
Brian Carlstrom7940e442013-07-12 13:46:57 -0700870 }
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700871 case kUnimplemented:
Brian Carlstrom7940e442013-07-12 13:46:57 -0700872 break;
873 }
874 UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;
875 return 0;
876}
877
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700878static uint8_t ModrmForDisp(int base, int disp) {
879 // BP requires an explicit disp, so do not omit it in the 0 case
880 if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) {
881 return 0;
882 } else if (IS_SIMM8(disp)) {
883 return 1;
884 } else {
885 return 2;
886 }
887}
888
889void X86Mir2Lir::CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg) {
890 if (kIsDebugBuild) {
891 // Sanity check r8_form is correctly specified.
892 if (entry->skeleton.r8_form) {
893 CHECK(strchr(entry->name, '8') != nullptr) << entry->name;
894 } else {
895 if (entry->skeleton.immediate_bytes != 1) { // Ignore ...I8 instructions.
Serguei Katkov1c557032014-06-23 13:23:38 +0700896 if (!StartsWith(entry->name, "Movzx8") && !StartsWith(entry->name, "Movsx8")
897 && !StartsWith(entry->name, "Movzx8q") && !StartsWith(entry->name, "Movsx8q")) {
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700898 CHECK(strchr(entry->name, '8') == nullptr) << entry->name;
899 }
900 }
901 }
902 if (RegStorage::RegNum(raw_reg) >= 4) {
903 // ah, bh, ch and dh are not valid registers in 32-bit.
Elena Sayapinadd644502014-07-01 18:39:52 +0700904 CHECK(cu_->target64 || !entry->skeleton.r8_form)
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700905 << "Invalid register " << static_cast<int>(RegStorage::RegNum(raw_reg))
906 << " for instruction " << entry->name << " in "
907 << PrettyMethod(cu_->method_idx, *cu_->dex_file);
908 }
909 }
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +0700910}
911
912void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry,
Ian Rogers5aa6e042014-06-13 16:38:24 -0700913 int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b) {
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +0700914 // REX.WRXB
915 // W - 64-bit operand
916 // R - MODRM.reg
917 // X - SIB.index
918 // B - MODRM.rm/SIB.base
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +0700919 bool w = (entry->skeleton.prefix1 == REX_W) || (entry->skeleton.prefix2 == REX_W);
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700920 bool r = NeedsRex(raw_reg_r);
921 bool x = NeedsRex(raw_reg_x);
922 bool b = NeedsRex(raw_reg_b);
Ian Rogers5aa6e042014-06-13 16:38:24 -0700923 bool r8_form = entry->skeleton.r8_form;
924 bool modrm_is_reg_reg = ModrmIsRegReg(entry);
925
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700926 uint8_t rex = 0;
Chao-ying Fu7e399fd2014-06-10 18:11:11 -0700927 if (r8_form) {
928 // Do we need an empty REX prefix to normalize byte register addressing?
Chao-ying Fu021b60f2014-07-09 11:32:31 -0700929 if (RegStorage::RegNum(raw_reg_r) >= 4 && !IsByteSecondOperand(entry)) {
Razvan A Lupusoruae9f3e62014-09-23 14:54:32 -0700930 rex |= REX; // REX.0000
Chao-ying Fu7e399fd2014-06-10 18:11:11 -0700931 } else if (modrm_is_reg_reg && RegStorage::RegNum(raw_reg_b) >= 4) {
Razvan A Lupusoruae9f3e62014-09-23 14:54:32 -0700932 rex |= REX; // REX.0000
Chao-ying Fu7e399fd2014-06-10 18:11:11 -0700933 }
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700934 }
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +0700935 if (w) {
Razvan A Lupusoruae9f3e62014-09-23 14:54:32 -0700936 rex |= REX_W; // REX.W000
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +0700937 }
938 if (r) {
Razvan A Lupusoruae9f3e62014-09-23 14:54:32 -0700939 rex |= REX_R; // REX.0R00
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +0700940 }
941 if (x) {
Razvan A Lupusoruae9f3e62014-09-23 14:54:32 -0700942 rex |= REX_X; // REX.00X0
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +0700943 }
944 if (b) {
Razvan A Lupusoruae9f3e62014-09-23 14:54:32 -0700945 rex |= REX_B; // REX.000B
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +0700946 }
Vladimir Marko057c74a2013-12-03 15:20:45 +0000947 if (entry->skeleton.prefix1 != 0) {
Elena Sayapinadd644502014-07-01 18:39:52 +0700948 if (cu_->target64 && entry->skeleton.prefix1 == THREAD_PREFIX) {
Ian Rogers0f9b9c52014-06-09 01:32:12 -0700949 // 64 bit addresses by GS, not FS.
Dmitry Petrochenko9ee801f2014-05-12 11:31:37 +0700950 code_buffer_.push_back(THREAD_PREFIX_GS);
951 } else {
Serguei Katkov94f3eb02014-06-24 13:23:17 +0700952 if (entry->skeleton.prefix1 == REX_W || entry->skeleton.prefix1 == REX) {
953 DCHECK(cu_->target64);
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +0700954 rex |= entry->skeleton.prefix1;
955 code_buffer_.push_back(rex);
956 rex = 0;
957 } else {
958 code_buffer_.push_back(entry->skeleton.prefix1);
959 }
Dmitry Petrochenko9ee801f2014-05-12 11:31:37 +0700960 }
Vladimir Marko057c74a2013-12-03 15:20:45 +0000961 if (entry->skeleton.prefix2 != 0) {
Serguei Katkov94f3eb02014-06-24 13:23:17 +0700962 if (entry->skeleton.prefix2 == REX_W || entry->skeleton.prefix1 == REX) {
963 DCHECK(cu_->target64);
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +0700964 rex |= entry->skeleton.prefix2;
965 code_buffer_.push_back(rex);
966 rex = 0;
967 } else {
968 code_buffer_.push_back(entry->skeleton.prefix2);
969 }
Vladimir Marko057c74a2013-12-03 15:20:45 +0000970 }
971 } else {
972 DCHECK_EQ(0, entry->skeleton.prefix2);
973 }
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +0700974 if (rex != 0) {
Elena Sayapinadd644502014-07-01 18:39:52 +0700975 DCHECK(cu_->target64);
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +0700976 code_buffer_.push_back(rex);
977 }
Vladimir Marko057c74a2013-12-03 15:20:45 +0000978}
979
980void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) {
981 code_buffer_.push_back(entry->skeleton.opcode);
982 if (entry->skeleton.opcode == 0x0F) {
983 code_buffer_.push_back(entry->skeleton.extra_opcode1);
984 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {
985 code_buffer_.push_back(entry->skeleton.extra_opcode2);
986 } else {
987 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
988 }
989 } else {
990 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
991 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
992 }
993}
994
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +0700995void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry,
Ian Rogers5aa6e042014-06-13 16:38:24 -0700996 int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b) {
997 EmitPrefix(entry, raw_reg_r, raw_reg_x, raw_reg_b);
Vladimir Marko057c74a2013-12-03 15:20:45 +0000998 EmitOpcode(entry);
999}
1000
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001001void X86Mir2Lir::EmitDisp(uint8_t base, int32_t disp) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001002 // BP requires an explicit disp, so do not omit it in the 0 case
buzbee091cc402014-03-31 10:14:40 -07001003 if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001004 return;
1005 } else if (IS_SIMM8(disp)) {
1006 code_buffer_.push_back(disp & 0xFF);
1007 } else {
1008 code_buffer_.push_back(disp & 0xFF);
1009 code_buffer_.push_back((disp >> 8) & 0xFF);
1010 code_buffer_.push_back((disp >> 16) & 0xFF);
1011 code_buffer_.push_back((disp >> 24) & 0xFF);
1012 }
1013}
1014
Dmitry Petrochenko9ee801f2014-05-12 11:31:37 +07001015void X86Mir2Lir::EmitModrmThread(uint8_t reg_or_opcode) {
Elena Sayapinadd644502014-07-01 18:39:52 +07001016 if (cu_->target64) {
Dmitry Petrochenko9ee801f2014-05-12 11:31:37 +07001017 // Absolute adressing for GS access.
Ian Rogersb28c1c02014-11-08 11:21:21 -08001018 uint8_t modrm = (0 << 6) | (reg_or_opcode << 3) | rs_rX86_SP_32.GetRegNum();
Dmitry Petrochenko9ee801f2014-05-12 11:31:37 +07001019 code_buffer_.push_back(modrm);
Ian Rogersb28c1c02014-11-08 11:21:21 -08001020 uint8_t sib = (0/*TIMES_1*/ << 6) | (rs_rX86_SP_32.GetRegNum() << 3) | rs_rBP.GetRegNum();
Dmitry Petrochenko9ee801f2014-05-12 11:31:37 +07001021 code_buffer_.push_back(sib);
1022 } else {
1023 uint8_t modrm = (0 << 6) | (reg_or_opcode << 3) | rs_rBP.GetRegNum();
1024 code_buffer_.push_back(modrm);
1025 }
1026}
1027
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001028void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp) {
1029 DCHECK_LT(reg_or_opcode, 8);
Mark Mendell27dee8b2014-12-01 19:06:12 -05001030 if (base == kRIPReg) {
1031 // x86_64 RIP handling: always 32 bit displacement.
1032 uint8_t modrm = (0x0 << 6) | (reg_or_opcode << 3) | 0x5;
1033 code_buffer_.push_back(modrm);
1034 code_buffer_.push_back(disp & 0xFF);
1035 code_buffer_.push_back((disp >> 8) & 0xFF);
1036 code_buffer_.push_back((disp >> 16) & 0xFF);
1037 code_buffer_.push_back((disp >> 24) & 0xFF);
1038 } else {
1039 DCHECK_LT(base, 8);
1040 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | base;
1041 code_buffer_.push_back(modrm);
1042 if (base == rs_rX86_SP_32.GetRegNum()) {
1043 // Special SIB for SP base
1044 code_buffer_.push_back(0 << 6 | rs_rX86_SP_32.GetRegNum() << 3 | rs_rX86_SP_32.GetRegNum());
1045 }
1046 EmitDisp(base, disp);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001047 }
Brian Carlstrom7940e442013-07-12 13:46:57 -07001048}
1049
Vladimir Marko057c74a2013-12-03 15:20:45 +00001050void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index,
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001051 int scale, int32_t disp) {
buzbee091cc402014-03-31 10:14:40 -07001052 DCHECK_LT(RegStorage::RegNum(reg_or_opcode), 8);
1053 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | RegStorage::RegNum(reg_or_opcode) << 3 |
Ian Rogersb28c1c02014-11-08 11:21:21 -08001054 rs_rX86_SP_32.GetRegNum();
Brian Carlstrom7940e442013-07-12 13:46:57 -07001055 code_buffer_.push_back(modrm);
1056 DCHECK_LT(scale, 4);
buzbee091cc402014-03-31 10:14:40 -07001057 DCHECK_LT(RegStorage::RegNum(index), 8);
1058 DCHECK_LT(RegStorage::RegNum(base), 8);
1059 uint8_t sib = (scale << 6) | (RegStorage::RegNum(index) << 3) | RegStorage::RegNum(base);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001060 code_buffer_.push_back(sib);
1061 EmitDisp(base, disp);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001062}
1063
Dmitry Petrochenko96992e82014-05-20 04:03:46 +07001064void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int64_t imm) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001065 switch (entry->skeleton.immediate_bytes) {
1066 case 1:
1067 DCHECK(IS_SIMM8(imm));
1068 code_buffer_.push_back(imm & 0xFF);
1069 break;
1070 case 2:
1071 DCHECK(IS_SIMM16(imm));
1072 code_buffer_.push_back(imm & 0xFF);
1073 code_buffer_.push_back((imm >> 8) & 0xFF);
1074 break;
1075 case 4:
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001076 DCHECK(IS_SIMM32(imm));
Brian Carlstrom7940e442013-07-12 13:46:57 -07001077 code_buffer_.push_back(imm & 0xFF);
1078 code_buffer_.push_back((imm >> 8) & 0xFF);
1079 code_buffer_.push_back((imm >> 16) & 0xFF);
1080 code_buffer_.push_back((imm >> 24) & 0xFF);
1081 break;
Dmitry Petrochenko96992e82014-05-20 04:03:46 +07001082 case 8:
1083 code_buffer_.push_back(imm & 0xFF);
1084 code_buffer_.push_back((imm >> 8) & 0xFF);
1085 code_buffer_.push_back((imm >> 16) & 0xFF);
1086 code_buffer_.push_back((imm >> 24) & 0xFF);
1087 code_buffer_.push_back((imm >> 32) & 0xFF);
1088 code_buffer_.push_back((imm >> 40) & 0xFF);
1089 code_buffer_.push_back((imm >> 48) & 0xFF);
1090 code_buffer_.push_back((imm >> 56) & 0xFF);
1091 break;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001092 default:
1093 LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes
1094 << ") for instruction: " << entry->name;
1095 break;
1096 }
1097}
1098
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001099void X86Mir2Lir::EmitNullary(const X86EncodingMap* entry) {
1100 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001101 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001102 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
Vladimir Marko057c74a2013-12-03 15:20:45 +00001103 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1104 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1105}
1106
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001107void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg) {
1108 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001109 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_reg);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001110 // There's no 3-byte instruction with +rd
1111 DCHECK(entry->skeleton.opcode != 0x0F ||
1112 (entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A));
1113 DCHECK(!RegStorage::IsFloat(raw_reg));
1114 uint8_t low_reg = LowRegisterBits(raw_reg);
1115 code_buffer_.back() += low_reg;
1116 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1117 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1118}
1119
1120void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg) {
1121 CheckValidByteRegister(entry, raw_reg);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001122 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_reg);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001123 uint8_t low_reg = LowRegisterBits(raw_reg);
1124 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg;
Vladimir Marko057c74a2013-12-03 15:20:45 +00001125 code_buffer_.push_back(modrm);
1126 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1127 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1128}
1129
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001130void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp) {
1131 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001132 EmitPrefix(entry, NO_REG, NO_REG, raw_base);
Vladimir Marko057c74a2013-12-03 15:20:45 +00001133 code_buffer_.push_back(entry->skeleton.opcode);
1134 DCHECK_NE(0x0F, entry->skeleton.opcode);
1135 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
1136 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001137 uint8_t low_base = LowRegisterBits(raw_base);
1138 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp);
Vladimir Marko057c74a2013-12-03 15:20:45 +00001139 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1140 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1141}
1142
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001143void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index,
1144 int scale, int32_t disp) {
1145 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001146 EmitPrefixAndOpcode(entry, NO_REG, raw_index, raw_base);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001147 uint8_t low_index = LowRegisterBits(raw_index);
1148 uint8_t low_base = LowRegisterBits(raw_base);
1149 EmitModrmSibDisp(entry->skeleton.modrm_opcode, low_base, low_index, scale, disp);
Vladimir Marko057c74a2013-12-03 15:20:45 +00001150 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1151 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1152}
1153
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001154void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp,
1155 int32_t raw_reg) {
1156 CheckValidByteRegister(entry, raw_reg);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001157 EmitPrefixAndOpcode(entry, raw_reg, NO_REG, raw_base);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001158 uint8_t low_reg = LowRegisterBits(raw_reg);
Mark Mendell27dee8b2014-12-01 19:06:12 -05001159 uint8_t low_base = (raw_base == kRIPReg) ? raw_base : LowRegisterBits(raw_base);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001160 EmitModrmDisp(low_reg, low_base, disp);
Vladimir Marko057c74a2013-12-03 15:20:45 +00001161 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1162 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1163 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1164}
1165
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001166void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base,
1167 int32_t disp) {
Vladimir Marko057c74a2013-12-03 15:20:45 +00001168 // Opcode will flip operands.
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001169 EmitMemReg(entry, raw_base, disp, raw_reg);
Vladimir Marko057c74a2013-12-03 15:20:45 +00001170}
1171
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001172void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base,
1173 int32_t raw_index, int scale, int32_t disp) {
1174 CheckValidByteRegister(entry, raw_reg);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001175 EmitPrefixAndOpcode(entry, raw_reg, raw_index, raw_base);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001176 uint8_t low_reg = LowRegisterBits(raw_reg);
1177 uint8_t low_index = LowRegisterBits(raw_index);
1178 uint8_t low_base = LowRegisterBits(raw_base);
1179 EmitModrmSibDisp(low_reg, low_base, low_index, scale, disp);
Vladimir Marko057c74a2013-12-03 15:20:45 +00001180 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1181 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1182 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1183}
1184
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001185void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index,
1186 int scale, int32_t disp, int32_t raw_reg) {
Vladimir Marko057c74a2013-12-03 15:20:45 +00001187 // Opcode will flip operands.
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001188 EmitRegArray(entry, raw_reg, raw_base, raw_index, scale, disp);
Vladimir Marko057c74a2013-12-03 15:20:45 +00001189}
1190
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001191void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp,
1192 int32_t imm) {
1193 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001194 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_base);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001195 uint8_t low_base = LowRegisterBits(raw_base);
1196 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp);
Mark Mendell2637f2e2014-04-30 10:10:47 -04001197 DCHECK_EQ(0, entry->skeleton.ax_opcode);
Mark Mendell9ed42772014-05-07 17:26:12 -04001198 EmitImm(entry, imm);
Mark Mendell2637f2e2014-04-30 10:10:47 -04001199}
1200
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001201void X86Mir2Lir::EmitArrayImm(const X86EncodingMap* entry,
1202 int32_t raw_base, int32_t raw_index, int scale, int32_t disp,
1203 int32_t imm) {
1204 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001205 EmitPrefixAndOpcode(entry, NO_REG, raw_index, raw_base);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001206 uint8_t low_index = LowRegisterBits(raw_index);
1207 uint8_t low_base = LowRegisterBits(raw_base);
1208 EmitModrmSibDisp(entry->skeleton.modrm_opcode, low_base, low_index, scale, disp);
1209 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1210 EmitImm(entry, imm);
1211}
1212
1213void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp) {
1214 DCHECK_EQ(false, entry->skeleton.r8_form);
Vladimir Marko057c74a2013-12-03 15:20:45 +00001215 DCHECK_NE(entry->skeleton.prefix1, 0);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001216 EmitPrefixAndOpcode(entry, raw_reg, NO_REG, NO_REG);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001217 uint8_t low_reg = LowRegisterBits(raw_reg);
1218 EmitModrmThread(low_reg);
Vladimir Marko057c74a2013-12-03 15:20:45 +00001219 code_buffer_.push_back(disp & 0xFF);
1220 code_buffer_.push_back((disp >> 8) & 0xFF);
1221 code_buffer_.push_back((disp >> 16) & 0xFF);
1222 code_buffer_.push_back((disp >> 24) & 0xFF);
1223 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1224 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1225 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1226}
1227
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001228void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2) {
Chao-ying Fu021b60f2014-07-09 11:32:31 -07001229 if (!IsByteSecondOperand(entry)) {
1230 CheckValidByteRegister(entry, raw_reg1);
1231 }
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001232 CheckValidByteRegister(entry, raw_reg2);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001233 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001234 uint8_t low_reg1 = LowRegisterBits(raw_reg1);
1235 uint8_t low_reg2 = LowRegisterBits(raw_reg2);
1236 uint8_t modrm = (3 << 6) | (low_reg1 << 3) | low_reg2;
Vladimir Marko057c74a2013-12-03 15:20:45 +00001237 code_buffer_.push_back(modrm);
1238 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1239 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1240 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1241}
1242
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001243void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2,
1244 int32_t imm) {
1245 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001246 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001247 uint8_t low_reg1 = LowRegisterBits(raw_reg1);
1248 uint8_t low_reg2 = LowRegisterBits(raw_reg2);
1249 uint8_t modrm = (3 << 6) | (low_reg1 << 3) | low_reg2;
Vladimir Marko057c74a2013-12-03 15:20:45 +00001250 code_buffer_.push_back(modrm);
1251 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1252 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1253 EmitImm(entry, imm);
1254}
1255
Mark Mendell4708dcd2014-01-22 09:05:18 -08001256void X86Mir2Lir::EmitRegMemImm(const X86EncodingMap* entry,
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001257 int32_t raw_reg, int32_t raw_base, int disp, int32_t imm) {
1258 DCHECK(!RegStorage::IsFloat(raw_reg));
1259 CheckValidByteRegister(entry, raw_reg);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001260 EmitPrefixAndOpcode(entry, raw_reg, NO_REG, raw_base);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001261 uint8_t low_reg = LowRegisterBits(raw_reg);
1262 uint8_t low_base = LowRegisterBits(raw_base);
1263 EmitModrmDisp(low_reg, low_base, disp);
Mark Mendell4708dcd2014-01-22 09:05:18 -08001264 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1265 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1266 EmitImm(entry, imm);
1267}
1268
Mark Mendell2637f2e2014-04-30 10:10:47 -04001269void X86Mir2Lir::EmitMemRegImm(const X86EncodingMap* entry,
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001270 int32_t raw_base, int32_t disp, int32_t raw_reg, int32_t imm) {
1271 // Opcode will flip operands.
1272 EmitRegMemImm(entry, raw_reg, raw_base, disp, imm);
Mark Mendell2637f2e2014-04-30 10:10:47 -04001273}
1274
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001275void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm) {
1276 CheckValidByteRegister(entry, raw_reg);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001277 EmitPrefix(entry, NO_REG, NO_REG, raw_reg);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001278 if (RegStorage::RegNum(raw_reg) == rs_rAX.GetRegNum() && entry->skeleton.ax_opcode != 0) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001279 code_buffer_.push_back(entry->skeleton.ax_opcode);
1280 } else {
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001281 uint8_t low_reg = LowRegisterBits(raw_reg);
Vladimir Marko057c74a2013-12-03 15:20:45 +00001282 EmitOpcode(entry);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001283 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001284 code_buffer_.push_back(modrm);
1285 }
Vladimir Marko057c74a2013-12-03 15:20:45 +00001286 EmitImm(entry, imm);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001287}
1288
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001289void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm) {
Chao-ying Fu7e399fd2014-06-10 18:11:11 -07001290 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001291 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG);
Dmitry Petrochenko9ee801f2014-05-12 11:31:37 +07001292 EmitModrmThread(entry->skeleton.modrm_opcode);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001293 code_buffer_.push_back(disp & 0xFF);
1294 code_buffer_.push_back((disp >> 8) & 0xFF);
1295 code_buffer_.push_back((disp >> 16) & 0xFF);
1296 code_buffer_.push_back((disp >> 24) & 0xFF);
Vladimir Marko057c74a2013-12-03 15:20:45 +00001297 EmitImm(entry, imm);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001298 DCHECK_EQ(entry->skeleton.ax_opcode, 0);
1299}
1300
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001301void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm) {
1302 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001303 EmitPrefix(entry, NO_REG, NO_REG, raw_reg);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001304 uint8_t low_reg = LowRegisterBits(raw_reg);
1305 code_buffer_.push_back(0xB8 + low_reg);
Dmitry Petrochenko96992e82014-05-20 04:03:46 +07001306 switch (entry->skeleton.immediate_bytes) {
1307 case 4:
1308 code_buffer_.push_back(imm & 0xFF);
1309 code_buffer_.push_back((imm >> 8) & 0xFF);
1310 code_buffer_.push_back((imm >> 16) & 0xFF);
1311 code_buffer_.push_back((imm >> 24) & 0xFF);
1312 break;
1313 case 8:
1314 code_buffer_.push_back(imm & 0xFF);
1315 code_buffer_.push_back((imm >> 8) & 0xFF);
1316 code_buffer_.push_back((imm >> 16) & 0xFF);
1317 code_buffer_.push_back((imm >> 24) & 0xFF);
1318 code_buffer_.push_back((imm >> 32) & 0xFF);
1319 code_buffer_.push_back((imm >> 40) & 0xFF);
1320 code_buffer_.push_back((imm >> 48) & 0xFF);
1321 code_buffer_.push_back((imm >> 56) & 0xFF);
1322 break;
1323 default:
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +07001324 LOG(FATAL) << "Unsupported immediate size for EmitMovRegImm: "
1325 << static_cast<uint32_t>(entry->skeleton.immediate_bytes);
Dmitry Petrochenko96992e82014-05-20 04:03:46 +07001326 }
Brian Carlstrom7940e442013-07-12 13:46:57 -07001327}
1328
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001329void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm) {
1330 CheckValidByteRegister(entry, raw_reg);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001331 EmitPrefix(entry, NO_REG, NO_REG, raw_reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001332 if (imm != 1) {
1333 code_buffer_.push_back(entry->skeleton.opcode);
1334 } else {
1335 // Shorter encoding for 1 bit shift
1336 code_buffer_.push_back(entry->skeleton.ax_opcode);
1337 }
Vladimir Marko057c74a2013-12-03 15:20:45 +00001338 DCHECK_NE(0x0F, entry->skeleton.opcode);
1339 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
1340 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001341 uint8_t low_reg = LowRegisterBits(raw_reg);
1342 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001343 code_buffer_.push_back(modrm);
1344 if (imm != 1) {
1345 DCHECK_EQ(entry->skeleton.immediate_bytes, 1);
1346 DCHECK(IS_SIMM8(imm));
1347 code_buffer_.push_back(imm & 0xFF);
1348 }
1349}
1350
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001351void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl) {
1352 CheckValidByteRegister(entry, raw_reg);
1353 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(raw_cl));
Ian Rogers5aa6e042014-06-13 16:38:24 -07001354 EmitPrefix(entry, NO_REG, NO_REG, raw_reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001355 code_buffer_.push_back(entry->skeleton.opcode);
Vladimir Marko057c74a2013-12-03 15:20:45 +00001356 DCHECK_NE(0x0F, entry->skeleton.opcode);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001357 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
1358 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001359 uint8_t low_reg = LowRegisterBits(raw_reg);
1360 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001361 code_buffer_.push_back(modrm);
1362 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1363 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1364}
1365
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001366void X86Mir2Lir::EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base,
1367 int32_t displacement, int32_t raw_cl) {
1368 DCHECK_EQ(false, entry->skeleton.r8_form);
1369 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(raw_cl));
Ian Rogers5aa6e042014-06-13 16:38:24 -07001370 EmitPrefix(entry, NO_REG, NO_REG, raw_base);
Mark Mendellfeb2b4e2014-01-28 12:59:49 -08001371 code_buffer_.push_back(entry->skeleton.opcode);
1372 DCHECK_NE(0x0F, entry->skeleton.opcode);
1373 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
1374 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001375 uint8_t low_base = LowRegisterBits(raw_base);
1376 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, displacement);
Mark Mendellfeb2b4e2014-01-28 12:59:49 -08001377 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1378 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1379}
1380
Yixin Shouf40f8902014-08-14 14:10:32 -04001381void X86Mir2Lir::EmitShiftRegRegCl(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t raw_cl) {
1382 DCHECK_EQ(false, entry->skeleton.r8_form);
1383 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(raw_cl));
1384 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2);
1385 uint8_t low_reg1 = LowRegisterBits(raw_reg1);
1386 uint8_t low_reg2 = LowRegisterBits(raw_reg2);
1387 uint8_t modrm = (3 << 6) | (low_reg1 << 3) | low_reg2;
1388 code_buffer_.push_back(modrm);
1389 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1390 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1391 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1392}
1393
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001394void X86Mir2Lir::EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp,
1395 int32_t imm) {
1396 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001397 EmitPrefix(entry, NO_REG, NO_REG, raw_base);
Mark Mendell2637f2e2014-04-30 10:10:47 -04001398 if (imm != 1) {
1399 code_buffer_.push_back(entry->skeleton.opcode);
1400 } else {
1401 // Shorter encoding for 1 bit shift
1402 code_buffer_.push_back(entry->skeleton.ax_opcode);
1403 }
1404 DCHECK_NE(0x0F, entry->skeleton.opcode);
1405 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
1406 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001407 uint8_t low_base = LowRegisterBits(raw_base);
1408 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp);
Mark Mendell2637f2e2014-04-30 10:10:47 -04001409 if (imm != 1) {
1410 DCHECK_EQ(entry->skeleton.immediate_bytes, 1);
1411 DCHECK(IS_SIMM8(imm));
1412 code_buffer_.push_back(imm & 0xFF);
1413 }
1414}
1415
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001416void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc) {
1417 CheckValidByteRegister(entry, raw_reg);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001418 EmitPrefix(entry, NO_REG, NO_REG, raw_reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001419 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1420 DCHECK_EQ(0x0F, entry->skeleton.opcode);
1421 code_buffer_.push_back(0x0F);
1422 DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001423 DCHECK_GE(cc, 0);
1424 DCHECK_LT(cc, 16);
1425 code_buffer_.push_back(0x90 | cc);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001426 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001427 uint8_t low_reg = LowRegisterBits(raw_reg);
1428 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001429 code_buffer_.push_back(modrm);
1430 DCHECK_EQ(entry->skeleton.immediate_bytes, 0);
1431}
1432
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001433void X86Mir2Lir::EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp,
1434 int32_t cc) {
1435 DCHECK_EQ(false, entry->skeleton.r8_form);
Mark Mendell2637f2e2014-04-30 10:10:47 -04001436 if (entry->skeleton.prefix1 != 0) {
1437 code_buffer_.push_back(entry->skeleton.prefix1);
1438 if (entry->skeleton.prefix2 != 0) {
1439 code_buffer_.push_back(entry->skeleton.prefix2);
1440 }
1441 } else {
1442 DCHECK_EQ(0, entry->skeleton.prefix2);
1443 }
1444 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1445 DCHECK_EQ(0x0F, entry->skeleton.opcode);
1446 code_buffer_.push_back(0x0F);
1447 DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001448 DCHECK_GE(cc, 0);
1449 DCHECK_LT(cc, 16);
1450 code_buffer_.push_back(0x90 | cc);
Mark Mendell2637f2e2014-04-30 10:10:47 -04001451 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001452 uint8_t low_base = LowRegisterBits(raw_base);
1453 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp);
Mark Mendell2637f2e2014-04-30 10:10:47 -04001454 DCHECK_EQ(entry->skeleton.immediate_bytes, 0);
1455}
1456
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001457void X86Mir2Lir::EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2,
1458 int32_t cc) {
1459 // Generate prefix and opcode without the condition.
1460 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001461 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2);
Razvan A Lupusorubd288c22013-12-20 17:27:23 -08001462
1463 // Now add the condition. The last byte of opcode is the one that receives it.
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001464 DCHECK_GE(cc, 0);
1465 DCHECK_LT(cc, 16);
1466 code_buffer_.back() += cc;
Razvan A Lupusorubd288c22013-12-20 17:27:23 -08001467
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001468 // Not expecting to have to encode immediate or do anything special for ModR/M since there are
1469 // two registers.
Razvan A Lupusorubd288c22013-12-20 17:27:23 -08001470 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1471 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1472
Razvan A Lupusorubd288c22013-12-20 17:27:23 -08001473 // For register to register encoding, the mod is 3.
1474 const uint8_t mod = (3 << 6);
1475
1476 // Encode the ModR/M byte now.
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001477 uint8_t low_reg1 = LowRegisterBits(raw_reg1);
1478 uint8_t low_reg2 = LowRegisterBits(raw_reg2);
1479 const uint8_t modrm = mod | (low_reg1 << 3) | low_reg2;
Razvan A Lupusorubd288c22013-12-20 17:27:23 -08001480 code_buffer_.push_back(modrm);
1481}
1482
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001483void X86Mir2Lir::EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base,
1484 int32_t disp, int32_t cc) {
1485 // Generate prefix and opcode without the condition.
1486 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001487 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_base);
Mark Mendell2637f2e2014-04-30 10:10:47 -04001488
1489 // Now add the condition. The last byte of opcode is the one that receives it.
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001490 DCHECK_GE(cc, 0);
1491 DCHECK_LT(cc, 16);
1492 code_buffer_.back() += cc;
Mark Mendell2637f2e2014-04-30 10:10:47 -04001493
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001494 // Not expecting to have to encode immediate or do anything special for ModR/M since there are
1495 // two registers.
Mark Mendell2637f2e2014-04-30 10:10:47 -04001496 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1497 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1498
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001499 uint8_t low_reg1 = LowRegisterBits(raw_reg1);
1500 uint8_t low_base = LowRegisterBits(raw_base);
1501 EmitModrmDisp(low_reg1, low_base, disp);
Mark Mendell2637f2e2014-04-30 10:10:47 -04001502}
1503
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001504void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int32_t rel) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001505 if (entry->opcode == kX86Jmp8) {
1506 DCHECK(IS_SIMM8(rel));
1507 code_buffer_.push_back(0xEB);
1508 code_buffer_.push_back(rel & 0xFF);
1509 } else if (entry->opcode == kX86Jmp32) {
1510 code_buffer_.push_back(0xE9);
1511 code_buffer_.push_back(rel & 0xFF);
1512 code_buffer_.push_back((rel >> 8) & 0xFF);
1513 code_buffer_.push_back((rel >> 16) & 0xFF);
1514 code_buffer_.push_back((rel >> 24) & 0xFF);
Mark Mendell4028a6c2014-02-19 20:06:20 -08001515 } else if (entry->opcode == kX86Jecxz8) {
1516 DCHECK(IS_SIMM8(rel));
1517 code_buffer_.push_back(0xE3);
1518 code_buffer_.push_back(rel & 0xFF);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001519 } else {
1520 DCHECK(entry->opcode == kX86JmpR);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001521 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001522 EmitPrefix(entry, NO_REG, NO_REG, rel);
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +07001523 code_buffer_.push_back(entry->skeleton.opcode);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001524 uint8_t low_reg = LowRegisterBits(rel);
1525 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001526 code_buffer_.push_back(modrm);
1527 }
1528}
1529
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001530void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc) {
1531 DCHECK_GE(cc, 0);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001532 DCHECK_LT(cc, 16);
1533 if (entry->opcode == kX86Jcc8) {
1534 DCHECK(IS_SIMM8(rel));
1535 code_buffer_.push_back(0x70 | cc);
1536 code_buffer_.push_back(rel & 0xFF);
1537 } else {
1538 DCHECK(entry->opcode == kX86Jcc32);
1539 code_buffer_.push_back(0x0F);
1540 code_buffer_.push_back(0x80 | cc);
1541 code_buffer_.push_back(rel & 0xFF);
1542 code_buffer_.push_back((rel >> 8) & 0xFF);
1543 code_buffer_.push_back((rel >> 16) & 0xFF);
1544 code_buffer_.push_back((rel >> 24) & 0xFF);
1545 }
1546}
1547
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001548void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp) {
1549 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001550 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_base);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001551 uint8_t low_base = LowRegisterBits(raw_base);
1552 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001553 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1554 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1555}
1556
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001557void X86Mir2Lir::EmitCallImmediate(const X86EncodingMap* entry, int32_t disp) {
1558 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001559 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG);
Mark Mendell55d0eac2014-02-06 11:02:52 -08001560 DCHECK_EQ(4, entry->skeleton.immediate_bytes);
1561 code_buffer_.push_back(disp & 0xFF);
1562 code_buffer_.push_back((disp >> 8) & 0xFF);
1563 code_buffer_.push_back((disp >> 16) & 0xFF);
1564 code_buffer_.push_back((disp >> 24) & 0xFF);
1565 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1566}
1567
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001568void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int32_t disp) {
1569 DCHECK_EQ(false, entry->skeleton.r8_form);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001570 DCHECK_NE(entry->skeleton.prefix1, 0);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001571 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG);
Dmitry Petrochenko9ee801f2014-05-12 11:31:37 +07001572 EmitModrmThread(entry->skeleton.modrm_opcode);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001573 code_buffer_.push_back(disp & 0xFF);
1574 code_buffer_.push_back((disp >> 8) & 0xFF);
1575 code_buffer_.push_back((disp >> 16) & 0xFF);
1576 code_buffer_.push_back((disp >> 24) & 0xFF);
1577 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1578 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1579}
1580
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001581void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table,
1582 int32_t raw_index, int scale, int32_t table_or_disp) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001583 int disp;
1584 if (entry->opcode == kX86PcRelLoadRA) {
Vladimir Marko1961b602015-04-08 20:51:48 +01001585 const SwitchTable* tab_rec = UnwrapPointer<SwitchTable>(table_or_disp);
1586 disp = tab_rec->offset - tab_rec->anchor->offset;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001587 } else {
1588 DCHECK(entry->opcode == kX86PcRelAdr);
Vladimir Markof6737f72015-03-23 17:05:14 +00001589 const EmbeddedData* tab_rec = UnwrapPointer<EmbeddedData>(raw_base_or_table);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001590 disp = tab_rec->offset;
1591 }
Brian Carlstrom7940e442013-07-12 13:46:57 -07001592 if (entry->opcode == kX86PcRelLoadRA) {
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001593 DCHECK_EQ(false, entry->skeleton.r8_form);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001594 EmitPrefix(entry, raw_reg, raw_index, raw_base_or_table);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001595 code_buffer_.push_back(entry->skeleton.opcode);
Vladimir Marko057c74a2013-12-03 15:20:45 +00001596 DCHECK_NE(0x0F, entry->skeleton.opcode);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001597 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
1598 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001599 uint8_t low_reg = LowRegisterBits(raw_reg);
Ian Rogersb28c1c02014-11-08 11:21:21 -08001600 uint8_t modrm = (2 << 6) | (low_reg << 3) | rs_rX86_SP_32.GetRegNum();
Brian Carlstrom7940e442013-07-12 13:46:57 -07001601 code_buffer_.push_back(modrm);
1602 DCHECK_LT(scale, 4);
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001603 uint8_t low_base_or_table = LowRegisterBits(raw_base_or_table);
1604 uint8_t low_index = LowRegisterBits(raw_index);
1605 uint8_t sib = (scale << 6) | (low_index << 3) | low_base_or_table;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001606 code_buffer_.push_back(sib);
1607 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1608 } else {
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001609 uint8_t low_reg = LowRegisterBits(raw_reg);
1610 code_buffer_.push_back(entry->skeleton.opcode + low_reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001611 }
1612 code_buffer_.push_back(disp & 0xFF);
1613 code_buffer_.push_back((disp >> 8) & 0xFF);
1614 code_buffer_.push_back((disp >> 16) & 0xFF);
1615 code_buffer_.push_back((disp >> 24) & 0xFF);
1616 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1617 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1618}
1619
Brian Carlstrom7940e442013-07-12 13:46:57 -07001620void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) {
1621 UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " "
1622 << BuildInsnString(entry->fmt, lir, 0);
Ian Rogers5aa6e042014-06-13 16:38:24 -07001623 for (size_t i = 0; i < GetInsnSize(lir); ++i) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001624 code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3
1625 }
1626}
1627
1628/*
1629 * Assemble the LIR into binary instruction format. Note that we may
1630 * discover that pc-relative displacements may not fit the selected
1631 * instruction. In those cases we will try to substitute a new code
1632 * sequence or request that the trace be shortened and retried.
1633 */
Roland Levillain4b8f1ec2015-08-26 18:34:03 +01001634AssemblerStatus X86Mir2Lir::AssembleInstructions(LIR* first_lir_insn,
1635 CodeOffset start_addr ATTRIBUTE_UNUSED) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001636 LIR *lir;
1637 AssemblerStatus res = kSuccess; // Assume success
1638
1639 const bool kVerbosePcFixup = false;
Chao-ying Fuc4013ea2015-04-22 10:51:21 -07001640 for (lir = first_lir_insn; lir != nullptr; lir = NEXT_LIR(lir)) {
buzbee409fe942013-10-11 10:49:56 -07001641 if (IsPseudoLirOp(lir->opcode)) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001642 continue;
1643 }
1644
1645 if (lir->flags.is_nop) {
1646 continue;
1647 }
1648
buzbeeb48819d2013-09-14 16:15:25 -07001649 if (lir->flags.fixup != kFixupNone) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001650 switch (lir->opcode) {
1651 case kX86Jcc8: {
1652 LIR *target_lir = lir->target;
Mathieu Chartier2cebb242015-04-21 16:50:40 -07001653 DCHECK(target_lir != nullptr);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001654 int delta = 0;
buzbee0d829482013-10-11 15:24:55 -07001655 CodeOffset pc;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001656 if (IS_SIMM8(lir->operands[0])) {
1657 pc = lir->offset + 2 /* opcode + rel8 */;
1658 } else {
1659 pc = lir->offset + 6 /* 2 byte opcode + rel32 */;
1660 }
buzbee0d829482013-10-11 15:24:55 -07001661 CodeOffset target = target_lir->offset;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001662 delta = target - pc;
1663 if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {
1664 if (kVerbosePcFixup) {
1665 LOG(INFO) << "Retry for JCC growth at " << lir->offset
1666 << " delta: " << delta << " old delta: " << lir->operands[0];
1667 }
1668 lir->opcode = kX86Jcc32;
Vladimir Marko8dea81c2014-06-06 14:50:36 +01001669 lir->flags.size = GetInsnSize(lir);
1670 DCHECK(lir->u.m.def_mask->Equals(kEncodeAll));
1671 DCHECK(lir->u.m.use_mask->Equals(kEncodeAll));
Brian Carlstrom7940e442013-07-12 13:46:57 -07001672 res = kRetryAll;
1673 }
1674 if (kVerbosePcFixup) {
1675 LOG(INFO) << "Source:";
1676 DumpLIRInsn(lir, 0);
1677 LOG(INFO) << "Target:";
1678 DumpLIRInsn(target_lir, 0);
1679 LOG(INFO) << "Delta " << delta;
1680 }
1681 lir->operands[0] = delta;
1682 break;
1683 }
1684 case kX86Jcc32: {
1685 LIR *target_lir = lir->target;
Mathieu Chartier2cebb242015-04-21 16:50:40 -07001686 DCHECK(target_lir != nullptr);
buzbee0d829482013-10-11 15:24:55 -07001687 CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */;
1688 CodeOffset target = target_lir->offset;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001689 int delta = target - pc;
1690 if (kVerbosePcFixup) {
1691 LOG(INFO) << "Source:";
1692 DumpLIRInsn(lir, 0);
1693 LOG(INFO) << "Target:";
1694 DumpLIRInsn(target_lir, 0);
1695 LOG(INFO) << "Delta " << delta;
1696 }
1697 lir->operands[0] = delta;
1698 break;
1699 }
Mark Mendell4028a6c2014-02-19 20:06:20 -08001700 case kX86Jecxz8: {
1701 LIR *target_lir = lir->target;
Mathieu Chartier2cebb242015-04-21 16:50:40 -07001702 DCHECK(target_lir != nullptr);
Mark Mendell4028a6c2014-02-19 20:06:20 -08001703 CodeOffset pc;
1704 pc = lir->offset + 2; // opcode + rel8
1705 CodeOffset target = target_lir->offset;
1706 int delta = target - pc;
1707 lir->operands[0] = delta;
1708 DCHECK(IS_SIMM8(delta));
1709 break;
1710 }
Brian Carlstrom7940e442013-07-12 13:46:57 -07001711 case kX86Jmp8: {
1712 LIR *target_lir = lir->target;
Mathieu Chartier2cebb242015-04-21 16:50:40 -07001713 DCHECK(target_lir != nullptr);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001714 int delta = 0;
buzbee0d829482013-10-11 15:24:55 -07001715 CodeOffset pc;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001716 if (IS_SIMM8(lir->operands[0])) {
1717 pc = lir->offset + 2 /* opcode + rel8 */;
1718 } else {
1719 pc = lir->offset + 5 /* opcode + rel32 */;
1720 }
buzbee0d829482013-10-11 15:24:55 -07001721 CodeOffset target = target_lir->offset;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001722 delta = target - pc;
1723 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) {
1724 // Useless branch
buzbee252254b2013-09-08 16:20:53 -07001725 NopLIR(lir);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001726 if (kVerbosePcFixup) {
1727 LOG(INFO) << "Retry for useless branch at " << lir->offset;
1728 }
1729 res = kRetryAll;
1730 } else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {
1731 if (kVerbosePcFixup) {
1732 LOG(INFO) << "Retry for JMP growth at " << lir->offset;
1733 }
1734 lir->opcode = kX86Jmp32;
Vladimir Marko8dea81c2014-06-06 14:50:36 +01001735 lir->flags.size = GetInsnSize(lir);
1736 DCHECK(lir->u.m.def_mask->Equals(kEncodeAll));
1737 DCHECK(lir->u.m.use_mask->Equals(kEncodeAll));
Brian Carlstrom7940e442013-07-12 13:46:57 -07001738 res = kRetryAll;
1739 }
1740 lir->operands[0] = delta;
1741 break;
1742 }
1743 case kX86Jmp32: {
1744 LIR *target_lir = lir->target;
Mathieu Chartier2cebb242015-04-21 16:50:40 -07001745 DCHECK(target_lir != nullptr);
buzbee0d829482013-10-11 15:24:55 -07001746 CodeOffset pc = lir->offset + 5 /* opcode + rel32 */;
1747 CodeOffset target = target_lir->offset;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001748 int delta = target - pc;
1749 lir->operands[0] = delta;
1750 break;
1751 }
1752 default:
Mark Mendell67c39c42014-01-31 17:28:00 -08001753 if (lir->flags.fixup == kFixupLoad) {
1754 LIR *target_lir = lir->target;
Mathieu Chartier2cebb242015-04-21 16:50:40 -07001755 DCHECK(target_lir != nullptr);
Mark Mendell67c39c42014-01-31 17:28:00 -08001756 CodeOffset target = target_lir->offset;
Mark Mendell27dee8b2014-12-01 19:06:12 -05001757 // Handle 64 bit RIP addressing.
1758 if (lir->operands[1] == kRIPReg) {
1759 // Offset is relative to next instruction.
1760 lir->operands[2] = target - (lir->offset + lir->flags.size);
1761 } else {
Vladimir Marko1961b602015-04-08 20:51:48 +01001762 const LIR* anchor = UnwrapPointer<LIR>(lir->operands[4]);
1763 lir->operands[2] = target - anchor->offset;
Mark Mendell27dee8b2014-12-01 19:06:12 -05001764 int newSize = GetInsnSize(lir);
1765 if (newSize != lir->flags.size) {
1766 lir->flags.size = newSize;
1767 res = kRetryAll;
1768 }
Mark Mendell67c39c42014-01-31 17:28:00 -08001769 }
Mark Mendell27dee8b2014-12-01 19:06:12 -05001770 } else if (lir->flags.fixup == kFixupSwitchTable) {
1771 DCHECK(cu_->target64);
1772 DCHECK_EQ(lir->opcode, kX86Lea64RM) << "Unknown instruction: " << X86Mir2Lir::EncodingMap[lir->opcode].name;
1773 DCHECK_EQ(lir->operands[1], static_cast<int>(kRIPReg));
1774 // Grab the target offset from the saved data.
Vladimir Markof6737f72015-03-23 17:05:14 +00001775 const EmbeddedData* tab_rec = UnwrapPointer<Mir2Lir::EmbeddedData>(lir->operands[4]);
Mark Mendell27dee8b2014-12-01 19:06:12 -05001776 CodeOffset target = tab_rec->offset;
1777 // Handle 64 bit RIP addressing.
1778 // Offset is relative to next instruction.
1779 lir->operands[2] = target - (lir->offset + lir->flags.size);
Mark Mendell67c39c42014-01-31 17:28:00 -08001780 }
Brian Carlstrom7940e442013-07-12 13:46:57 -07001781 break;
1782 }
1783 }
1784
1785 /*
1786 * If one of the pc-relative instructions expanded we'll have
1787 * to make another pass. Don't bother to fully assemble the
1788 * instruction.
1789 */
1790 if (res != kSuccess) {
1791 continue;
1792 }
1793 CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size());
1794 const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode];
1795 size_t starting_cbuf_size = code_buffer_.size();
1796 switch (entry->kind) {
1797 case kData: // 4 bytes of data
1798 code_buffer_.push_back(lir->operands[0]);
1799 break;
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001800 case kNullary: // 1 byte of opcode and possible prefixes.
1801 EmitNullary(entry);
Mark Mendell4028a6c2014-02-19 20:06:20 -08001802 break;
Vladimir Markoa8b4caf2013-10-24 15:08:57 +01001803 case kRegOpcode: // lir operands - 0: reg
1804 EmitOpRegOpcode(entry, lir->operands[0]);
1805 break;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001806 case kReg: // lir operands - 0: reg
1807 EmitOpReg(entry, lir->operands[0]);
1808 break;
1809 case kMem: // lir operands - 0: base, 1: disp
1810 EmitOpMem(entry, lir->operands[0], lir->operands[1]);
1811 break;
Vladimir Marko057c74a2013-12-03 15:20:45 +00001812 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp
1813 EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]);
1814 break;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001815 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg
1816 EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1817 break;
Mark Mendell343adb52013-12-18 06:02:17 -08001818 case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate
1819 EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1820 break;
Mark Mendell2637f2e2014-04-30 10:10:47 -04001821 case kArrayImm: // lir operands - 0: base, 1: index, 2: disp, 3:scale, 4:immediate
1822 EmitArrayImm(entry, lir->operands[0], lir->operands[1], lir->operands[2],
1823 lir->operands[3], lir->operands[4]);
1824 break;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001825 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg
1826 EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2],
1827 lir->operands[3], lir->operands[4]);
1828 break;
1829 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp
1830 EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1831 break;
1832 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp
1833 EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2],
1834 lir->operands[3], lir->operands[4]);
1835 break;
1836 case kRegThread: // lir operands - 0: reg, 1: disp
1837 EmitRegThread(entry, lir->operands[0], lir->operands[1]);
1838 break;
1839 case kRegReg: // lir operands - 0: reg1, 1: reg2
1840 EmitRegReg(entry, lir->operands[0], lir->operands[1]);
1841 break;
1842 case kRegRegStore: // lir operands - 0: reg2, 1: reg1
1843 EmitRegReg(entry, lir->operands[1], lir->operands[0]);
1844 break;
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001845 case kMemRegImm: // lir operands - 0: base, 1: disp, 2: reg 3: immediate
Mark Mendell2637f2e2014-04-30 10:10:47 -04001846 EmitMemRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2],
1847 lir->operands[3]);
1848 break;
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001849 case kRegRegImm: // lir operands - 0: reg1, 1: reg2, 2: imm
Brian Carlstrom7940e442013-07-12 13:46:57 -07001850 EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1851 break;
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001852 case kRegRegImmStore: // lir operands - 0: reg2, 1: reg1, 2: imm
1853 EmitRegRegImm(entry, lir->operands[1], lir->operands[0], lir->operands[2]);
1854 break;
1855 case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm
Mark Mendell4708dcd2014-01-22 09:05:18 -08001856 EmitRegMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2],
1857 lir->operands[3]);
1858 break;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001859 case kRegImm: // lir operands - 0: reg, 1: immediate
1860 EmitRegImm(entry, lir->operands[0], lir->operands[1]);
1861 break;
1862 case kThreadImm: // lir operands - 0: disp, 1: immediate
1863 EmitThreadImm(entry, lir->operands[0], lir->operands[1]);
1864 break;
1865 case kMovRegImm: // lir operands - 0: reg, 1: immediate
1866 EmitMovRegImm(entry, lir->operands[0], lir->operands[1]);
1867 break;
Yixin Shou5192cbb2014-07-01 13:48:17 -04001868 case kMovRegQuadImm: {
1869 int64_t value = static_cast<int64_t>(static_cast<int64_t>(lir->operands[1]) << 32 |
1870 static_cast<uint32_t>(lir->operands[2]));
1871 EmitMovRegImm(entry, lir->operands[0], value);
1872 }
1873 break;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001874 case kShiftRegImm: // lir operands - 0: reg, 1: immediate
1875 EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]);
1876 break;
Mark Mendell2637f2e2014-04-30 10:10:47 -04001877 case kShiftMemImm: // lir operands - 0: base, 1: disp, 2:immediate
1878 EmitShiftMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1879 break;
Brian Carlstrom7934ac22013-07-26 10:54:15 -07001880 case kShiftRegCl: // lir operands - 0: reg, 1: cl
Brian Carlstrom7940e442013-07-12 13:46:57 -07001881 EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]);
1882 break;
Mark Mendellfeb2b4e2014-01-28 12:59:49 -08001883 case kShiftMemCl: // lir operands - 0: base, 1:displacement, 2: cl
1884 EmitShiftMemCl(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1885 break;
Yixin Shouf40f8902014-08-14 14:10:32 -04001886 case kShiftRegRegCl: // lir operands - 0: reg1, 1: reg2, 2: cl
1887 EmitShiftRegRegCl(entry, lir->operands[1], lir->operands[0], lir->operands[2]);
1888 break;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001889 case kRegCond: // lir operands - 0: reg, 1: condition
1890 EmitRegCond(entry, lir->operands[0], lir->operands[1]);
1891 break;
Mark Mendell2637f2e2014-04-30 10:10:47 -04001892 case kMemCond: // lir operands - 0: base, 1: displacement, 2: condition
1893 EmitMemCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1894 break;
Razvan A Lupusorubd288c22013-12-20 17:27:23 -08001895 case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: condition
1896 EmitRegRegCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1897 break;
Mark Mendell2637f2e2014-04-30 10:10:47 -04001898 case kRegMemCond: // lir operands - 0: reg, 1: reg, displacement, 3: condition
Dmitry Petrochenkoa20468c2014-04-30 13:40:19 +07001899 EmitRegMemCond(entry, lir->operands[0], lir->operands[1], lir->operands[2],
1900 lir->operands[3]);
Mark Mendell2637f2e2014-04-30 10:10:47 -04001901 break;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001902 case kJmp: // lir operands - 0: rel
Brian Carlstrom60d7a652014-03-13 18:10:08 -07001903 if (entry->opcode == kX86JmpT) {
1904 // This works since the instruction format for jmp and call is basically the same and
1905 // EmitCallThread loads opcode info.
1906 EmitCallThread(entry, lir->operands[0]);
1907 } else {
1908 EmitJmp(entry, lir->operands[0]);
1909 }
Brian Carlstrom7940e442013-07-12 13:46:57 -07001910 break;
1911 case kJcc: // lir operands - 0: rel, 1: CC, target assigned
1912 EmitJcc(entry, lir->operands[0], lir->operands[1]);
1913 break;
1914 case kCall:
1915 switch (entry->opcode) {
Mark Mendell55d0eac2014-02-06 11:02:52 -08001916 case kX86CallI: // lir operands - 0: disp
1917 EmitCallImmediate(entry, lir->operands[0]);
1918 break;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001919 case kX86CallM: // lir operands - 0: base, 1: disp
1920 EmitCallMem(entry, lir->operands[0], lir->operands[1]);
1921 break;
1922 case kX86CallT: // lir operands - 0: disp
1923 EmitCallThread(entry, lir->operands[0]);
1924 break;
1925 default:
1926 EmitUnimplemented(entry, lir);
1927 break;
1928 }
1929 break;
1930 case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table
1931 EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2],
1932 lir->operands[3], lir->operands[4]);
1933 break;
Ian Rogers0f9b9c52014-06-09 01:32:12 -07001934 case kNop: // TODO: these instruction kinds are missing implementations.
1935 case kThreadReg:
1936 case kRegArrayImm:
1937 case kShiftArrayImm:
1938 case kShiftArrayCl:
1939 case kArrayCond:
1940 case kUnimplemented:
Brian Carlstrom7940e442013-07-12 13:46:57 -07001941 EmitUnimplemented(entry, lir);
1942 break;
1943 }
Ian Rogers5aa6e042014-06-13 16:38:24 -07001944 DCHECK_EQ(lir->flags.size, GetInsnSize(lir));
1945 CHECK_EQ(lir->flags.size, code_buffer_.size() - starting_cbuf_size)
Brian Carlstrom7940e442013-07-12 13:46:57 -07001946 << "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name;
1947 }
1948 return res;
1949}
1950
buzbeeb48819d2013-09-14 16:15:25 -07001951// LIR offset assignment.
1952// TODO: consolidate w/ Arm assembly mechanism.
1953int X86Mir2Lir::AssignInsnOffsets() {
1954 LIR* lir;
1955 int offset = 0;
1956
Mathieu Chartier2cebb242015-04-21 16:50:40 -07001957 for (lir = first_lir_insn_; lir != nullptr; lir = NEXT_LIR(lir)) {
buzbeeb48819d2013-09-14 16:15:25 -07001958 lir->offset = offset;
buzbee409fe942013-10-11 10:49:56 -07001959 if (LIKELY(!IsPseudoLirOp(lir->opcode))) {
buzbeeb48819d2013-09-14 16:15:25 -07001960 if (!lir->flags.is_nop) {
1961 offset += lir->flags.size;
1962 }
1963 } else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) {
1964 if (offset & 0x2) {
1965 offset += 2;
1966 lir->operands[0] = 1;
1967 } else {
1968 lir->operands[0] = 0;
1969 }
1970 }
1971 /* Pseudo opcodes don't consume space */
1972 }
1973 return offset;
1974}
1975
1976/*
1977 * Walk the compilation unit and assign offsets to instructions
1978 * and literals and compute the total size of the compiled unit.
1979 * TODO: consolidate w/ Arm assembly mechanism.
1980 */
1981void X86Mir2Lir::AssignOffsets() {
1982 int offset = AssignInsnOffsets();
1983
Mark Mendelld65c51a2014-04-29 16:55:20 -04001984 if (const_vectors_ != nullptr) {
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -07001985 // Vector literals must be 16-byte aligned. The header that is placed
1986 // in the code section causes misalignment so we take it into account.
1987 // Otherwise, we are sure that for x86 method is aligned to 16.
1988 DCHECK_EQ(GetInstructionSetAlignment(cu_->instruction_set), 16u);
1989 uint32_t bytes_to_fill = (0x10 - ((offset + sizeof(OatQuickMethodHeader)) & 0xF)) & 0xF;
1990 offset += bytes_to_fill;
Mark Mendelld65c51a2014-04-29 16:55:20 -04001991
1992 // Now assign each literal the right offset.
1993 for (LIR *p = const_vectors_; p != nullptr; p = p->next) {
1994 p->offset = offset;
1995 offset += 16;
1996 }
1997 }
1998
buzbeeb48819d2013-09-14 16:15:25 -07001999 /* Const values have to be word aligned */
Andreas Gampe66018822014-05-05 20:47:19 -07002000 offset = RoundUp(offset, 4);
buzbeeb48819d2013-09-14 16:15:25 -07002001
2002 /* Set up offsets for literals */
2003 data_offset_ = offset;
2004
2005 offset = AssignLiteralOffset(offset);
2006
2007 offset = AssignSwitchTablesOffset(offset);
2008
2009 offset = AssignFillArrayDataOffset(offset);
2010
2011 total_size_ = offset;
2012}
2013
2014/*
2015 * Go over each instruction in the list and calculate the offset from the top
2016 * before sending them off to the assembler. If out-of-range branch distance is
2017 * seen rearrange the instructions a bit to correct it.
2018 * TODO: consolidate w/ Arm assembly mechanism.
2019 */
2020void X86Mir2Lir::AssembleLIR() {
buzbeea61f4952013-08-23 14:27:06 -07002021 cu_->NewTimingSplit("Assemble");
Mark Mendell55d0eac2014-02-06 11:02:52 -08002022
2023 // We will remove the method address if we never ended up using it
Vladimir Marko1961b602015-04-08 20:51:48 +01002024 if (pc_rel_base_reg_.Valid() && !pc_rel_base_reg_used_) {
2025 if (kIsDebugBuild) {
2026 LOG(WARNING) << "PC-relative addressing base promoted but unused in "
2027 << PrettyMethod(cu_->method_idx, *cu_->dex_file);
2028 }
2029 setup_pc_rel_base_reg_->flags.is_nop = true;
2030 NEXT_LIR(setup_pc_rel_base_reg_)->flags.is_nop = true;
Mark Mendell55d0eac2014-02-06 11:02:52 -08002031 }
2032
buzbeeb48819d2013-09-14 16:15:25 -07002033 AssignOffsets();
2034 int assembler_retries = 0;
2035 /*
2036 * Assemble here. Note that we generate code with optimistic assumptions
2037 * and if found now to work, we'll have to redo the sequence and retry.
2038 */
2039
2040 while (true) {
Chao-ying Fuc4013ea2015-04-22 10:51:21 -07002041 AssemblerStatus res = AssembleInstructions(first_lir_insn_, 0);
buzbeeb48819d2013-09-14 16:15:25 -07002042 if (res == kSuccess) {
2043 break;
2044 } else {
2045 assembler_retries++;
2046 if (assembler_retries > MAX_ASSEMBLER_RETRIES) {
2047 CodegenDump();
2048 LOG(FATAL) << "Assembler error - too many retries";
2049 }
2050 // Redo offsets and try again
2051 AssignOffsets();
2052 code_buffer_.clear();
2053 }
2054 }
2055
2056 // Install literals
2057 InstallLiteralPools();
2058
2059 // Install switch tables
2060 InstallSwitchTables();
2061
2062 // Install fill array data
2063 InstallFillArrayData();
2064
2065 // Create the mapping table and native offset to reference map.
buzbeea61f4952013-08-23 14:27:06 -07002066 cu_->NewTimingSplit("PcMappingTable");
buzbeeb48819d2013-09-14 16:15:25 -07002067 CreateMappingTables();
2068
buzbeea61f4952013-08-23 14:27:06 -07002069 cu_->NewTimingSplit("GcMap");
buzbeeb48819d2013-09-14 16:15:25 -07002070 CreateNativeGcMap();
2071}
2072
Brian Carlstrom7940e442013-07-12 13:46:57 -07002073} // namespace art