Elliott Hughes | 2faa5f1 | 2012-01-30 14:42:07 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 16 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 17 | #include "assembler_x86.h" |
| 18 | |
Elliott Hughes | 1aa246d | 2012-12-13 09:29:36 -0800 | [diff] [blame] | 19 | #include "base/casts.h" |
Ian Rogers | 166db04 | 2013-07-26 12:05:57 -0700 | [diff] [blame] | 20 | #include "entrypoints/quick/quick_entrypoints.h" |
Brian Carlstrom | 578bbdc | 2011-07-21 14:07:47 -0700 | [diff] [blame] | 21 | #include "memory_region.h" |
Brian Carlstrom | 578bbdc | 2011-07-21 14:07:47 -0700 | [diff] [blame] | 22 | #include "thread.h" |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 23 | |
Carl Shapiro | 6b6b5f0 | 2011-06-21 15:05:09 -0700 | [diff] [blame] | 24 | namespace art { |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 25 | namespace x86 { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 26 | |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 27 | std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) { |
| 28 | return os << "XMM" << static_cast<int>(reg); |
| 29 | } |
| 30 | |
| 31 | std::ostream& operator<<(std::ostream& os, const X87Register& reg) { |
| 32 | return os << "ST" << static_cast<int>(reg); |
| 33 | } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 34 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 35 | void X86Assembler::call(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 36 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 37 | EmitUint8(0xFF); |
| 38 | EmitRegisterOperand(2, reg); |
| 39 | } |
| 40 | |
| 41 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 42 | void X86Assembler::call(const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 43 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 44 | EmitUint8(0xFF); |
| 45 | EmitOperand(2, address); |
| 46 | } |
| 47 | |
| 48 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 49 | void X86Assembler::call(Label* label) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 50 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 51 | EmitUint8(0xE8); |
| 52 | static const int kSize = 5; |
Nicolas Geoffray | 1cf9528 | 2014-12-12 19:22:03 +0000 | [diff] [blame] | 53 | // Offset by one because we already have emitted the opcode. |
| 54 | EmitLabel(label, kSize - 1); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 55 | } |
| 56 | |
| 57 | |
Nicolas Geoffray | 8ccc3f5 | 2014-03-19 10:34:11 +0000 | [diff] [blame] | 58 | void X86Assembler::call(const ExternalLabel& label) { |
| 59 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 60 | intptr_t call_start = buffer_.GetPosition(); |
| 61 | EmitUint8(0xE8); |
| 62 | EmitInt32(label.address()); |
| 63 | static const intptr_t kCallExternalLabelSize = 5; |
| 64 | DCHECK_EQ((buffer_.GetPosition() - call_start), kCallExternalLabelSize); |
| 65 | } |
| 66 | |
| 67 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 68 | void X86Assembler::pushl(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 69 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 70 | EmitUint8(0x50 + reg); |
| 71 | } |
| 72 | |
| 73 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 74 | void X86Assembler::pushl(const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 75 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 76 | EmitUint8(0xFF); |
| 77 | EmitOperand(6, address); |
| 78 | } |
| 79 | |
| 80 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 81 | void X86Assembler::pushl(const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 82 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 83 | if (imm.is_int8()) { |
| 84 | EmitUint8(0x6A); |
| 85 | EmitUint8(imm.value() & 0xFF); |
| 86 | } else { |
| 87 | EmitUint8(0x68); |
| 88 | EmitImmediate(imm); |
| 89 | } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 93 | void X86Assembler::popl(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 94 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 95 | EmitUint8(0x58 + reg); |
| 96 | } |
| 97 | |
| 98 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 99 | void X86Assembler::popl(const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 100 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 101 | EmitUint8(0x8F); |
| 102 | EmitOperand(0, address); |
| 103 | } |
| 104 | |
| 105 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 106 | void X86Assembler::movl(Register dst, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 107 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 108 | EmitUint8(0xB8 + dst); |
| 109 | EmitImmediate(imm); |
| 110 | } |
| 111 | |
| 112 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 113 | void X86Assembler::movl(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 114 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 115 | EmitUint8(0x89); |
| 116 | EmitRegisterOperand(src, dst); |
| 117 | } |
| 118 | |
| 119 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 120 | void X86Assembler::movl(Register dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 121 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 122 | EmitUint8(0x8B); |
| 123 | EmitOperand(dst, src); |
| 124 | } |
| 125 | |
| 126 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 127 | void X86Assembler::movl(const Address& dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 128 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 129 | EmitUint8(0x89); |
| 130 | EmitOperand(src, dst); |
| 131 | } |
| 132 | |
| 133 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 134 | void X86Assembler::movl(const Address& dst, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 135 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 136 | EmitUint8(0xC7); |
| 137 | EmitOperand(0, dst); |
| 138 | EmitImmediate(imm); |
| 139 | } |
| 140 | |
Ian Rogers | bdb0391 | 2011-09-14 00:55:44 -0700 | [diff] [blame] | 141 | void X86Assembler::movl(const Address& dst, Label* lbl) { |
| 142 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 143 | EmitUint8(0xC7); |
| 144 | EmitOperand(0, dst); |
| 145 | EmitLabel(lbl, dst.length_ + 5); |
| 146 | } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 147 | |
Mark Mendell | 7a08fb5 | 2015-07-15 14:09:35 -0400 | [diff] [blame] | 148 | void X86Assembler::movntl(const Address& dst, Register src) { |
| 149 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 150 | EmitUint8(0x0F); |
| 151 | EmitUint8(0xC3); |
| 152 | EmitOperand(src, dst); |
| 153 | } |
| 154 | |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 155 | void X86Assembler::bswapl(Register dst) { |
| 156 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 157 | EmitUint8(0x0F); |
| 158 | EmitUint8(0xC8 + dst); |
| 159 | } |
| 160 | |
Mark Mendell | bcee092 | 2015-09-15 21:45:01 -0400 | [diff] [blame] | 161 | void X86Assembler::bsfl(Register dst, Register src) { |
| 162 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 163 | EmitUint8(0x0F); |
| 164 | EmitUint8(0xBC); |
| 165 | EmitRegisterOperand(dst, src); |
| 166 | } |
| 167 | |
| 168 | void X86Assembler::bsfl(Register dst, const Address& src) { |
| 169 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 170 | EmitUint8(0x0F); |
| 171 | EmitUint8(0xBC); |
| 172 | EmitOperand(dst, src); |
| 173 | } |
| 174 | |
Mark Mendell | 8ae3ffb | 2015-08-12 21:16:41 -0400 | [diff] [blame] | 175 | void X86Assembler::bsrl(Register dst, Register src) { |
| 176 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 177 | EmitUint8(0x0F); |
| 178 | EmitUint8(0xBD); |
| 179 | EmitRegisterOperand(dst, src); |
| 180 | } |
| 181 | |
| 182 | void X86Assembler::bsrl(Register dst, const Address& src) { |
| 183 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 184 | EmitUint8(0x0F); |
| 185 | EmitUint8(0xBD); |
| 186 | EmitOperand(dst, src); |
| 187 | } |
| 188 | |
Aart Bik | c39dac1 | 2016-01-21 08:59:48 -0800 | [diff] [blame] | 189 | void X86Assembler::popcntl(Register dst, Register src) { |
| 190 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 191 | EmitUint8(0xF3); |
| 192 | EmitUint8(0x0F); |
| 193 | EmitUint8(0xB8); |
| 194 | EmitRegisterOperand(dst, src); |
| 195 | } |
| 196 | |
| 197 | void X86Assembler::popcntl(Register dst, const Address& src) { |
| 198 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 199 | EmitUint8(0xF3); |
| 200 | EmitUint8(0x0F); |
| 201 | EmitUint8(0xB8); |
| 202 | EmitOperand(dst, src); |
| 203 | } |
| 204 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 205 | void X86Assembler::movzxb(Register dst, ByteRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 206 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 207 | EmitUint8(0x0F); |
| 208 | EmitUint8(0xB6); |
| 209 | EmitRegisterOperand(dst, src); |
| 210 | } |
| 211 | |
| 212 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 213 | void X86Assembler::movzxb(Register dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 214 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 215 | EmitUint8(0x0F); |
| 216 | EmitUint8(0xB6); |
| 217 | EmitOperand(dst, src); |
| 218 | } |
| 219 | |
| 220 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 221 | void X86Assembler::movsxb(Register dst, ByteRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 222 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 223 | EmitUint8(0x0F); |
| 224 | EmitUint8(0xBE); |
| 225 | EmitRegisterOperand(dst, src); |
| 226 | } |
| 227 | |
| 228 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 229 | void X86Assembler::movsxb(Register dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 230 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 231 | EmitUint8(0x0F); |
| 232 | EmitUint8(0xBE); |
| 233 | EmitOperand(dst, src); |
| 234 | } |
| 235 | |
| 236 | |
Elliott Hughes | 1bac54f | 2012-03-16 12:48:31 -0700 | [diff] [blame] | 237 | void X86Assembler::movb(Register /*dst*/, const Address& /*src*/) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 238 | LOG(FATAL) << "Use movzxb or movsxb instead."; |
| 239 | } |
| 240 | |
| 241 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 242 | void X86Assembler::movb(const Address& dst, ByteRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 243 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 244 | EmitUint8(0x88); |
| 245 | EmitOperand(src, dst); |
| 246 | } |
| 247 | |
| 248 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 249 | void X86Assembler::movb(const Address& dst, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 250 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 251 | EmitUint8(0xC6); |
| 252 | EmitOperand(EAX, dst); |
| 253 | CHECK(imm.is_int8()); |
| 254 | EmitUint8(imm.value() & 0xFF); |
| 255 | } |
| 256 | |
| 257 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 258 | void X86Assembler::movzxw(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 259 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 260 | EmitUint8(0x0F); |
| 261 | EmitUint8(0xB7); |
| 262 | EmitRegisterOperand(dst, src); |
| 263 | } |
| 264 | |
| 265 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 266 | void X86Assembler::movzxw(Register dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 267 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 268 | EmitUint8(0x0F); |
| 269 | EmitUint8(0xB7); |
| 270 | EmitOperand(dst, src); |
| 271 | } |
| 272 | |
| 273 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 274 | void X86Assembler::movsxw(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 275 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 276 | EmitUint8(0x0F); |
| 277 | EmitUint8(0xBF); |
| 278 | EmitRegisterOperand(dst, src); |
| 279 | } |
| 280 | |
| 281 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 282 | void X86Assembler::movsxw(Register dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 283 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 284 | EmitUint8(0x0F); |
| 285 | EmitUint8(0xBF); |
| 286 | EmitOperand(dst, src); |
| 287 | } |
| 288 | |
| 289 | |
Elliott Hughes | 1bac54f | 2012-03-16 12:48:31 -0700 | [diff] [blame] | 290 | void X86Assembler::movw(Register /*dst*/, const Address& /*src*/) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 291 | LOG(FATAL) << "Use movzxw or movsxw instead."; |
| 292 | } |
| 293 | |
| 294 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 295 | void X86Assembler::movw(const Address& dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 296 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 297 | EmitOperandSizeOverride(); |
| 298 | EmitUint8(0x89); |
| 299 | EmitOperand(src, dst); |
| 300 | } |
| 301 | |
| 302 | |
Nicolas Geoffray | 26a25ef | 2014-09-30 13:54:09 +0100 | [diff] [blame] | 303 | void X86Assembler::movw(const Address& dst, const Immediate& imm) { |
| 304 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 305 | EmitOperandSizeOverride(); |
| 306 | EmitUint8(0xC7); |
| 307 | EmitOperand(0, dst); |
Nicolas Geoffray | b6e7206 | 2014-10-07 14:54:48 +0100 | [diff] [blame] | 308 | CHECK(imm.is_uint16() || imm.is_int16()); |
Nicolas Geoffray | 26a25ef | 2014-09-30 13:54:09 +0100 | [diff] [blame] | 309 | EmitUint8(imm.value() & 0xFF); |
| 310 | EmitUint8(imm.value() >> 8); |
| 311 | } |
| 312 | |
| 313 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 314 | void X86Assembler::leal(Register dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 315 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 316 | EmitUint8(0x8D); |
| 317 | EmitOperand(dst, src); |
| 318 | } |
| 319 | |
| 320 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 321 | void X86Assembler::cmovl(Condition condition, Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 322 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 323 | EmitUint8(0x0F); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 324 | EmitUint8(0x40 + condition); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 325 | EmitRegisterOperand(dst, src); |
| 326 | } |
| 327 | |
| 328 | |
Mark Mendell | abdac47 | 2016-02-12 13:49:03 -0500 | [diff] [blame] | 329 | void X86Assembler::cmovl(Condition condition, Register dst, const Address& src) { |
| 330 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 331 | EmitUint8(0x0F); |
| 332 | EmitUint8(0x40 + condition); |
| 333 | EmitOperand(dst, src); |
| 334 | } |
| 335 | |
| 336 | |
Nicolas Geoffray | 5b4b898 | 2014-12-18 17:45:56 +0000 | [diff] [blame] | 337 | void X86Assembler::setb(Condition condition, Register dst) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 338 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 339 | EmitUint8(0x0F); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 340 | EmitUint8(0x90 + condition); |
Nicolas Geoffray | 5b4b898 | 2014-12-18 17:45:56 +0000 | [diff] [blame] | 341 | EmitOperand(0, Operand(dst)); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 342 | } |
| 343 | |
| 344 | |
Nicolas Geoffray | 7fb49da | 2014-10-06 09:12:41 +0100 | [diff] [blame] | 345 | void X86Assembler::movaps(XmmRegister dst, XmmRegister src) { |
| 346 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 347 | EmitUint8(0x0F); |
| 348 | EmitUint8(0x28); |
| 349 | EmitXmmRegisterOperand(dst, src); |
| 350 | } |
| 351 | |
| 352 | |
Aart Bik | c778226 | 2017-01-13 16:20:08 -0800 | [diff] [blame^] | 353 | void X86Assembler::movaps(XmmRegister dst, const Address& src) { |
| 354 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 355 | EmitUint8(0x0F); |
| 356 | EmitUint8(0x28); |
| 357 | EmitOperand(dst, src); |
| 358 | } |
| 359 | |
| 360 | |
| 361 | void X86Assembler::movups(XmmRegister dst, const Address& src) { |
| 362 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 363 | EmitUint8(0x0F); |
| 364 | EmitUint8(0x10); |
| 365 | EmitOperand(dst, src); |
| 366 | } |
| 367 | |
| 368 | |
| 369 | void X86Assembler::movaps(const Address& dst, XmmRegister src) { |
| 370 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 371 | EmitUint8(0x0F); |
| 372 | EmitUint8(0x29); |
| 373 | EmitOperand(src, dst); |
| 374 | } |
| 375 | |
| 376 | |
| 377 | void X86Assembler::movups(const Address& dst, XmmRegister src) { |
| 378 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 379 | EmitUint8(0x0F); |
| 380 | EmitUint8(0x11); |
| 381 | EmitOperand(src, dst); |
| 382 | } |
| 383 | |
| 384 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 385 | void X86Assembler::movss(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 386 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 387 | EmitUint8(0xF3); |
| 388 | EmitUint8(0x0F); |
| 389 | EmitUint8(0x10); |
| 390 | EmitOperand(dst, src); |
| 391 | } |
| 392 | |
| 393 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 394 | void X86Assembler::movss(const Address& dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 395 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 396 | EmitUint8(0xF3); |
| 397 | EmitUint8(0x0F); |
| 398 | EmitUint8(0x11); |
| 399 | EmitOperand(src, dst); |
| 400 | } |
| 401 | |
| 402 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 403 | void X86Assembler::movss(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 404 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 405 | EmitUint8(0xF3); |
| 406 | EmitUint8(0x0F); |
| 407 | EmitUint8(0x11); |
| 408 | EmitXmmRegisterOperand(src, dst); |
| 409 | } |
| 410 | |
| 411 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 412 | void X86Assembler::movd(XmmRegister dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 413 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 414 | EmitUint8(0x66); |
| 415 | EmitUint8(0x0F); |
| 416 | EmitUint8(0x6E); |
| 417 | EmitOperand(dst, Operand(src)); |
| 418 | } |
| 419 | |
| 420 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 421 | void X86Assembler::movd(Register dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 422 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 423 | EmitUint8(0x66); |
| 424 | EmitUint8(0x0F); |
| 425 | EmitUint8(0x7E); |
| 426 | EmitOperand(src, Operand(dst)); |
| 427 | } |
| 428 | |
| 429 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 430 | void X86Assembler::addss(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 431 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 432 | EmitUint8(0xF3); |
| 433 | EmitUint8(0x0F); |
| 434 | EmitUint8(0x58); |
| 435 | EmitXmmRegisterOperand(dst, src); |
| 436 | } |
| 437 | |
| 438 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 439 | void X86Assembler::addss(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 440 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 441 | EmitUint8(0xF3); |
| 442 | EmitUint8(0x0F); |
| 443 | EmitUint8(0x58); |
| 444 | EmitOperand(dst, src); |
| 445 | } |
| 446 | |
| 447 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 448 | void X86Assembler::subss(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 449 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 450 | EmitUint8(0xF3); |
| 451 | EmitUint8(0x0F); |
| 452 | EmitUint8(0x5C); |
| 453 | EmitXmmRegisterOperand(dst, src); |
| 454 | } |
| 455 | |
| 456 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 457 | void X86Assembler::subss(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 458 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 459 | EmitUint8(0xF3); |
| 460 | EmitUint8(0x0F); |
| 461 | EmitUint8(0x5C); |
| 462 | EmitOperand(dst, src); |
| 463 | } |
| 464 | |
| 465 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 466 | void X86Assembler::mulss(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 467 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 468 | EmitUint8(0xF3); |
| 469 | EmitUint8(0x0F); |
| 470 | EmitUint8(0x59); |
| 471 | EmitXmmRegisterOperand(dst, src); |
| 472 | } |
| 473 | |
| 474 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 475 | void X86Assembler::mulss(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 476 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 477 | EmitUint8(0xF3); |
| 478 | EmitUint8(0x0F); |
| 479 | EmitUint8(0x59); |
| 480 | EmitOperand(dst, src); |
| 481 | } |
| 482 | |
| 483 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 484 | void X86Assembler::divss(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 485 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 486 | EmitUint8(0xF3); |
| 487 | EmitUint8(0x0F); |
| 488 | EmitUint8(0x5E); |
| 489 | EmitXmmRegisterOperand(dst, src); |
| 490 | } |
| 491 | |
| 492 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 493 | void X86Assembler::divss(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 494 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 495 | EmitUint8(0xF3); |
| 496 | EmitUint8(0x0F); |
| 497 | EmitUint8(0x5E); |
| 498 | EmitOperand(dst, src); |
| 499 | } |
| 500 | |
| 501 | |
Aart Bik | c778226 | 2017-01-13 16:20:08 -0800 | [diff] [blame^] | 502 | void X86Assembler::addps(XmmRegister dst, XmmRegister src) { |
| 503 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 504 | EmitUint8(0x0F); |
| 505 | EmitUint8(0x58); |
| 506 | EmitXmmRegisterOperand(dst, src); |
| 507 | } |
| 508 | |
| 509 | |
| 510 | void X86Assembler::subps(XmmRegister dst, XmmRegister src) { |
| 511 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 512 | EmitUint8(0x0F); |
| 513 | EmitUint8(0x5C); |
| 514 | EmitXmmRegisterOperand(dst, src); |
| 515 | } |
| 516 | |
| 517 | |
| 518 | void X86Assembler::mulps(XmmRegister dst, XmmRegister src) { |
| 519 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 520 | EmitUint8(0x0F); |
| 521 | EmitUint8(0x59); |
| 522 | EmitXmmRegisterOperand(dst, src); |
| 523 | } |
| 524 | |
| 525 | |
| 526 | void X86Assembler::divps(XmmRegister dst, XmmRegister src) { |
| 527 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 528 | EmitUint8(0x0F); |
| 529 | EmitUint8(0x5E); |
| 530 | EmitXmmRegisterOperand(dst, src); |
| 531 | } |
| 532 | |
| 533 | |
| 534 | void X86Assembler::movapd(XmmRegister dst, XmmRegister src) { |
| 535 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 536 | EmitUint8(0x66); |
| 537 | EmitUint8(0x0F); |
| 538 | EmitUint8(0x28); |
| 539 | EmitXmmRegisterOperand(dst, src); |
| 540 | } |
| 541 | |
| 542 | |
| 543 | void X86Assembler::movapd(XmmRegister dst, const Address& src) { |
| 544 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 545 | EmitUint8(0x66); |
| 546 | EmitUint8(0x0F); |
| 547 | EmitUint8(0x28); |
| 548 | EmitOperand(dst, src); |
| 549 | } |
| 550 | |
| 551 | |
| 552 | void X86Assembler::movupd(XmmRegister dst, const Address& src) { |
| 553 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 554 | EmitUint8(0x66); |
| 555 | EmitUint8(0x0F); |
| 556 | EmitUint8(0x10); |
| 557 | EmitOperand(dst, src); |
| 558 | } |
| 559 | |
| 560 | |
| 561 | void X86Assembler::movapd(const Address& dst, XmmRegister src) { |
| 562 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 563 | EmitUint8(0x66); |
| 564 | EmitUint8(0x0F); |
| 565 | EmitUint8(0x29); |
| 566 | EmitOperand(src, dst); |
| 567 | } |
| 568 | |
| 569 | |
| 570 | void X86Assembler::movupd(const Address& dst, XmmRegister src) { |
| 571 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 572 | EmitUint8(0x66); |
| 573 | EmitUint8(0x0F); |
| 574 | EmitUint8(0x11); |
| 575 | EmitOperand(src, dst); |
| 576 | } |
| 577 | |
| 578 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 579 | void X86Assembler::flds(const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 580 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 581 | EmitUint8(0xD9); |
| 582 | EmitOperand(0, src); |
| 583 | } |
| 584 | |
| 585 | |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 586 | void X86Assembler::fsts(const Address& dst) { |
| 587 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 588 | EmitUint8(0xD9); |
| 589 | EmitOperand(2, dst); |
| 590 | } |
| 591 | |
| 592 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 593 | void X86Assembler::fstps(const Address& dst) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 594 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 595 | EmitUint8(0xD9); |
| 596 | EmitOperand(3, dst); |
| 597 | } |
| 598 | |
| 599 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 600 | void X86Assembler::movsd(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 601 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 602 | EmitUint8(0xF2); |
| 603 | EmitUint8(0x0F); |
| 604 | EmitUint8(0x10); |
| 605 | EmitOperand(dst, src); |
| 606 | } |
| 607 | |
| 608 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 609 | void X86Assembler::movsd(const Address& dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 610 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 611 | EmitUint8(0xF2); |
| 612 | EmitUint8(0x0F); |
| 613 | EmitUint8(0x11); |
| 614 | EmitOperand(src, dst); |
| 615 | } |
| 616 | |
| 617 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 618 | void X86Assembler::movsd(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 619 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 620 | EmitUint8(0xF2); |
| 621 | EmitUint8(0x0F); |
| 622 | EmitUint8(0x11); |
| 623 | EmitXmmRegisterOperand(src, dst); |
| 624 | } |
| 625 | |
| 626 | |
Nicolas Geoffray | 234d69d | 2015-03-09 10:28:50 +0000 | [diff] [blame] | 627 | void X86Assembler::movhpd(XmmRegister dst, const Address& src) { |
| 628 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 629 | EmitUint8(0x66); |
| 630 | EmitUint8(0x0F); |
| 631 | EmitUint8(0x16); |
| 632 | EmitOperand(dst, src); |
| 633 | } |
| 634 | |
| 635 | |
| 636 | void X86Assembler::movhpd(const Address& dst, XmmRegister src) { |
| 637 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 638 | EmitUint8(0x66); |
| 639 | EmitUint8(0x0F); |
| 640 | EmitUint8(0x17); |
| 641 | EmitOperand(src, dst); |
| 642 | } |
| 643 | |
| 644 | |
| 645 | void X86Assembler::psrldq(XmmRegister reg, const Immediate& shift_count) { |
| 646 | DCHECK(shift_count.is_uint8()); |
| 647 | |
| 648 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 649 | EmitUint8(0x66); |
| 650 | EmitUint8(0x0F); |
| 651 | EmitUint8(0x73); |
| 652 | EmitXmmRegisterOperand(3, reg); |
| 653 | EmitUint8(shift_count.value()); |
| 654 | } |
| 655 | |
| 656 | |
Calin Juravle | 52c4896 | 2014-12-16 17:02:57 +0000 | [diff] [blame] | 657 | void X86Assembler::psrlq(XmmRegister reg, const Immediate& shift_count) { |
| 658 | DCHECK(shift_count.is_uint8()); |
| 659 | |
| 660 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 661 | EmitUint8(0x66); |
| 662 | EmitUint8(0x0F); |
| 663 | EmitUint8(0x73); |
| 664 | EmitXmmRegisterOperand(2, reg); |
| 665 | EmitUint8(shift_count.value()); |
| 666 | } |
| 667 | |
| 668 | |
| 669 | void X86Assembler::punpckldq(XmmRegister dst, XmmRegister src) { |
| 670 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 671 | EmitUint8(0x66); |
| 672 | EmitUint8(0x0F); |
| 673 | EmitUint8(0x62); |
| 674 | EmitXmmRegisterOperand(dst, src); |
| 675 | } |
| 676 | |
| 677 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 678 | void X86Assembler::addsd(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 679 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 680 | EmitUint8(0xF2); |
| 681 | EmitUint8(0x0F); |
| 682 | EmitUint8(0x58); |
| 683 | EmitXmmRegisterOperand(dst, src); |
| 684 | } |
| 685 | |
| 686 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 687 | void X86Assembler::addsd(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 688 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 689 | EmitUint8(0xF2); |
| 690 | EmitUint8(0x0F); |
| 691 | EmitUint8(0x58); |
| 692 | EmitOperand(dst, src); |
| 693 | } |
| 694 | |
| 695 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 696 | void X86Assembler::subsd(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 697 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 698 | EmitUint8(0xF2); |
| 699 | EmitUint8(0x0F); |
| 700 | EmitUint8(0x5C); |
| 701 | EmitXmmRegisterOperand(dst, src); |
| 702 | } |
| 703 | |
| 704 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 705 | void X86Assembler::subsd(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 706 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 707 | EmitUint8(0xF2); |
| 708 | EmitUint8(0x0F); |
| 709 | EmitUint8(0x5C); |
| 710 | EmitOperand(dst, src); |
| 711 | } |
| 712 | |
| 713 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 714 | void X86Assembler::mulsd(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 715 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 716 | EmitUint8(0xF2); |
| 717 | EmitUint8(0x0F); |
| 718 | EmitUint8(0x59); |
| 719 | EmitXmmRegisterOperand(dst, src); |
| 720 | } |
| 721 | |
| 722 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 723 | void X86Assembler::mulsd(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 724 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 725 | EmitUint8(0xF2); |
| 726 | EmitUint8(0x0F); |
| 727 | EmitUint8(0x59); |
| 728 | EmitOperand(dst, src); |
| 729 | } |
| 730 | |
| 731 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 732 | void X86Assembler::divsd(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 733 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 734 | EmitUint8(0xF2); |
| 735 | EmitUint8(0x0F); |
| 736 | EmitUint8(0x5E); |
| 737 | EmitXmmRegisterOperand(dst, src); |
| 738 | } |
| 739 | |
| 740 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 741 | void X86Assembler::divsd(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 742 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 743 | EmitUint8(0xF2); |
| 744 | EmitUint8(0x0F); |
| 745 | EmitUint8(0x5E); |
| 746 | EmitOperand(dst, src); |
| 747 | } |
| 748 | |
| 749 | |
Aart Bik | c778226 | 2017-01-13 16:20:08 -0800 | [diff] [blame^] | 750 | void X86Assembler::addpd(XmmRegister dst, XmmRegister src) { |
| 751 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 752 | EmitUint8(0x66); |
| 753 | EmitUint8(0x0F); |
| 754 | EmitUint8(0x58); |
| 755 | EmitXmmRegisterOperand(dst, src); |
| 756 | } |
| 757 | |
| 758 | |
| 759 | void X86Assembler::subpd(XmmRegister dst, XmmRegister src) { |
| 760 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 761 | EmitUint8(0x66); |
| 762 | EmitUint8(0x0F); |
| 763 | EmitUint8(0x5C); |
| 764 | EmitXmmRegisterOperand(dst, src); |
| 765 | } |
| 766 | |
| 767 | |
| 768 | void X86Assembler::mulpd(XmmRegister dst, XmmRegister src) { |
| 769 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 770 | EmitUint8(0x66); |
| 771 | EmitUint8(0x0F); |
| 772 | EmitUint8(0x59); |
| 773 | EmitXmmRegisterOperand(dst, src); |
| 774 | } |
| 775 | |
| 776 | |
| 777 | void X86Assembler::divpd(XmmRegister dst, XmmRegister src) { |
| 778 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 779 | EmitUint8(0x66); |
| 780 | EmitUint8(0x0F); |
| 781 | EmitUint8(0x5E); |
| 782 | EmitXmmRegisterOperand(dst, src); |
| 783 | } |
| 784 | |
| 785 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 786 | void X86Assembler::cvtsi2ss(XmmRegister dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 787 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 788 | EmitUint8(0xF3); |
| 789 | EmitUint8(0x0F); |
| 790 | EmitUint8(0x2A); |
| 791 | EmitOperand(dst, Operand(src)); |
| 792 | } |
| 793 | |
| 794 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 795 | void X86Assembler::cvtsi2sd(XmmRegister dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 796 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 797 | EmitUint8(0xF2); |
| 798 | EmitUint8(0x0F); |
| 799 | EmitUint8(0x2A); |
| 800 | EmitOperand(dst, Operand(src)); |
| 801 | } |
| 802 | |
| 803 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 804 | void X86Assembler::cvtss2si(Register dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 805 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 806 | EmitUint8(0xF3); |
| 807 | EmitUint8(0x0F); |
| 808 | EmitUint8(0x2D); |
| 809 | EmitXmmRegisterOperand(dst, src); |
| 810 | } |
| 811 | |
| 812 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 813 | void X86Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 814 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 815 | EmitUint8(0xF3); |
| 816 | EmitUint8(0x0F); |
| 817 | EmitUint8(0x5A); |
| 818 | EmitXmmRegisterOperand(dst, src); |
| 819 | } |
| 820 | |
| 821 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 822 | void X86Assembler::cvtsd2si(Register dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 823 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 824 | EmitUint8(0xF2); |
| 825 | EmitUint8(0x0F); |
| 826 | EmitUint8(0x2D); |
| 827 | EmitXmmRegisterOperand(dst, src); |
| 828 | } |
| 829 | |
| 830 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 831 | void X86Assembler::cvttss2si(Register dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 832 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 833 | EmitUint8(0xF3); |
| 834 | EmitUint8(0x0F); |
| 835 | EmitUint8(0x2C); |
| 836 | EmitXmmRegisterOperand(dst, src); |
| 837 | } |
| 838 | |
| 839 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 840 | void X86Assembler::cvttsd2si(Register dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 841 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 842 | EmitUint8(0xF2); |
| 843 | EmitUint8(0x0F); |
| 844 | EmitUint8(0x2C); |
| 845 | EmitXmmRegisterOperand(dst, src); |
| 846 | } |
| 847 | |
| 848 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 849 | void X86Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 850 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 851 | EmitUint8(0xF2); |
| 852 | EmitUint8(0x0F); |
| 853 | EmitUint8(0x5A); |
| 854 | EmitXmmRegisterOperand(dst, src); |
| 855 | } |
| 856 | |
| 857 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 858 | void X86Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 859 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 860 | EmitUint8(0xF3); |
| 861 | EmitUint8(0x0F); |
| 862 | EmitUint8(0xE6); |
| 863 | EmitXmmRegisterOperand(dst, src); |
| 864 | } |
| 865 | |
| 866 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 867 | void X86Assembler::comiss(XmmRegister a, XmmRegister b) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 868 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 869 | EmitUint8(0x0F); |
| 870 | EmitUint8(0x2F); |
| 871 | EmitXmmRegisterOperand(a, b); |
| 872 | } |
| 873 | |
| 874 | |
Aart Bik | 18ba121 | 2016-08-01 14:11:20 -0700 | [diff] [blame] | 875 | void X86Assembler::comiss(XmmRegister a, const Address& b) { |
| 876 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 877 | EmitUint8(0x0F); |
| 878 | EmitUint8(0x2F); |
| 879 | EmitOperand(a, b); |
| 880 | } |
| 881 | |
| 882 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 883 | void X86Assembler::comisd(XmmRegister a, XmmRegister b) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 884 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 885 | EmitUint8(0x66); |
| 886 | EmitUint8(0x0F); |
| 887 | EmitUint8(0x2F); |
| 888 | EmitXmmRegisterOperand(a, b); |
| 889 | } |
| 890 | |
| 891 | |
Aart Bik | 18ba121 | 2016-08-01 14:11:20 -0700 | [diff] [blame] | 892 | void X86Assembler::comisd(XmmRegister a, const Address& b) { |
| 893 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 894 | EmitUint8(0x66); |
| 895 | EmitUint8(0x0F); |
| 896 | EmitUint8(0x2F); |
| 897 | EmitOperand(a, b); |
| 898 | } |
| 899 | |
| 900 | |
Calin Juravle | ddb7df2 | 2014-11-25 20:56:51 +0000 | [diff] [blame] | 901 | void X86Assembler::ucomiss(XmmRegister a, XmmRegister b) { |
| 902 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 903 | EmitUint8(0x0F); |
| 904 | EmitUint8(0x2E); |
| 905 | EmitXmmRegisterOperand(a, b); |
| 906 | } |
| 907 | |
| 908 | |
Mark Mendell | 9f51f26 | 2015-10-30 09:21:37 -0400 | [diff] [blame] | 909 | void X86Assembler::ucomiss(XmmRegister a, const Address& b) { |
| 910 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 911 | EmitUint8(0x0F); |
| 912 | EmitUint8(0x2E); |
| 913 | EmitOperand(a, b); |
| 914 | } |
| 915 | |
| 916 | |
Calin Juravle | ddb7df2 | 2014-11-25 20:56:51 +0000 | [diff] [blame] | 917 | void X86Assembler::ucomisd(XmmRegister a, XmmRegister b) { |
| 918 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 919 | EmitUint8(0x66); |
| 920 | EmitUint8(0x0F); |
| 921 | EmitUint8(0x2E); |
| 922 | EmitXmmRegisterOperand(a, b); |
| 923 | } |
| 924 | |
| 925 | |
Mark Mendell | 9f51f26 | 2015-10-30 09:21:37 -0400 | [diff] [blame] | 926 | void X86Assembler::ucomisd(XmmRegister a, const Address& b) { |
| 927 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 928 | EmitUint8(0x66); |
| 929 | EmitUint8(0x0F); |
| 930 | EmitUint8(0x2E); |
| 931 | EmitOperand(a, b); |
| 932 | } |
| 933 | |
| 934 | |
Mark Mendell | fb8d279 | 2015-03-31 22:16:59 -0400 | [diff] [blame] | 935 | void X86Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) { |
| 936 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 937 | EmitUint8(0x66); |
| 938 | EmitUint8(0x0F); |
| 939 | EmitUint8(0x3A); |
| 940 | EmitUint8(0x0B); |
| 941 | EmitXmmRegisterOperand(dst, src); |
| 942 | EmitUint8(imm.value()); |
| 943 | } |
| 944 | |
| 945 | |
| 946 | void X86Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) { |
| 947 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 948 | EmitUint8(0x66); |
| 949 | EmitUint8(0x0F); |
| 950 | EmitUint8(0x3A); |
| 951 | EmitUint8(0x0A); |
| 952 | EmitXmmRegisterOperand(dst, src); |
| 953 | EmitUint8(imm.value()); |
| 954 | } |
| 955 | |
| 956 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 957 | void X86Assembler::sqrtsd(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 958 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 959 | EmitUint8(0xF2); |
| 960 | EmitUint8(0x0F); |
| 961 | EmitUint8(0x51); |
| 962 | EmitXmmRegisterOperand(dst, src); |
| 963 | } |
| 964 | |
| 965 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 966 | void X86Assembler::sqrtss(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 967 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 968 | EmitUint8(0xF3); |
| 969 | EmitUint8(0x0F); |
| 970 | EmitUint8(0x51); |
| 971 | EmitXmmRegisterOperand(dst, src); |
| 972 | } |
| 973 | |
| 974 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 975 | void X86Assembler::xorpd(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 976 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 977 | EmitUint8(0x66); |
| 978 | EmitUint8(0x0F); |
| 979 | EmitUint8(0x57); |
| 980 | EmitOperand(dst, src); |
| 981 | } |
| 982 | |
| 983 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 984 | void X86Assembler::xorpd(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 985 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 986 | EmitUint8(0x66); |
| 987 | EmitUint8(0x0F); |
| 988 | EmitUint8(0x57); |
| 989 | EmitXmmRegisterOperand(dst, src); |
| 990 | } |
| 991 | |
| 992 | |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 993 | void X86Assembler::andps(XmmRegister dst, XmmRegister src) { |
| 994 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 995 | EmitUint8(0x0F); |
| 996 | EmitUint8(0x54); |
| 997 | EmitXmmRegisterOperand(dst, src); |
| 998 | } |
| 999 | |
| 1000 | |
| 1001 | void X86Assembler::andpd(XmmRegister dst, XmmRegister src) { |
| 1002 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1003 | EmitUint8(0x66); |
| 1004 | EmitUint8(0x0F); |
| 1005 | EmitUint8(0x54); |
| 1006 | EmitXmmRegisterOperand(dst, src); |
| 1007 | } |
| 1008 | |
| 1009 | |
| 1010 | void X86Assembler::orpd(XmmRegister dst, XmmRegister src) { |
| 1011 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1012 | EmitUint8(0x66); |
| 1013 | EmitUint8(0x0F); |
| 1014 | EmitUint8(0x56); |
| 1015 | EmitXmmRegisterOperand(dst, src); |
| 1016 | } |
| 1017 | |
| 1018 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1019 | void X86Assembler::xorps(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1020 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1021 | EmitUint8(0x0F); |
| 1022 | EmitUint8(0x57); |
| 1023 | EmitOperand(dst, src); |
| 1024 | } |
| 1025 | |
| 1026 | |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 1027 | void X86Assembler::orps(XmmRegister dst, XmmRegister src) { |
| 1028 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1029 | EmitUint8(0x0F); |
| 1030 | EmitUint8(0x56); |
| 1031 | EmitXmmRegisterOperand(dst, src); |
| 1032 | } |
| 1033 | |
| 1034 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1035 | void X86Assembler::xorps(XmmRegister dst, XmmRegister src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1036 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1037 | EmitUint8(0x0F); |
| 1038 | EmitUint8(0x57); |
| 1039 | EmitXmmRegisterOperand(dst, src); |
| 1040 | } |
| 1041 | |
| 1042 | |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 1043 | void X86Assembler::andps(XmmRegister dst, const Address& src) { |
| 1044 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1045 | EmitUint8(0x0F); |
| 1046 | EmitUint8(0x54); |
| 1047 | EmitOperand(dst, src); |
| 1048 | } |
| 1049 | |
| 1050 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1051 | void X86Assembler::andpd(XmmRegister dst, const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1052 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1053 | EmitUint8(0x66); |
| 1054 | EmitUint8(0x0F); |
| 1055 | EmitUint8(0x54); |
| 1056 | EmitOperand(dst, src); |
| 1057 | } |
| 1058 | |
| 1059 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1060 | void X86Assembler::fldl(const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1061 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1062 | EmitUint8(0xDD); |
| 1063 | EmitOperand(0, src); |
| 1064 | } |
| 1065 | |
| 1066 | |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 1067 | void X86Assembler::fstl(const Address& dst) { |
| 1068 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1069 | EmitUint8(0xDD); |
| 1070 | EmitOperand(2, dst); |
| 1071 | } |
| 1072 | |
| 1073 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1074 | void X86Assembler::fstpl(const Address& dst) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1075 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1076 | EmitUint8(0xDD); |
| 1077 | EmitOperand(3, dst); |
| 1078 | } |
| 1079 | |
| 1080 | |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 1081 | void X86Assembler::fstsw() { |
| 1082 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1083 | EmitUint8(0x9B); |
| 1084 | EmitUint8(0xDF); |
| 1085 | EmitUint8(0xE0); |
| 1086 | } |
| 1087 | |
| 1088 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1089 | void X86Assembler::fnstcw(const Address& dst) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1090 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1091 | EmitUint8(0xD9); |
| 1092 | EmitOperand(7, dst); |
| 1093 | } |
| 1094 | |
| 1095 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1096 | void X86Assembler::fldcw(const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1097 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1098 | EmitUint8(0xD9); |
| 1099 | EmitOperand(5, src); |
| 1100 | } |
| 1101 | |
| 1102 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1103 | void X86Assembler::fistpl(const Address& dst) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1104 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1105 | EmitUint8(0xDF); |
| 1106 | EmitOperand(7, dst); |
| 1107 | } |
| 1108 | |
| 1109 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1110 | void X86Assembler::fistps(const Address& dst) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1111 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1112 | EmitUint8(0xDB); |
| 1113 | EmitOperand(3, dst); |
| 1114 | } |
| 1115 | |
| 1116 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1117 | void X86Assembler::fildl(const Address& src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1118 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1119 | EmitUint8(0xDF); |
| 1120 | EmitOperand(5, src); |
| 1121 | } |
| 1122 | |
| 1123 | |
Roland Levillain | 0a18601 | 2015-04-13 17:00:20 +0100 | [diff] [blame] | 1124 | void X86Assembler::filds(const Address& src) { |
| 1125 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1126 | EmitUint8(0xDB); |
| 1127 | EmitOperand(0, src); |
| 1128 | } |
| 1129 | |
| 1130 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1131 | void X86Assembler::fincstp() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1132 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1133 | EmitUint8(0xD9); |
| 1134 | EmitUint8(0xF7); |
| 1135 | } |
| 1136 | |
| 1137 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1138 | void X86Assembler::ffree(const Immediate& index) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1139 | CHECK_LT(index.value(), 7); |
| 1140 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1141 | EmitUint8(0xDD); |
| 1142 | EmitUint8(0xC0 + index.value()); |
| 1143 | } |
| 1144 | |
| 1145 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1146 | void X86Assembler::fsin() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1147 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1148 | EmitUint8(0xD9); |
| 1149 | EmitUint8(0xFE); |
| 1150 | } |
| 1151 | |
| 1152 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1153 | void X86Assembler::fcos() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1154 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1155 | EmitUint8(0xD9); |
| 1156 | EmitUint8(0xFF); |
| 1157 | } |
| 1158 | |
| 1159 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1160 | void X86Assembler::fptan() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1161 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1162 | EmitUint8(0xD9); |
| 1163 | EmitUint8(0xF2); |
| 1164 | } |
| 1165 | |
| 1166 | |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 1167 | void X86Assembler::fucompp() { |
| 1168 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1169 | EmitUint8(0xDA); |
| 1170 | EmitUint8(0xE9); |
| 1171 | } |
| 1172 | |
| 1173 | |
| 1174 | void X86Assembler::fprem() { |
| 1175 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1176 | EmitUint8(0xD9); |
| 1177 | EmitUint8(0xF8); |
| 1178 | } |
| 1179 | |
| 1180 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1181 | void X86Assembler::xchgl(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1182 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1183 | EmitUint8(0x87); |
| 1184 | EmitRegisterOperand(dst, src); |
| 1185 | } |
| 1186 | |
Nicolas Geoffray | 3c04974 | 2014-09-24 18:10:46 +0100 | [diff] [blame] | 1187 | |
Ian Rogers | 7caad77 | 2012-03-30 01:07:54 -0700 | [diff] [blame] | 1188 | void X86Assembler::xchgl(Register reg, const Address& address) { |
| 1189 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1190 | EmitUint8(0x87); |
| 1191 | EmitOperand(reg, address); |
| 1192 | } |
| 1193 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1194 | |
Serguei Katkov | 3b62593 | 2016-05-06 10:24:17 +0600 | [diff] [blame] | 1195 | void X86Assembler::cmpb(const Address& address, const Immediate& imm) { |
| 1196 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1197 | EmitUint8(0x80); |
| 1198 | EmitOperand(7, address); |
| 1199 | EmitUint8(imm.value() & 0xFF); |
| 1200 | } |
| 1201 | |
| 1202 | |
Nicolas Geoffray | 3c04974 | 2014-09-24 18:10:46 +0100 | [diff] [blame] | 1203 | void X86Assembler::cmpw(const Address& address, const Immediate& imm) { |
| 1204 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1205 | EmitUint8(0x66); |
| 1206 | EmitComplex(7, address, imm); |
| 1207 | } |
| 1208 | |
| 1209 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1210 | void X86Assembler::cmpl(Register reg, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1211 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1212 | EmitComplex(7, Operand(reg), imm); |
| 1213 | } |
| 1214 | |
| 1215 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1216 | void X86Assembler::cmpl(Register reg0, Register reg1) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1217 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1218 | EmitUint8(0x3B); |
| 1219 | EmitOperand(reg0, Operand(reg1)); |
| 1220 | } |
| 1221 | |
| 1222 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1223 | void X86Assembler::cmpl(Register reg, const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1224 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1225 | EmitUint8(0x3B); |
| 1226 | EmitOperand(reg, address); |
| 1227 | } |
| 1228 | |
| 1229 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1230 | void X86Assembler::addl(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1231 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1232 | EmitUint8(0x03); |
| 1233 | EmitRegisterOperand(dst, src); |
| 1234 | } |
| 1235 | |
| 1236 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1237 | void X86Assembler::addl(Register reg, const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1238 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1239 | EmitUint8(0x03); |
| 1240 | EmitOperand(reg, address); |
| 1241 | } |
| 1242 | |
| 1243 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1244 | void X86Assembler::cmpl(const Address& address, Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1245 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1246 | EmitUint8(0x39); |
| 1247 | EmitOperand(reg, address); |
| 1248 | } |
| 1249 | |
| 1250 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1251 | void X86Assembler::cmpl(const Address& address, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1252 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1253 | EmitComplex(7, address, imm); |
| 1254 | } |
| 1255 | |
| 1256 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1257 | void X86Assembler::testl(Register reg1, Register reg2) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1258 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1259 | EmitUint8(0x85); |
| 1260 | EmitRegisterOperand(reg1, reg2); |
| 1261 | } |
| 1262 | |
| 1263 | |
Nicolas Geoffray | f12feb8 | 2014-07-17 18:32:41 +0100 | [diff] [blame] | 1264 | void X86Assembler::testl(Register reg, const Address& address) { |
| 1265 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1266 | EmitUint8(0x85); |
| 1267 | EmitOperand(reg, address); |
| 1268 | } |
| 1269 | |
| 1270 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1271 | void X86Assembler::testl(Register reg, const Immediate& immediate) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1272 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1273 | // For registers that have a byte variant (EAX, EBX, ECX, and EDX) |
| 1274 | // we only test the byte register to keep the encoding short. |
| 1275 | if (immediate.is_uint8() && reg < 4) { |
| 1276 | // Use zero-extended 8-bit immediate. |
| 1277 | if (reg == EAX) { |
| 1278 | EmitUint8(0xA8); |
| 1279 | } else { |
| 1280 | EmitUint8(0xF6); |
| 1281 | EmitUint8(0xC0 + reg); |
| 1282 | } |
| 1283 | EmitUint8(immediate.value() & 0xFF); |
| 1284 | } else if (reg == EAX) { |
| 1285 | // Use short form if the destination is EAX. |
| 1286 | EmitUint8(0xA9); |
| 1287 | EmitImmediate(immediate); |
| 1288 | } else { |
| 1289 | EmitUint8(0xF7); |
| 1290 | EmitOperand(0, Operand(reg)); |
| 1291 | EmitImmediate(immediate); |
| 1292 | } |
| 1293 | } |
| 1294 | |
| 1295 | |
Vladimir Marko | 953437b | 2016-08-24 08:30:46 +0000 | [diff] [blame] | 1296 | void X86Assembler::testb(const Address& dst, const Immediate& imm) { |
| 1297 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1298 | EmitUint8(0xF6); |
| 1299 | EmitOperand(EAX, dst); |
| 1300 | CHECK(imm.is_int8()); |
| 1301 | EmitUint8(imm.value() & 0xFF); |
| 1302 | } |
| 1303 | |
| 1304 | |
| 1305 | void X86Assembler::testl(const Address& dst, const Immediate& imm) { |
| 1306 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1307 | EmitUint8(0xF7); |
| 1308 | EmitOperand(0, dst); |
| 1309 | EmitImmediate(imm); |
| 1310 | } |
| 1311 | |
| 1312 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1313 | void X86Assembler::andl(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1314 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1315 | EmitUint8(0x23); |
| 1316 | EmitOperand(dst, Operand(src)); |
| 1317 | } |
| 1318 | |
| 1319 | |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 1320 | void X86Assembler::andl(Register reg, const Address& address) { |
| 1321 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1322 | EmitUint8(0x23); |
| 1323 | EmitOperand(reg, address); |
| 1324 | } |
| 1325 | |
| 1326 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1327 | void X86Assembler::andl(Register dst, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1328 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1329 | EmitComplex(4, Operand(dst), imm); |
| 1330 | } |
| 1331 | |
| 1332 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1333 | void X86Assembler::orl(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1334 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1335 | EmitUint8(0x0B); |
| 1336 | EmitOperand(dst, Operand(src)); |
| 1337 | } |
| 1338 | |
| 1339 | |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 1340 | void X86Assembler::orl(Register reg, const Address& address) { |
| 1341 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1342 | EmitUint8(0x0B); |
| 1343 | EmitOperand(reg, address); |
| 1344 | } |
| 1345 | |
| 1346 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1347 | void X86Assembler::orl(Register dst, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1348 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1349 | EmitComplex(1, Operand(dst), imm); |
| 1350 | } |
| 1351 | |
| 1352 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1353 | void X86Assembler::xorl(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1354 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1355 | EmitUint8(0x33); |
| 1356 | EmitOperand(dst, Operand(src)); |
| 1357 | } |
| 1358 | |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 1359 | |
| 1360 | void X86Assembler::xorl(Register reg, const Address& address) { |
| 1361 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1362 | EmitUint8(0x33); |
| 1363 | EmitOperand(reg, address); |
| 1364 | } |
| 1365 | |
| 1366 | |
Nicolas Geoffray | b55f835 | 2014-04-07 15:26:35 +0100 | [diff] [blame] | 1367 | void X86Assembler::xorl(Register dst, const Immediate& imm) { |
| 1368 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1369 | EmitComplex(6, Operand(dst), imm); |
| 1370 | } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1371 | |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 1372 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1373 | void X86Assembler::addl(Register reg, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1374 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1375 | EmitComplex(0, Operand(reg), imm); |
| 1376 | } |
| 1377 | |
| 1378 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1379 | void X86Assembler::addl(const Address& address, Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1380 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1381 | EmitUint8(0x01); |
| 1382 | EmitOperand(reg, address); |
| 1383 | } |
| 1384 | |
| 1385 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1386 | void X86Assembler::addl(const Address& address, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1387 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1388 | EmitComplex(0, address, imm); |
| 1389 | } |
| 1390 | |
| 1391 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1392 | void X86Assembler::adcl(Register reg, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1393 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1394 | EmitComplex(2, Operand(reg), imm); |
| 1395 | } |
| 1396 | |
| 1397 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1398 | void X86Assembler::adcl(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1399 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1400 | EmitUint8(0x13); |
| 1401 | EmitOperand(dst, Operand(src)); |
| 1402 | } |
| 1403 | |
| 1404 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1405 | void X86Assembler::adcl(Register dst, const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1406 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1407 | EmitUint8(0x13); |
| 1408 | EmitOperand(dst, address); |
| 1409 | } |
| 1410 | |
| 1411 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1412 | void X86Assembler::subl(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1413 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1414 | EmitUint8(0x2B); |
| 1415 | EmitOperand(dst, Operand(src)); |
| 1416 | } |
| 1417 | |
| 1418 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1419 | void X86Assembler::subl(Register reg, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1420 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1421 | EmitComplex(5, Operand(reg), imm); |
| 1422 | } |
| 1423 | |
| 1424 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1425 | void X86Assembler::subl(Register reg, const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1426 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1427 | EmitUint8(0x2B); |
| 1428 | EmitOperand(reg, address); |
| 1429 | } |
| 1430 | |
| 1431 | |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 1432 | void X86Assembler::subl(const Address& address, Register reg) { |
| 1433 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1434 | EmitUint8(0x29); |
| 1435 | EmitOperand(reg, address); |
| 1436 | } |
| 1437 | |
| 1438 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1439 | void X86Assembler::cdq() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1440 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1441 | EmitUint8(0x99); |
| 1442 | } |
| 1443 | |
| 1444 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1445 | void X86Assembler::idivl(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1446 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1447 | EmitUint8(0xF7); |
| 1448 | EmitUint8(0xF8 | reg); |
| 1449 | } |
| 1450 | |
| 1451 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1452 | void X86Assembler::imull(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1453 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1454 | EmitUint8(0x0F); |
| 1455 | EmitUint8(0xAF); |
| 1456 | EmitOperand(dst, Operand(src)); |
| 1457 | } |
| 1458 | |
| 1459 | |
Mark Mendell | 4a2aa4a | 2015-07-27 16:13:10 -0400 | [diff] [blame] | 1460 | void X86Assembler::imull(Register dst, Register src, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1461 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Mark Mendell | 4a2aa4a | 2015-07-27 16:13:10 -0400 | [diff] [blame] | 1462 | // See whether imm can be represented as a sign-extended 8bit value. |
| 1463 | int32_t v32 = static_cast<int32_t>(imm.value()); |
| 1464 | if (IsInt<8>(v32)) { |
| 1465 | // Sign-extension works. |
| 1466 | EmitUint8(0x6B); |
| 1467 | EmitOperand(dst, Operand(src)); |
| 1468 | EmitUint8(static_cast<uint8_t>(v32 & 0xFF)); |
| 1469 | } else { |
| 1470 | // Not representable, use full immediate. |
| 1471 | EmitUint8(0x69); |
| 1472 | EmitOperand(dst, Operand(src)); |
| 1473 | EmitImmediate(imm); |
| 1474 | } |
| 1475 | } |
| 1476 | |
| 1477 | |
| 1478 | void X86Assembler::imull(Register reg, const Immediate& imm) { |
| 1479 | imull(reg, reg, imm); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1480 | } |
| 1481 | |
| 1482 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1483 | void X86Assembler::imull(Register reg, const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1484 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1485 | EmitUint8(0x0F); |
| 1486 | EmitUint8(0xAF); |
| 1487 | EmitOperand(reg, address); |
| 1488 | } |
| 1489 | |
| 1490 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1491 | void X86Assembler::imull(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1492 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1493 | EmitUint8(0xF7); |
| 1494 | EmitOperand(5, Operand(reg)); |
| 1495 | } |
| 1496 | |
| 1497 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1498 | void X86Assembler::imull(const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1499 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1500 | EmitUint8(0xF7); |
| 1501 | EmitOperand(5, address); |
| 1502 | } |
| 1503 | |
| 1504 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1505 | void X86Assembler::mull(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1506 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1507 | EmitUint8(0xF7); |
| 1508 | EmitOperand(4, Operand(reg)); |
| 1509 | } |
| 1510 | |
| 1511 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1512 | void X86Assembler::mull(const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1513 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1514 | EmitUint8(0xF7); |
| 1515 | EmitOperand(4, address); |
| 1516 | } |
| 1517 | |
| 1518 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1519 | void X86Assembler::sbbl(Register dst, Register src) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1520 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1521 | EmitUint8(0x1B); |
| 1522 | EmitOperand(dst, Operand(src)); |
| 1523 | } |
| 1524 | |
| 1525 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1526 | void X86Assembler::sbbl(Register reg, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1527 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1528 | EmitComplex(3, Operand(reg), imm); |
| 1529 | } |
| 1530 | |
| 1531 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1532 | void X86Assembler::sbbl(Register dst, const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1533 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1534 | EmitUint8(0x1B); |
| 1535 | EmitOperand(dst, address); |
| 1536 | } |
| 1537 | |
| 1538 | |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 1539 | void X86Assembler::sbbl(const Address& address, Register src) { |
| 1540 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1541 | EmitUint8(0x19); |
| 1542 | EmitOperand(src, address); |
| 1543 | } |
| 1544 | |
| 1545 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1546 | void X86Assembler::incl(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1547 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1548 | EmitUint8(0x40 + reg); |
| 1549 | } |
| 1550 | |
| 1551 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1552 | void X86Assembler::incl(const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1553 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1554 | EmitUint8(0xFF); |
| 1555 | EmitOperand(0, address); |
| 1556 | } |
| 1557 | |
| 1558 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1559 | void X86Assembler::decl(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1560 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1561 | EmitUint8(0x48 + reg); |
| 1562 | } |
| 1563 | |
| 1564 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1565 | void X86Assembler::decl(const Address& address) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1566 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1567 | EmitUint8(0xFF); |
| 1568 | EmitOperand(1, address); |
| 1569 | } |
| 1570 | |
| 1571 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1572 | void X86Assembler::shll(Register reg, const Immediate& imm) { |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 1573 | EmitGenericShift(4, Operand(reg), imm); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1574 | } |
| 1575 | |
| 1576 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1577 | void X86Assembler::shll(Register operand, Register shifter) { |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 1578 | EmitGenericShift(4, Operand(operand), shifter); |
| 1579 | } |
| 1580 | |
| 1581 | |
| 1582 | void X86Assembler::shll(const Address& address, const Immediate& imm) { |
| 1583 | EmitGenericShift(4, address, imm); |
| 1584 | } |
| 1585 | |
| 1586 | |
| 1587 | void X86Assembler::shll(const Address& address, Register shifter) { |
| 1588 | EmitGenericShift(4, address, shifter); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1589 | } |
| 1590 | |
| 1591 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1592 | void X86Assembler::shrl(Register reg, const Immediate& imm) { |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 1593 | EmitGenericShift(5, Operand(reg), imm); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1594 | } |
| 1595 | |
| 1596 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1597 | void X86Assembler::shrl(Register operand, Register shifter) { |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 1598 | EmitGenericShift(5, Operand(operand), shifter); |
| 1599 | } |
| 1600 | |
| 1601 | |
| 1602 | void X86Assembler::shrl(const Address& address, const Immediate& imm) { |
| 1603 | EmitGenericShift(5, address, imm); |
| 1604 | } |
| 1605 | |
| 1606 | |
| 1607 | void X86Assembler::shrl(const Address& address, Register shifter) { |
| 1608 | EmitGenericShift(5, address, shifter); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1609 | } |
| 1610 | |
| 1611 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1612 | void X86Assembler::sarl(Register reg, const Immediate& imm) { |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 1613 | EmitGenericShift(7, Operand(reg), imm); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1614 | } |
| 1615 | |
| 1616 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1617 | void X86Assembler::sarl(Register operand, Register shifter) { |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 1618 | EmitGenericShift(7, Operand(operand), shifter); |
| 1619 | } |
| 1620 | |
| 1621 | |
| 1622 | void X86Assembler::sarl(const Address& address, const Immediate& imm) { |
| 1623 | EmitGenericShift(7, address, imm); |
| 1624 | } |
| 1625 | |
| 1626 | |
| 1627 | void X86Assembler::sarl(const Address& address, Register shifter) { |
| 1628 | EmitGenericShift(7, address, shifter); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1629 | } |
| 1630 | |
| 1631 | |
Calin Juravle | 9aec02f | 2014-11-18 23:06:35 +0000 | [diff] [blame] | 1632 | void X86Assembler::shld(Register dst, Register src, Register shifter) { |
| 1633 | DCHECK_EQ(ECX, shifter); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1634 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1635 | EmitUint8(0x0F); |
| 1636 | EmitUint8(0xA5); |
| 1637 | EmitRegisterOperand(src, dst); |
| 1638 | } |
| 1639 | |
| 1640 | |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 1641 | void X86Assembler::shld(Register dst, Register src, const Immediate& imm) { |
| 1642 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1643 | EmitUint8(0x0F); |
| 1644 | EmitUint8(0xA4); |
| 1645 | EmitRegisterOperand(src, dst); |
| 1646 | EmitUint8(imm.value() & 0xFF); |
| 1647 | } |
| 1648 | |
| 1649 | |
Calin Juravle | 9aec02f | 2014-11-18 23:06:35 +0000 | [diff] [blame] | 1650 | void X86Assembler::shrd(Register dst, Register src, Register shifter) { |
| 1651 | DCHECK_EQ(ECX, shifter); |
| 1652 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1653 | EmitUint8(0x0F); |
| 1654 | EmitUint8(0xAD); |
| 1655 | EmitRegisterOperand(src, dst); |
| 1656 | } |
| 1657 | |
| 1658 | |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 1659 | void X86Assembler::shrd(Register dst, Register src, const Immediate& imm) { |
| 1660 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1661 | EmitUint8(0x0F); |
| 1662 | EmitUint8(0xAC); |
| 1663 | EmitRegisterOperand(src, dst); |
| 1664 | EmitUint8(imm.value() & 0xFF); |
| 1665 | } |
| 1666 | |
| 1667 | |
Mark Mendell | bcee092 | 2015-09-15 21:45:01 -0400 | [diff] [blame] | 1668 | void X86Assembler::roll(Register reg, const Immediate& imm) { |
| 1669 | EmitGenericShift(0, Operand(reg), imm); |
| 1670 | } |
| 1671 | |
| 1672 | |
| 1673 | void X86Assembler::roll(Register operand, Register shifter) { |
| 1674 | EmitGenericShift(0, Operand(operand), shifter); |
| 1675 | } |
| 1676 | |
| 1677 | |
| 1678 | void X86Assembler::rorl(Register reg, const Immediate& imm) { |
| 1679 | EmitGenericShift(1, Operand(reg), imm); |
| 1680 | } |
| 1681 | |
| 1682 | |
| 1683 | void X86Assembler::rorl(Register operand, Register shifter) { |
| 1684 | EmitGenericShift(1, Operand(operand), shifter); |
| 1685 | } |
| 1686 | |
| 1687 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1688 | void X86Assembler::negl(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1689 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1690 | EmitUint8(0xF7); |
| 1691 | EmitOperand(3, Operand(reg)); |
| 1692 | } |
| 1693 | |
| 1694 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1695 | void X86Assembler::notl(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1696 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1697 | EmitUint8(0xF7); |
| 1698 | EmitUint8(0xD0 | reg); |
| 1699 | } |
| 1700 | |
| 1701 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1702 | void X86Assembler::enter(const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1703 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1704 | EmitUint8(0xC8); |
| 1705 | CHECK(imm.is_uint16()); |
| 1706 | EmitUint8(imm.value() & 0xFF); |
| 1707 | EmitUint8((imm.value() >> 8) & 0xFF); |
| 1708 | EmitUint8(0x00); |
| 1709 | } |
| 1710 | |
| 1711 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1712 | void X86Assembler::leave() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1713 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1714 | EmitUint8(0xC9); |
| 1715 | } |
| 1716 | |
| 1717 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1718 | void X86Assembler::ret() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1719 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1720 | EmitUint8(0xC3); |
| 1721 | } |
| 1722 | |
| 1723 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1724 | void X86Assembler::ret(const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1725 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1726 | EmitUint8(0xC2); |
| 1727 | CHECK(imm.is_uint16()); |
| 1728 | EmitUint8(imm.value() & 0xFF); |
| 1729 | EmitUint8((imm.value() >> 8) & 0xFF); |
| 1730 | } |
| 1731 | |
| 1732 | |
| 1733 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1734 | void X86Assembler::nop() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1735 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1736 | EmitUint8(0x90); |
| 1737 | } |
| 1738 | |
| 1739 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1740 | void X86Assembler::int3() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1741 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1742 | EmitUint8(0xCC); |
| 1743 | } |
| 1744 | |
| 1745 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1746 | void X86Assembler::hlt() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1747 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1748 | EmitUint8(0xF4); |
| 1749 | } |
| 1750 | |
| 1751 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1752 | void X86Assembler::j(Condition condition, Label* label) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1753 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1754 | if (label->IsBound()) { |
| 1755 | static const int kShortSize = 2; |
| 1756 | static const int kLongSize = 6; |
| 1757 | int offset = label->Position() - buffer_.Size(); |
| 1758 | CHECK_LE(offset, 0); |
Andreas Gampe | ab1eb0d | 2015-02-13 19:23:55 -0800 | [diff] [blame] | 1759 | if (IsInt<8>(offset - kShortSize)) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1760 | EmitUint8(0x70 + condition); |
| 1761 | EmitUint8((offset - kShortSize) & 0xFF); |
| 1762 | } else { |
| 1763 | EmitUint8(0x0F); |
| 1764 | EmitUint8(0x80 + condition); |
| 1765 | EmitInt32(offset - kLongSize); |
| 1766 | } |
| 1767 | } else { |
| 1768 | EmitUint8(0x0F); |
| 1769 | EmitUint8(0x80 + condition); |
| 1770 | EmitLabelLink(label); |
| 1771 | } |
| 1772 | } |
| 1773 | |
| 1774 | |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 1775 | void X86Assembler::j(Condition condition, NearLabel* label) { |
| 1776 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1777 | if (label->IsBound()) { |
| 1778 | static const int kShortSize = 2; |
| 1779 | int offset = label->Position() - buffer_.Size(); |
| 1780 | CHECK_LE(offset, 0); |
| 1781 | CHECK(IsInt<8>(offset - kShortSize)); |
| 1782 | EmitUint8(0x70 + condition); |
| 1783 | EmitUint8((offset - kShortSize) & 0xFF); |
| 1784 | } else { |
| 1785 | EmitUint8(0x70 + condition); |
| 1786 | EmitLabelLink(label); |
| 1787 | } |
| 1788 | } |
| 1789 | |
| 1790 | |
| 1791 | void X86Assembler::jecxz(NearLabel* label) { |
| 1792 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1793 | if (label->IsBound()) { |
| 1794 | static const int kShortSize = 2; |
| 1795 | int offset = label->Position() - buffer_.Size(); |
| 1796 | CHECK_LE(offset, 0); |
| 1797 | CHECK(IsInt<8>(offset - kShortSize)); |
| 1798 | EmitUint8(0xE3); |
| 1799 | EmitUint8((offset - kShortSize) & 0xFF); |
| 1800 | } else { |
| 1801 | EmitUint8(0xE3); |
| 1802 | EmitLabelLink(label); |
| 1803 | } |
| 1804 | } |
| 1805 | |
| 1806 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1807 | void X86Assembler::jmp(Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1808 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1809 | EmitUint8(0xFF); |
| 1810 | EmitRegisterOperand(4, reg); |
| 1811 | } |
| 1812 | |
Ian Rogers | 7caad77 | 2012-03-30 01:07:54 -0700 | [diff] [blame] | 1813 | void X86Assembler::jmp(const Address& address) { |
| 1814 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1815 | EmitUint8(0xFF); |
| 1816 | EmitOperand(4, address); |
| 1817 | } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1818 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1819 | void X86Assembler::jmp(Label* label) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1820 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1821 | if (label->IsBound()) { |
| 1822 | static const int kShortSize = 2; |
| 1823 | static const int kLongSize = 5; |
| 1824 | int offset = label->Position() - buffer_.Size(); |
| 1825 | CHECK_LE(offset, 0); |
Andreas Gampe | ab1eb0d | 2015-02-13 19:23:55 -0800 | [diff] [blame] | 1826 | if (IsInt<8>(offset - kShortSize)) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1827 | EmitUint8(0xEB); |
| 1828 | EmitUint8((offset - kShortSize) & 0xFF); |
| 1829 | } else { |
| 1830 | EmitUint8(0xE9); |
| 1831 | EmitInt32(offset - kLongSize); |
| 1832 | } |
| 1833 | } else { |
| 1834 | EmitUint8(0xE9); |
| 1835 | EmitLabelLink(label); |
| 1836 | } |
| 1837 | } |
| 1838 | |
| 1839 | |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 1840 | void X86Assembler::jmp(NearLabel* label) { |
| 1841 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1842 | if (label->IsBound()) { |
| 1843 | static const int kShortSize = 2; |
| 1844 | int offset = label->Position() - buffer_.Size(); |
| 1845 | CHECK_LE(offset, 0); |
| 1846 | CHECK(IsInt<8>(offset - kShortSize)); |
| 1847 | EmitUint8(0xEB); |
| 1848 | EmitUint8((offset - kShortSize) & 0xFF); |
| 1849 | } else { |
| 1850 | EmitUint8(0xEB); |
| 1851 | EmitLabelLink(label); |
| 1852 | } |
| 1853 | } |
| 1854 | |
| 1855 | |
jessicahandojo | b03d640 | 2016-09-07 12:16:53 -0700 | [diff] [blame] | 1856 | void X86Assembler::repne_scasb() { |
| 1857 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1858 | EmitUint8(0xF2); |
| 1859 | EmitUint8(0xAE); |
| 1860 | } |
| 1861 | |
| 1862 | |
Andreas Gampe | 21030dd | 2015-05-07 14:46:15 -0700 | [diff] [blame] | 1863 | void X86Assembler::repne_scasw() { |
| 1864 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1865 | EmitUint8(0x66); |
| 1866 | EmitUint8(0xF2); |
| 1867 | EmitUint8(0xAF); |
| 1868 | } |
| 1869 | |
| 1870 | |
jessicahandojo | b03d640 | 2016-09-07 12:16:53 -0700 | [diff] [blame] | 1871 | void X86Assembler::repe_cmpsb() { |
| 1872 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1873 | EmitUint8(0xF2); |
| 1874 | EmitUint8(0xA6); |
| 1875 | } |
| 1876 | |
| 1877 | |
agicsaki | 71311f8 | 2015-07-27 11:34:13 -0700 | [diff] [blame] | 1878 | void X86Assembler::repe_cmpsw() { |
| 1879 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1880 | EmitUint8(0x66); |
| 1881 | EmitUint8(0xF3); |
| 1882 | EmitUint8(0xA7); |
| 1883 | } |
| 1884 | |
| 1885 | |
agicsaki | 970abfb | 2015-07-31 10:31:14 -0700 | [diff] [blame] | 1886 | void X86Assembler::repe_cmpsl() { |
| 1887 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1888 | EmitUint8(0xF3); |
| 1889 | EmitUint8(0xA7); |
| 1890 | } |
| 1891 | |
| 1892 | |
jessicahandojo | b03d640 | 2016-09-07 12:16:53 -0700 | [diff] [blame] | 1893 | void X86Assembler::rep_movsb() { |
| 1894 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1895 | EmitUint8(0xF3); |
| 1896 | EmitUint8(0xA4); |
| 1897 | } |
| 1898 | |
| 1899 | |
Mark Mendell | b9c4bbe | 2015-07-01 14:26:52 -0400 | [diff] [blame] | 1900 | void X86Assembler::rep_movsw() { |
| 1901 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1902 | EmitUint8(0x66); |
| 1903 | EmitUint8(0xF3); |
| 1904 | EmitUint8(0xA5); |
| 1905 | } |
| 1906 | |
| 1907 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1908 | X86Assembler* X86Assembler::lock() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1909 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1910 | EmitUint8(0xF0); |
Ian Rogers | 0d666d8 | 2011-08-14 16:03:46 -0700 | [diff] [blame] | 1911 | return this; |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1912 | } |
| 1913 | |
| 1914 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1915 | void X86Assembler::cmpxchgl(const Address& address, Register reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1916 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1917 | EmitUint8(0x0F); |
| 1918 | EmitUint8(0xB1); |
| 1919 | EmitOperand(reg, address); |
| 1920 | } |
| 1921 | |
Mark Mendell | 58d25fd | 2015-04-03 14:52:31 -0400 | [diff] [blame] | 1922 | |
| 1923 | void X86Assembler::cmpxchg8b(const Address& address) { |
| 1924 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1925 | EmitUint8(0x0F); |
| 1926 | EmitUint8(0xC7); |
| 1927 | EmitOperand(1, address); |
| 1928 | } |
| 1929 | |
| 1930 | |
Elliott Hughes | 79ab9e3 | 2012-03-12 15:41:35 -0700 | [diff] [blame] | 1931 | void X86Assembler::mfence() { |
| 1932 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1933 | EmitUint8(0x0F); |
| 1934 | EmitUint8(0xAE); |
| 1935 | EmitUint8(0xF0); |
| 1936 | } |
| 1937 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1938 | X86Assembler* X86Assembler::fs() { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1939 | // TODO: fs is a prefix and not an instruction |
| 1940 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1941 | EmitUint8(0x64); |
Ian Rogers | 0d666d8 | 2011-08-14 16:03:46 -0700 | [diff] [blame] | 1942 | return this; |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1943 | } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1944 | |
Ian Rogers | befbd57 | 2014-03-06 01:13:39 -0800 | [diff] [blame] | 1945 | X86Assembler* X86Assembler::gs() { |
| 1946 | // TODO: fs is a prefix and not an instruction |
| 1947 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1948 | EmitUint8(0x65); |
| 1949 | return this; |
| 1950 | } |
| 1951 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1952 | void X86Assembler::AddImmediate(Register reg, const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1953 | int value = imm.value(); |
| 1954 | if (value > 0) { |
| 1955 | if (value == 1) { |
| 1956 | incl(reg); |
| 1957 | } else if (value != 0) { |
| 1958 | addl(reg, imm); |
| 1959 | } |
| 1960 | } else if (value < 0) { |
| 1961 | value = -value; |
| 1962 | if (value == 1) { |
| 1963 | decl(reg); |
| 1964 | } else if (value != 0) { |
| 1965 | subl(reg, Immediate(value)); |
| 1966 | } |
| 1967 | } |
| 1968 | } |
| 1969 | |
| 1970 | |
Roland Levillain | 647b9ed | 2014-11-27 12:06:00 +0000 | [diff] [blame] | 1971 | void X86Assembler::LoadLongConstant(XmmRegister dst, int64_t value) { |
| 1972 | // TODO: Need to have a code constants table. |
| 1973 | pushl(Immediate(High32Bits(value))); |
| 1974 | pushl(Immediate(Low32Bits(value))); |
| 1975 | movsd(dst, Address(ESP, 0)); |
| 1976 | addl(ESP, Immediate(2 * sizeof(int32_t))); |
| 1977 | } |
| 1978 | |
| 1979 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1980 | void X86Assembler::LoadDoubleConstant(XmmRegister dst, double value) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1981 | // TODO: Need to have a code constants table. |
| 1982 | int64_t constant = bit_cast<int64_t, double>(value); |
Roland Levillain | 647b9ed | 2014-11-27 12:06:00 +0000 | [diff] [blame] | 1983 | LoadLongConstant(dst, constant); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1984 | } |
| 1985 | |
| 1986 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1987 | void X86Assembler::Align(int alignment, int offset) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1988 | CHECK(IsPowerOfTwo(alignment)); |
| 1989 | // Emit nop instruction until the real position is aligned. |
| 1990 | while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) { |
| 1991 | nop(); |
| 1992 | } |
| 1993 | } |
| 1994 | |
| 1995 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1996 | void X86Assembler::Bind(Label* label) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1997 | int bound = buffer_.Size(); |
| 1998 | CHECK(!label->IsBound()); // Labels can only be bound once. |
| 1999 | while (label->IsLinked()) { |
| 2000 | int position = label->LinkPosition(); |
| 2001 | int next = buffer_.Load<int32_t>(position); |
| 2002 | buffer_.Store<int32_t>(position, bound - (position + 4)); |
| 2003 | label->position_ = next; |
| 2004 | } |
| 2005 | label->BindTo(bound); |
| 2006 | } |
| 2007 | |
| 2008 | |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 2009 | void X86Assembler::Bind(NearLabel* label) { |
| 2010 | int bound = buffer_.Size(); |
| 2011 | CHECK(!label->IsBound()); // Labels can only be bound once. |
| 2012 | while (label->IsLinked()) { |
| 2013 | int position = label->LinkPosition(); |
| 2014 | uint8_t delta = buffer_.Load<uint8_t>(position); |
| 2015 | int offset = bound - (position + 1); |
| 2016 | CHECK(IsInt<8>(offset)); |
| 2017 | buffer_.Store<int8_t>(position, offset); |
| 2018 | label->position_ = delta != 0u ? label->position_ - delta : 0; |
| 2019 | } |
| 2020 | label->BindTo(bound); |
| 2021 | } |
| 2022 | |
| 2023 | |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2024 | void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) { |
| 2025 | CHECK_GE(reg_or_opcode, 0); |
| 2026 | CHECK_LT(reg_or_opcode, 8); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2027 | const int length = operand.length_; |
| 2028 | CHECK_GT(length, 0); |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2029 | // Emit the ModRM byte updated with the given reg value. |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2030 | CHECK_EQ(operand.encoding_[0] & 0x38, 0); |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2031 | EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3)); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2032 | // Emit the rest of the encoded operand. |
| 2033 | for (int i = 1; i < length; i++) { |
| 2034 | EmitUint8(operand.encoding_[i]); |
| 2035 | } |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 2036 | AssemblerFixup* fixup = operand.GetFixup(); |
| 2037 | if (fixup != nullptr) { |
| 2038 | EmitFixup(fixup); |
| 2039 | } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2040 | } |
| 2041 | |
| 2042 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2043 | void X86Assembler::EmitImmediate(const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2044 | EmitInt32(imm.value()); |
| 2045 | } |
| 2046 | |
| 2047 | |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2048 | void X86Assembler::EmitComplex(int reg_or_opcode, |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2049 | const Operand& operand, |
| 2050 | const Immediate& immediate) { |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2051 | CHECK_GE(reg_or_opcode, 0); |
| 2052 | CHECK_LT(reg_or_opcode, 8); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2053 | if (immediate.is_int8()) { |
| 2054 | // Use sign-extended 8-bit immediate. |
| 2055 | EmitUint8(0x83); |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2056 | EmitOperand(reg_or_opcode, operand); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2057 | EmitUint8(immediate.value() & 0xFF); |
| 2058 | } else if (operand.IsRegister(EAX)) { |
| 2059 | // Use short form if the destination is eax. |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2060 | EmitUint8(0x05 + (reg_or_opcode << 3)); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2061 | EmitImmediate(immediate); |
| 2062 | } else { |
| 2063 | EmitUint8(0x81); |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2064 | EmitOperand(reg_or_opcode, operand); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2065 | EmitImmediate(immediate); |
| 2066 | } |
| 2067 | } |
| 2068 | |
| 2069 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2070 | void X86Assembler::EmitLabel(Label* label, int instruction_size) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2071 | if (label->IsBound()) { |
| 2072 | int offset = label->Position() - buffer_.Size(); |
| 2073 | CHECK_LE(offset, 0); |
| 2074 | EmitInt32(offset - instruction_size); |
| 2075 | } else { |
| 2076 | EmitLabelLink(label); |
| 2077 | } |
| 2078 | } |
| 2079 | |
| 2080 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2081 | void X86Assembler::EmitLabelLink(Label* label) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2082 | CHECK(!label->IsBound()); |
| 2083 | int position = buffer_.Size(); |
| 2084 | EmitInt32(label->position_); |
| 2085 | label->LinkTo(position); |
| 2086 | } |
| 2087 | |
| 2088 | |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 2089 | void X86Assembler::EmitLabelLink(NearLabel* label) { |
| 2090 | CHECK(!label->IsBound()); |
| 2091 | int position = buffer_.Size(); |
| 2092 | if (label->IsLinked()) { |
| 2093 | // Save the delta in the byte that we have to play with. |
| 2094 | uint32_t delta = position - label->LinkPosition(); |
| 2095 | CHECK(IsUint<8>(delta)); |
| 2096 | EmitUint8(delta & 0xFF); |
| 2097 | } else { |
| 2098 | EmitUint8(0); |
| 2099 | } |
| 2100 | label->LinkTo(position); |
| 2101 | } |
| 2102 | |
| 2103 | |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2104 | void X86Assembler::EmitGenericShift(int reg_or_opcode, |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 2105 | const Operand& operand, |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2106 | const Immediate& imm) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2107 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2108 | CHECK(imm.is_int8()); |
| 2109 | if (imm.value() == 1) { |
| 2110 | EmitUint8(0xD1); |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 2111 | EmitOperand(reg_or_opcode, operand); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2112 | } else { |
| 2113 | EmitUint8(0xC1); |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 2114 | EmitOperand(reg_or_opcode, operand); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2115 | EmitUint8(imm.value() & 0xFF); |
| 2116 | } |
| 2117 | } |
| 2118 | |
| 2119 | |
Ian Rogers | 44fb0d0 | 2012-03-23 16:46:24 -0700 | [diff] [blame] | 2120 | void X86Assembler::EmitGenericShift(int reg_or_opcode, |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 2121 | const Operand& operand, |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2122 | Register shifter) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2123 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2124 | CHECK_EQ(shifter, ECX); |
| 2125 | EmitUint8(0xD3); |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 2126 | EmitOperand(reg_or_opcode, operand); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 2127 | } |
| 2128 | |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 2129 | void X86Assembler::AddConstantArea() { |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame] | 2130 | ArrayRef<const int32_t> area = constant_area_.GetBuffer(); |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 2131 | // Generate the data for the literal area. |
| 2132 | for (size_t i = 0, e = area.size(); i < e; i++) { |
| 2133 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2134 | EmitInt32(area[i]); |
| 2135 | } |
| 2136 | } |
| 2137 | |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 2138 | size_t ConstantArea::AppendInt32(int32_t v) { |
| 2139 | size_t result = buffer_.size() * elem_size_; |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 2140 | buffer_.push_back(v); |
| 2141 | return result; |
| 2142 | } |
| 2143 | |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 2144 | size_t ConstantArea::AddInt32(int32_t v) { |
| 2145 | for (size_t i = 0, e = buffer_.size(); i < e; i++) { |
| 2146 | if (v == buffer_[i]) { |
| 2147 | return i * elem_size_; |
| 2148 | } |
| 2149 | } |
| 2150 | |
| 2151 | // Didn't match anything. |
| 2152 | return AppendInt32(v); |
| 2153 | } |
| 2154 | |
| 2155 | size_t ConstantArea::AddInt64(int64_t v) { |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 2156 | int32_t v_low = Low32Bits(v); |
| 2157 | int32_t v_high = High32Bits(v); |
| 2158 | if (buffer_.size() > 1) { |
| 2159 | // Ensure we don't pass the end of the buffer. |
| 2160 | for (size_t i = 0, e = buffer_.size() - 1; i < e; i++) { |
| 2161 | if (v_low == buffer_[i] && v_high == buffer_[i + 1]) { |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 2162 | return i * elem_size_; |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 2163 | } |
| 2164 | } |
| 2165 | } |
| 2166 | |
| 2167 | // Didn't match anything. |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 2168 | size_t result = buffer_.size() * elem_size_; |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 2169 | buffer_.push_back(v_low); |
| 2170 | buffer_.push_back(v_high); |
| 2171 | return result; |
| 2172 | } |
| 2173 | |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 2174 | size_t ConstantArea::AddDouble(double v) { |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 2175 | // Treat the value as a 64-bit integer value. |
| 2176 | return AddInt64(bit_cast<int64_t, double>(v)); |
| 2177 | } |
| 2178 | |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 2179 | size_t ConstantArea::AddFloat(float v) { |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 2180 | // Treat the value as a 32-bit integer value. |
| 2181 | return AddInt32(bit_cast<int32_t, float>(v)); |
| 2182 | } |
| 2183 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 2184 | } // namespace x86 |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 2185 | } // namespace art |