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Elliott Hughes2faa5f12012-01-30 14:42:07 -08001/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070016
Ian Rogers2c8f6532011-09-02 17:16:34 -070017#include "assembler_x86.h"
18
Elliott Hughes1aa246d2012-12-13 09:29:36 -080019#include "base/casts.h"
Ian Rogers166db042013-07-26 12:05:57 -070020#include "entrypoints/quick/quick_entrypoints.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070021#include "memory_region.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070022#include "thread.h"
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070023
Carl Shapiro6b6b5f02011-06-21 15:05:09 -070024namespace art {
Ian Rogers2c8f6532011-09-02 17:16:34 -070025namespace x86 {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070026
Ian Rogersb033c752011-07-20 12:22:35 -070027std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) {
28 return os << "XMM" << static_cast<int>(reg);
29}
30
31std::ostream& operator<<(std::ostream& os, const X87Register& reg) {
32 return os << "ST" << static_cast<int>(reg);
33}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070034
Ian Rogers2c8f6532011-09-02 17:16:34 -070035void X86Assembler::call(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070036 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
37 EmitUint8(0xFF);
38 EmitRegisterOperand(2, reg);
39}
40
41
Ian Rogers2c8f6532011-09-02 17:16:34 -070042void X86Assembler::call(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070043 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
44 EmitUint8(0xFF);
45 EmitOperand(2, address);
46}
47
48
Ian Rogers2c8f6532011-09-02 17:16:34 -070049void X86Assembler::call(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070050 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
51 EmitUint8(0xE8);
52 static const int kSize = 5;
Nicolas Geoffray1cf95282014-12-12 19:22:03 +000053 // Offset by one because we already have emitted the opcode.
54 EmitLabel(label, kSize - 1);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070055}
56
57
Nicolas Geoffray8ccc3f52014-03-19 10:34:11 +000058void X86Assembler::call(const ExternalLabel& label) {
59 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
60 intptr_t call_start = buffer_.GetPosition();
61 EmitUint8(0xE8);
62 EmitInt32(label.address());
63 static const intptr_t kCallExternalLabelSize = 5;
64 DCHECK_EQ((buffer_.GetPosition() - call_start), kCallExternalLabelSize);
65}
66
67
Ian Rogers2c8f6532011-09-02 17:16:34 -070068void X86Assembler::pushl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070069 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
70 EmitUint8(0x50 + reg);
71}
72
73
Ian Rogers2c8f6532011-09-02 17:16:34 -070074void X86Assembler::pushl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070075 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
76 EmitUint8(0xFF);
77 EmitOperand(6, address);
78}
79
80
Ian Rogers2c8f6532011-09-02 17:16:34 -070081void X86Assembler::pushl(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070082 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Ian Rogers44fb0d02012-03-23 16:46:24 -070083 if (imm.is_int8()) {
84 EmitUint8(0x6A);
85 EmitUint8(imm.value() & 0xFF);
86 } else {
87 EmitUint8(0x68);
88 EmitImmediate(imm);
89 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070090}
91
92
Ian Rogers2c8f6532011-09-02 17:16:34 -070093void X86Assembler::popl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070094 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
95 EmitUint8(0x58 + reg);
96}
97
98
Ian Rogers2c8f6532011-09-02 17:16:34 -070099void X86Assembler::popl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700100 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
101 EmitUint8(0x8F);
102 EmitOperand(0, address);
103}
104
105
Ian Rogers2c8f6532011-09-02 17:16:34 -0700106void X86Assembler::movl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700107 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
108 EmitUint8(0xB8 + dst);
109 EmitImmediate(imm);
110}
111
112
Ian Rogers2c8f6532011-09-02 17:16:34 -0700113void X86Assembler::movl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700114 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
115 EmitUint8(0x89);
116 EmitRegisterOperand(src, dst);
117}
118
119
Ian Rogers2c8f6532011-09-02 17:16:34 -0700120void X86Assembler::movl(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700121 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
122 EmitUint8(0x8B);
123 EmitOperand(dst, src);
124}
125
126
Ian Rogers2c8f6532011-09-02 17:16:34 -0700127void X86Assembler::movl(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700128 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
129 EmitUint8(0x89);
130 EmitOperand(src, dst);
131}
132
133
Ian Rogers2c8f6532011-09-02 17:16:34 -0700134void X86Assembler::movl(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700135 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
136 EmitUint8(0xC7);
137 EmitOperand(0, dst);
138 EmitImmediate(imm);
139}
140
Ian Rogersbdb03912011-09-14 00:55:44 -0700141void X86Assembler::movl(const Address& dst, Label* lbl) {
142 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
143 EmitUint8(0xC7);
144 EmitOperand(0, dst);
145 EmitLabel(lbl, dst.length_ + 5);
146}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700147
Mark Mendell7a08fb52015-07-15 14:09:35 -0400148void X86Assembler::movntl(const Address& dst, Register src) {
149 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
150 EmitUint8(0x0F);
151 EmitUint8(0xC3);
152 EmitOperand(src, dst);
153}
154
Mark Mendell09ed1a32015-03-25 08:30:06 -0400155void X86Assembler::bswapl(Register dst) {
156 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
157 EmitUint8(0x0F);
158 EmitUint8(0xC8 + dst);
159}
160
Mark Mendellbcee0922015-09-15 21:45:01 -0400161void X86Assembler::bsfl(Register dst, Register src) {
162 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
163 EmitUint8(0x0F);
164 EmitUint8(0xBC);
165 EmitRegisterOperand(dst, src);
166}
167
168void X86Assembler::bsfl(Register dst, const Address& src) {
169 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
170 EmitUint8(0x0F);
171 EmitUint8(0xBC);
172 EmitOperand(dst, src);
173}
174
Mark Mendell8ae3ffb2015-08-12 21:16:41 -0400175void X86Assembler::bsrl(Register dst, Register src) {
176 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
177 EmitUint8(0x0F);
178 EmitUint8(0xBD);
179 EmitRegisterOperand(dst, src);
180}
181
182void X86Assembler::bsrl(Register dst, const Address& src) {
183 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
184 EmitUint8(0x0F);
185 EmitUint8(0xBD);
186 EmitOperand(dst, src);
187}
188
Aart Bikc39dac12016-01-21 08:59:48 -0800189void X86Assembler::popcntl(Register dst, Register src) {
190 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
191 EmitUint8(0xF3);
192 EmitUint8(0x0F);
193 EmitUint8(0xB8);
194 EmitRegisterOperand(dst, src);
195}
196
197void X86Assembler::popcntl(Register dst, const Address& src) {
198 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
199 EmitUint8(0xF3);
200 EmitUint8(0x0F);
201 EmitUint8(0xB8);
202 EmitOperand(dst, src);
203}
204
Ian Rogers2c8f6532011-09-02 17:16:34 -0700205void X86Assembler::movzxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700206 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
207 EmitUint8(0x0F);
208 EmitUint8(0xB6);
209 EmitRegisterOperand(dst, src);
210}
211
212
Ian Rogers2c8f6532011-09-02 17:16:34 -0700213void X86Assembler::movzxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700214 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
215 EmitUint8(0x0F);
216 EmitUint8(0xB6);
217 EmitOperand(dst, src);
218}
219
220
Ian Rogers2c8f6532011-09-02 17:16:34 -0700221void X86Assembler::movsxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700222 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
223 EmitUint8(0x0F);
224 EmitUint8(0xBE);
225 EmitRegisterOperand(dst, src);
226}
227
228
Ian Rogers2c8f6532011-09-02 17:16:34 -0700229void X86Assembler::movsxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700230 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
231 EmitUint8(0x0F);
232 EmitUint8(0xBE);
233 EmitOperand(dst, src);
234}
235
236
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700237void X86Assembler::movb(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700238 LOG(FATAL) << "Use movzxb or movsxb instead.";
239}
240
241
Ian Rogers2c8f6532011-09-02 17:16:34 -0700242void X86Assembler::movb(const Address& dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700243 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
244 EmitUint8(0x88);
245 EmitOperand(src, dst);
246}
247
248
Ian Rogers2c8f6532011-09-02 17:16:34 -0700249void X86Assembler::movb(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700250 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
251 EmitUint8(0xC6);
252 EmitOperand(EAX, dst);
253 CHECK(imm.is_int8());
254 EmitUint8(imm.value() & 0xFF);
255}
256
257
Ian Rogers2c8f6532011-09-02 17:16:34 -0700258void X86Assembler::movzxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700259 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
260 EmitUint8(0x0F);
261 EmitUint8(0xB7);
262 EmitRegisterOperand(dst, src);
263}
264
265
Ian Rogers2c8f6532011-09-02 17:16:34 -0700266void X86Assembler::movzxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700267 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
268 EmitUint8(0x0F);
269 EmitUint8(0xB7);
270 EmitOperand(dst, src);
271}
272
273
Ian Rogers2c8f6532011-09-02 17:16:34 -0700274void X86Assembler::movsxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700275 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
276 EmitUint8(0x0F);
277 EmitUint8(0xBF);
278 EmitRegisterOperand(dst, src);
279}
280
281
Ian Rogers2c8f6532011-09-02 17:16:34 -0700282void X86Assembler::movsxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700283 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
284 EmitUint8(0x0F);
285 EmitUint8(0xBF);
286 EmitOperand(dst, src);
287}
288
289
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700290void X86Assembler::movw(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700291 LOG(FATAL) << "Use movzxw or movsxw instead.";
292}
293
294
Ian Rogers2c8f6532011-09-02 17:16:34 -0700295void X86Assembler::movw(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700296 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
297 EmitOperandSizeOverride();
298 EmitUint8(0x89);
299 EmitOperand(src, dst);
300}
301
302
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100303void X86Assembler::movw(const Address& dst, const Immediate& imm) {
304 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
305 EmitOperandSizeOverride();
306 EmitUint8(0xC7);
307 EmitOperand(0, dst);
Nicolas Geoffrayb6e72062014-10-07 14:54:48 +0100308 CHECK(imm.is_uint16() || imm.is_int16());
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100309 EmitUint8(imm.value() & 0xFF);
310 EmitUint8(imm.value() >> 8);
311}
312
313
Ian Rogers2c8f6532011-09-02 17:16:34 -0700314void X86Assembler::leal(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700315 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
316 EmitUint8(0x8D);
317 EmitOperand(dst, src);
318}
319
320
Ian Rogers2c8f6532011-09-02 17:16:34 -0700321void X86Assembler::cmovl(Condition condition, Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700322 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
323 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700324 EmitUint8(0x40 + condition);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700325 EmitRegisterOperand(dst, src);
326}
327
328
Mark Mendellabdac472016-02-12 13:49:03 -0500329void X86Assembler::cmovl(Condition condition, Register dst, const Address& src) {
330 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
331 EmitUint8(0x0F);
332 EmitUint8(0x40 + condition);
333 EmitOperand(dst, src);
334}
335
336
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000337void X86Assembler::setb(Condition condition, Register dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700338 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
339 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700340 EmitUint8(0x90 + condition);
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000341 EmitOperand(0, Operand(dst));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700342}
343
344
Nicolas Geoffray7fb49da2014-10-06 09:12:41 +0100345void X86Assembler::movaps(XmmRegister dst, XmmRegister src) {
346 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
347 EmitUint8(0x0F);
348 EmitUint8(0x28);
349 EmitXmmRegisterOperand(dst, src);
350}
351
352
Aart Bikc7782262017-01-13 16:20:08 -0800353void X86Assembler::movaps(XmmRegister dst, const Address& src) {
354 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
355 EmitUint8(0x0F);
356 EmitUint8(0x28);
357 EmitOperand(dst, src);
358}
359
360
361void X86Assembler::movups(XmmRegister dst, const Address& src) {
362 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
363 EmitUint8(0x0F);
364 EmitUint8(0x10);
365 EmitOperand(dst, src);
366}
367
368
369void X86Assembler::movaps(const Address& dst, XmmRegister src) {
370 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
371 EmitUint8(0x0F);
372 EmitUint8(0x29);
373 EmitOperand(src, dst);
374}
375
376
377void X86Assembler::movups(const Address& dst, XmmRegister src) {
378 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
379 EmitUint8(0x0F);
380 EmitUint8(0x11);
381 EmitOperand(src, dst);
382}
383
384
Ian Rogers2c8f6532011-09-02 17:16:34 -0700385void X86Assembler::movss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700386 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
387 EmitUint8(0xF3);
388 EmitUint8(0x0F);
389 EmitUint8(0x10);
390 EmitOperand(dst, src);
391}
392
393
Ian Rogers2c8f6532011-09-02 17:16:34 -0700394void X86Assembler::movss(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700395 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
396 EmitUint8(0xF3);
397 EmitUint8(0x0F);
398 EmitUint8(0x11);
399 EmitOperand(src, dst);
400}
401
402
Ian Rogers2c8f6532011-09-02 17:16:34 -0700403void X86Assembler::movss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700404 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
405 EmitUint8(0xF3);
406 EmitUint8(0x0F);
407 EmitUint8(0x11);
408 EmitXmmRegisterOperand(src, dst);
409}
410
411
Ian Rogers2c8f6532011-09-02 17:16:34 -0700412void X86Assembler::movd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700413 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
414 EmitUint8(0x66);
415 EmitUint8(0x0F);
416 EmitUint8(0x6E);
417 EmitOperand(dst, Operand(src));
418}
419
420
Ian Rogers2c8f6532011-09-02 17:16:34 -0700421void X86Assembler::movd(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700422 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
423 EmitUint8(0x66);
424 EmitUint8(0x0F);
425 EmitUint8(0x7E);
426 EmitOperand(src, Operand(dst));
427}
428
429
Ian Rogers2c8f6532011-09-02 17:16:34 -0700430void X86Assembler::addss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700431 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
432 EmitUint8(0xF3);
433 EmitUint8(0x0F);
434 EmitUint8(0x58);
435 EmitXmmRegisterOperand(dst, src);
436}
437
438
Ian Rogers2c8f6532011-09-02 17:16:34 -0700439void X86Assembler::addss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700440 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
441 EmitUint8(0xF3);
442 EmitUint8(0x0F);
443 EmitUint8(0x58);
444 EmitOperand(dst, src);
445}
446
447
Ian Rogers2c8f6532011-09-02 17:16:34 -0700448void X86Assembler::subss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700449 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
450 EmitUint8(0xF3);
451 EmitUint8(0x0F);
452 EmitUint8(0x5C);
453 EmitXmmRegisterOperand(dst, src);
454}
455
456
Ian Rogers2c8f6532011-09-02 17:16:34 -0700457void X86Assembler::subss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700458 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
459 EmitUint8(0xF3);
460 EmitUint8(0x0F);
461 EmitUint8(0x5C);
462 EmitOperand(dst, src);
463}
464
465
Ian Rogers2c8f6532011-09-02 17:16:34 -0700466void X86Assembler::mulss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700467 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
468 EmitUint8(0xF3);
469 EmitUint8(0x0F);
470 EmitUint8(0x59);
471 EmitXmmRegisterOperand(dst, src);
472}
473
474
Ian Rogers2c8f6532011-09-02 17:16:34 -0700475void X86Assembler::mulss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700476 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
477 EmitUint8(0xF3);
478 EmitUint8(0x0F);
479 EmitUint8(0x59);
480 EmitOperand(dst, src);
481}
482
483
Ian Rogers2c8f6532011-09-02 17:16:34 -0700484void X86Assembler::divss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700485 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
486 EmitUint8(0xF3);
487 EmitUint8(0x0F);
488 EmitUint8(0x5E);
489 EmitXmmRegisterOperand(dst, src);
490}
491
492
Ian Rogers2c8f6532011-09-02 17:16:34 -0700493void X86Assembler::divss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700494 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
495 EmitUint8(0xF3);
496 EmitUint8(0x0F);
497 EmitUint8(0x5E);
498 EmitOperand(dst, src);
499}
500
501
Aart Bikc7782262017-01-13 16:20:08 -0800502void X86Assembler::addps(XmmRegister dst, XmmRegister src) {
503 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
504 EmitUint8(0x0F);
505 EmitUint8(0x58);
506 EmitXmmRegisterOperand(dst, src);
507}
508
509
510void X86Assembler::subps(XmmRegister dst, XmmRegister src) {
511 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
512 EmitUint8(0x0F);
513 EmitUint8(0x5C);
514 EmitXmmRegisterOperand(dst, src);
515}
516
517
518void X86Assembler::mulps(XmmRegister dst, XmmRegister src) {
519 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
520 EmitUint8(0x0F);
521 EmitUint8(0x59);
522 EmitXmmRegisterOperand(dst, src);
523}
524
525
526void X86Assembler::divps(XmmRegister dst, XmmRegister src) {
527 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
528 EmitUint8(0x0F);
529 EmitUint8(0x5E);
530 EmitXmmRegisterOperand(dst, src);
531}
532
533
534void X86Assembler::movapd(XmmRegister dst, XmmRegister src) {
535 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
536 EmitUint8(0x66);
537 EmitUint8(0x0F);
538 EmitUint8(0x28);
539 EmitXmmRegisterOperand(dst, src);
540}
541
542
543void X86Assembler::movapd(XmmRegister dst, const Address& src) {
544 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
545 EmitUint8(0x66);
546 EmitUint8(0x0F);
547 EmitUint8(0x28);
548 EmitOperand(dst, src);
549}
550
551
552void X86Assembler::movupd(XmmRegister dst, const Address& src) {
553 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
554 EmitUint8(0x66);
555 EmitUint8(0x0F);
556 EmitUint8(0x10);
557 EmitOperand(dst, src);
558}
559
560
561void X86Assembler::movapd(const Address& dst, XmmRegister src) {
562 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
563 EmitUint8(0x66);
564 EmitUint8(0x0F);
565 EmitUint8(0x29);
566 EmitOperand(src, dst);
567}
568
569
570void X86Assembler::movupd(const Address& dst, XmmRegister src) {
571 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
572 EmitUint8(0x66);
573 EmitUint8(0x0F);
574 EmitUint8(0x11);
575 EmitOperand(src, dst);
576}
577
578
Ian Rogers2c8f6532011-09-02 17:16:34 -0700579void X86Assembler::flds(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700580 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
581 EmitUint8(0xD9);
582 EmitOperand(0, src);
583}
584
585
Mark Mendell24f2dfa2015-01-14 19:51:45 -0500586void X86Assembler::fsts(const Address& dst) {
587 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
588 EmitUint8(0xD9);
589 EmitOperand(2, dst);
590}
591
592
Ian Rogers2c8f6532011-09-02 17:16:34 -0700593void X86Assembler::fstps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700594 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
595 EmitUint8(0xD9);
596 EmitOperand(3, dst);
597}
598
599
Ian Rogers2c8f6532011-09-02 17:16:34 -0700600void X86Assembler::movsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700601 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
602 EmitUint8(0xF2);
603 EmitUint8(0x0F);
604 EmitUint8(0x10);
605 EmitOperand(dst, src);
606}
607
608
Ian Rogers2c8f6532011-09-02 17:16:34 -0700609void X86Assembler::movsd(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700610 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
611 EmitUint8(0xF2);
612 EmitUint8(0x0F);
613 EmitUint8(0x11);
614 EmitOperand(src, dst);
615}
616
617
Ian Rogers2c8f6532011-09-02 17:16:34 -0700618void X86Assembler::movsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700619 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
620 EmitUint8(0xF2);
621 EmitUint8(0x0F);
622 EmitUint8(0x11);
623 EmitXmmRegisterOperand(src, dst);
624}
625
626
Nicolas Geoffray234d69d2015-03-09 10:28:50 +0000627void X86Assembler::movhpd(XmmRegister dst, const Address& src) {
628 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
629 EmitUint8(0x66);
630 EmitUint8(0x0F);
631 EmitUint8(0x16);
632 EmitOperand(dst, src);
633}
634
635
636void X86Assembler::movhpd(const Address& dst, XmmRegister src) {
637 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
638 EmitUint8(0x66);
639 EmitUint8(0x0F);
640 EmitUint8(0x17);
641 EmitOperand(src, dst);
642}
643
644
645void X86Assembler::psrldq(XmmRegister reg, const Immediate& shift_count) {
646 DCHECK(shift_count.is_uint8());
647
648 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
649 EmitUint8(0x66);
650 EmitUint8(0x0F);
651 EmitUint8(0x73);
652 EmitXmmRegisterOperand(3, reg);
653 EmitUint8(shift_count.value());
654}
655
656
Calin Juravle52c48962014-12-16 17:02:57 +0000657void X86Assembler::psrlq(XmmRegister reg, const Immediate& shift_count) {
658 DCHECK(shift_count.is_uint8());
659
660 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
661 EmitUint8(0x66);
662 EmitUint8(0x0F);
663 EmitUint8(0x73);
664 EmitXmmRegisterOperand(2, reg);
665 EmitUint8(shift_count.value());
666}
667
668
669void X86Assembler::punpckldq(XmmRegister dst, XmmRegister src) {
670 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
671 EmitUint8(0x66);
672 EmitUint8(0x0F);
673 EmitUint8(0x62);
674 EmitXmmRegisterOperand(dst, src);
675}
676
677
Ian Rogers2c8f6532011-09-02 17:16:34 -0700678void X86Assembler::addsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700679 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
680 EmitUint8(0xF2);
681 EmitUint8(0x0F);
682 EmitUint8(0x58);
683 EmitXmmRegisterOperand(dst, src);
684}
685
686
Ian Rogers2c8f6532011-09-02 17:16:34 -0700687void X86Assembler::addsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700688 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
689 EmitUint8(0xF2);
690 EmitUint8(0x0F);
691 EmitUint8(0x58);
692 EmitOperand(dst, src);
693}
694
695
Ian Rogers2c8f6532011-09-02 17:16:34 -0700696void X86Assembler::subsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700697 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
698 EmitUint8(0xF2);
699 EmitUint8(0x0F);
700 EmitUint8(0x5C);
701 EmitXmmRegisterOperand(dst, src);
702}
703
704
Ian Rogers2c8f6532011-09-02 17:16:34 -0700705void X86Assembler::subsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700706 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
707 EmitUint8(0xF2);
708 EmitUint8(0x0F);
709 EmitUint8(0x5C);
710 EmitOperand(dst, src);
711}
712
713
Ian Rogers2c8f6532011-09-02 17:16:34 -0700714void X86Assembler::mulsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700715 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
716 EmitUint8(0xF2);
717 EmitUint8(0x0F);
718 EmitUint8(0x59);
719 EmitXmmRegisterOperand(dst, src);
720}
721
722
Ian Rogers2c8f6532011-09-02 17:16:34 -0700723void X86Assembler::mulsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700724 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
725 EmitUint8(0xF2);
726 EmitUint8(0x0F);
727 EmitUint8(0x59);
728 EmitOperand(dst, src);
729}
730
731
Ian Rogers2c8f6532011-09-02 17:16:34 -0700732void X86Assembler::divsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700733 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
734 EmitUint8(0xF2);
735 EmitUint8(0x0F);
736 EmitUint8(0x5E);
737 EmitXmmRegisterOperand(dst, src);
738}
739
740
Ian Rogers2c8f6532011-09-02 17:16:34 -0700741void X86Assembler::divsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700742 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
743 EmitUint8(0xF2);
744 EmitUint8(0x0F);
745 EmitUint8(0x5E);
746 EmitOperand(dst, src);
747}
748
749
Aart Bikc7782262017-01-13 16:20:08 -0800750void X86Assembler::addpd(XmmRegister dst, XmmRegister src) {
751 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
752 EmitUint8(0x66);
753 EmitUint8(0x0F);
754 EmitUint8(0x58);
755 EmitXmmRegisterOperand(dst, src);
756}
757
758
759void X86Assembler::subpd(XmmRegister dst, XmmRegister src) {
760 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
761 EmitUint8(0x66);
762 EmitUint8(0x0F);
763 EmitUint8(0x5C);
764 EmitXmmRegisterOperand(dst, src);
765}
766
767
768void X86Assembler::mulpd(XmmRegister dst, XmmRegister src) {
769 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
770 EmitUint8(0x66);
771 EmitUint8(0x0F);
772 EmitUint8(0x59);
773 EmitXmmRegisterOperand(dst, src);
774}
775
776
777void X86Assembler::divpd(XmmRegister dst, XmmRegister src) {
778 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
779 EmitUint8(0x66);
780 EmitUint8(0x0F);
781 EmitUint8(0x5E);
782 EmitXmmRegisterOperand(dst, src);
783}
784
785
Ian Rogers2c8f6532011-09-02 17:16:34 -0700786void X86Assembler::cvtsi2ss(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700787 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
788 EmitUint8(0xF3);
789 EmitUint8(0x0F);
790 EmitUint8(0x2A);
791 EmitOperand(dst, Operand(src));
792}
793
794
Ian Rogers2c8f6532011-09-02 17:16:34 -0700795void X86Assembler::cvtsi2sd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700796 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
797 EmitUint8(0xF2);
798 EmitUint8(0x0F);
799 EmitUint8(0x2A);
800 EmitOperand(dst, Operand(src));
801}
802
803
Ian Rogers2c8f6532011-09-02 17:16:34 -0700804void X86Assembler::cvtss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700805 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
806 EmitUint8(0xF3);
807 EmitUint8(0x0F);
808 EmitUint8(0x2D);
809 EmitXmmRegisterOperand(dst, src);
810}
811
812
Ian Rogers2c8f6532011-09-02 17:16:34 -0700813void X86Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700814 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
815 EmitUint8(0xF3);
816 EmitUint8(0x0F);
817 EmitUint8(0x5A);
818 EmitXmmRegisterOperand(dst, src);
819}
820
821
Ian Rogers2c8f6532011-09-02 17:16:34 -0700822void X86Assembler::cvtsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700823 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
824 EmitUint8(0xF2);
825 EmitUint8(0x0F);
826 EmitUint8(0x2D);
827 EmitXmmRegisterOperand(dst, src);
828}
829
830
Ian Rogers2c8f6532011-09-02 17:16:34 -0700831void X86Assembler::cvttss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700832 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
833 EmitUint8(0xF3);
834 EmitUint8(0x0F);
835 EmitUint8(0x2C);
836 EmitXmmRegisterOperand(dst, src);
837}
838
839
Ian Rogers2c8f6532011-09-02 17:16:34 -0700840void X86Assembler::cvttsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700841 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
842 EmitUint8(0xF2);
843 EmitUint8(0x0F);
844 EmitUint8(0x2C);
845 EmitXmmRegisterOperand(dst, src);
846}
847
848
Ian Rogers2c8f6532011-09-02 17:16:34 -0700849void X86Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700850 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
851 EmitUint8(0xF2);
852 EmitUint8(0x0F);
853 EmitUint8(0x5A);
854 EmitXmmRegisterOperand(dst, src);
855}
856
857
Ian Rogers2c8f6532011-09-02 17:16:34 -0700858void X86Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700859 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
860 EmitUint8(0xF3);
861 EmitUint8(0x0F);
862 EmitUint8(0xE6);
863 EmitXmmRegisterOperand(dst, src);
864}
865
866
Ian Rogers2c8f6532011-09-02 17:16:34 -0700867void X86Assembler::comiss(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700868 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
869 EmitUint8(0x0F);
870 EmitUint8(0x2F);
871 EmitXmmRegisterOperand(a, b);
872}
873
874
Aart Bik18ba1212016-08-01 14:11:20 -0700875void X86Assembler::comiss(XmmRegister a, const Address& b) {
876 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
877 EmitUint8(0x0F);
878 EmitUint8(0x2F);
879 EmitOperand(a, b);
880}
881
882
Ian Rogers2c8f6532011-09-02 17:16:34 -0700883void X86Assembler::comisd(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700884 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
885 EmitUint8(0x66);
886 EmitUint8(0x0F);
887 EmitUint8(0x2F);
888 EmitXmmRegisterOperand(a, b);
889}
890
891
Aart Bik18ba1212016-08-01 14:11:20 -0700892void X86Assembler::comisd(XmmRegister a, const Address& b) {
893 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
894 EmitUint8(0x66);
895 EmitUint8(0x0F);
896 EmitUint8(0x2F);
897 EmitOperand(a, b);
898}
899
900
Calin Juravleddb7df22014-11-25 20:56:51 +0000901void X86Assembler::ucomiss(XmmRegister a, XmmRegister b) {
902 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
903 EmitUint8(0x0F);
904 EmitUint8(0x2E);
905 EmitXmmRegisterOperand(a, b);
906}
907
908
Mark Mendell9f51f262015-10-30 09:21:37 -0400909void X86Assembler::ucomiss(XmmRegister a, const Address& b) {
910 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
911 EmitUint8(0x0F);
912 EmitUint8(0x2E);
913 EmitOperand(a, b);
914}
915
916
Calin Juravleddb7df22014-11-25 20:56:51 +0000917void X86Assembler::ucomisd(XmmRegister a, XmmRegister b) {
918 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
919 EmitUint8(0x66);
920 EmitUint8(0x0F);
921 EmitUint8(0x2E);
922 EmitXmmRegisterOperand(a, b);
923}
924
925
Mark Mendell9f51f262015-10-30 09:21:37 -0400926void X86Assembler::ucomisd(XmmRegister a, const Address& b) {
927 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
928 EmitUint8(0x66);
929 EmitUint8(0x0F);
930 EmitUint8(0x2E);
931 EmitOperand(a, b);
932}
933
934
Mark Mendellfb8d2792015-03-31 22:16:59 -0400935void X86Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
936 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
937 EmitUint8(0x66);
938 EmitUint8(0x0F);
939 EmitUint8(0x3A);
940 EmitUint8(0x0B);
941 EmitXmmRegisterOperand(dst, src);
942 EmitUint8(imm.value());
943}
944
945
946void X86Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) {
947 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
948 EmitUint8(0x66);
949 EmitUint8(0x0F);
950 EmitUint8(0x3A);
951 EmitUint8(0x0A);
952 EmitXmmRegisterOperand(dst, src);
953 EmitUint8(imm.value());
954}
955
956
Ian Rogers2c8f6532011-09-02 17:16:34 -0700957void X86Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700958 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
959 EmitUint8(0xF2);
960 EmitUint8(0x0F);
961 EmitUint8(0x51);
962 EmitXmmRegisterOperand(dst, src);
963}
964
965
Ian Rogers2c8f6532011-09-02 17:16:34 -0700966void X86Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700967 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
968 EmitUint8(0xF3);
969 EmitUint8(0x0F);
970 EmitUint8(0x51);
971 EmitXmmRegisterOperand(dst, src);
972}
973
974
Ian Rogers2c8f6532011-09-02 17:16:34 -0700975void X86Assembler::xorpd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700976 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
977 EmitUint8(0x66);
978 EmitUint8(0x0F);
979 EmitUint8(0x57);
980 EmitOperand(dst, src);
981}
982
983
Ian Rogers2c8f6532011-09-02 17:16:34 -0700984void X86Assembler::xorpd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700985 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
986 EmitUint8(0x66);
987 EmitUint8(0x0F);
988 EmitUint8(0x57);
989 EmitXmmRegisterOperand(dst, src);
990}
991
992
Mark Mendell09ed1a32015-03-25 08:30:06 -0400993void X86Assembler::andps(XmmRegister dst, XmmRegister src) {
994 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
995 EmitUint8(0x0F);
996 EmitUint8(0x54);
997 EmitXmmRegisterOperand(dst, src);
998}
999
1000
1001void X86Assembler::andpd(XmmRegister dst, XmmRegister src) {
1002 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1003 EmitUint8(0x66);
1004 EmitUint8(0x0F);
1005 EmitUint8(0x54);
1006 EmitXmmRegisterOperand(dst, src);
1007}
1008
1009
1010void X86Assembler::orpd(XmmRegister dst, XmmRegister src) {
1011 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1012 EmitUint8(0x66);
1013 EmitUint8(0x0F);
1014 EmitUint8(0x56);
1015 EmitXmmRegisterOperand(dst, src);
1016}
1017
1018
Ian Rogers2c8f6532011-09-02 17:16:34 -07001019void X86Assembler::xorps(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001020 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1021 EmitUint8(0x0F);
1022 EmitUint8(0x57);
1023 EmitOperand(dst, src);
1024}
1025
1026
Mark Mendell09ed1a32015-03-25 08:30:06 -04001027void X86Assembler::orps(XmmRegister dst, XmmRegister src) {
1028 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1029 EmitUint8(0x0F);
1030 EmitUint8(0x56);
1031 EmitXmmRegisterOperand(dst, src);
1032}
1033
1034
Ian Rogers2c8f6532011-09-02 17:16:34 -07001035void X86Assembler::xorps(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001036 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1037 EmitUint8(0x0F);
1038 EmitUint8(0x57);
1039 EmitXmmRegisterOperand(dst, src);
1040}
1041
1042
Mark Mendell09ed1a32015-03-25 08:30:06 -04001043void X86Assembler::andps(XmmRegister dst, const Address& src) {
1044 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1045 EmitUint8(0x0F);
1046 EmitUint8(0x54);
1047 EmitOperand(dst, src);
1048}
1049
1050
Ian Rogers2c8f6532011-09-02 17:16:34 -07001051void X86Assembler::andpd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001052 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1053 EmitUint8(0x66);
1054 EmitUint8(0x0F);
1055 EmitUint8(0x54);
1056 EmitOperand(dst, src);
1057}
1058
1059
Aart Bik12e06ed2017-01-31 16:11:24 -08001060void X86Assembler::shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1061 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1062 EmitUint8(0x66);
1063 EmitUint8(0x0F);
1064 EmitUint8(0xC6);
1065 EmitXmmRegisterOperand(dst, src);
1066 EmitUint8(imm.value());
1067}
1068
1069
1070void X86Assembler::shufps(XmmRegister dst, XmmRegister src, const Immediate& imm) {
1071 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1072 EmitUint8(0x0F);
1073 EmitUint8(0xC6);
1074 EmitXmmRegisterOperand(dst, src);
1075 EmitUint8(imm.value());
1076}
1077
1078
Ian Rogers2c8f6532011-09-02 17:16:34 -07001079void X86Assembler::fldl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001080 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1081 EmitUint8(0xDD);
1082 EmitOperand(0, src);
1083}
1084
1085
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001086void X86Assembler::fstl(const Address& dst) {
1087 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1088 EmitUint8(0xDD);
1089 EmitOperand(2, dst);
1090}
1091
1092
Ian Rogers2c8f6532011-09-02 17:16:34 -07001093void X86Assembler::fstpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001094 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1095 EmitUint8(0xDD);
1096 EmitOperand(3, dst);
1097}
1098
1099
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001100void X86Assembler::fstsw() {
1101 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1102 EmitUint8(0x9B);
1103 EmitUint8(0xDF);
1104 EmitUint8(0xE0);
1105}
1106
1107
Ian Rogers2c8f6532011-09-02 17:16:34 -07001108void X86Assembler::fnstcw(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001109 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1110 EmitUint8(0xD9);
1111 EmitOperand(7, dst);
1112}
1113
1114
Ian Rogers2c8f6532011-09-02 17:16:34 -07001115void X86Assembler::fldcw(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001116 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1117 EmitUint8(0xD9);
1118 EmitOperand(5, src);
1119}
1120
1121
Ian Rogers2c8f6532011-09-02 17:16:34 -07001122void X86Assembler::fistpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001123 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1124 EmitUint8(0xDF);
1125 EmitOperand(7, dst);
1126}
1127
1128
Ian Rogers2c8f6532011-09-02 17:16:34 -07001129void X86Assembler::fistps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001130 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1131 EmitUint8(0xDB);
1132 EmitOperand(3, dst);
1133}
1134
1135
Ian Rogers2c8f6532011-09-02 17:16:34 -07001136void X86Assembler::fildl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001137 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1138 EmitUint8(0xDF);
1139 EmitOperand(5, src);
1140}
1141
1142
Roland Levillain0a186012015-04-13 17:00:20 +01001143void X86Assembler::filds(const Address& src) {
1144 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1145 EmitUint8(0xDB);
1146 EmitOperand(0, src);
1147}
1148
1149
Ian Rogers2c8f6532011-09-02 17:16:34 -07001150void X86Assembler::fincstp() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001151 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1152 EmitUint8(0xD9);
1153 EmitUint8(0xF7);
1154}
1155
1156
Ian Rogers2c8f6532011-09-02 17:16:34 -07001157void X86Assembler::ffree(const Immediate& index) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001158 CHECK_LT(index.value(), 7);
1159 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1160 EmitUint8(0xDD);
1161 EmitUint8(0xC0 + index.value());
1162}
1163
1164
Ian Rogers2c8f6532011-09-02 17:16:34 -07001165void X86Assembler::fsin() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001166 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1167 EmitUint8(0xD9);
1168 EmitUint8(0xFE);
1169}
1170
1171
Ian Rogers2c8f6532011-09-02 17:16:34 -07001172void X86Assembler::fcos() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001173 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1174 EmitUint8(0xD9);
1175 EmitUint8(0xFF);
1176}
1177
1178
Ian Rogers2c8f6532011-09-02 17:16:34 -07001179void X86Assembler::fptan() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001180 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1181 EmitUint8(0xD9);
1182 EmitUint8(0xF2);
1183}
1184
1185
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001186void X86Assembler::fucompp() {
1187 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1188 EmitUint8(0xDA);
1189 EmitUint8(0xE9);
1190}
1191
1192
1193void X86Assembler::fprem() {
1194 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1195 EmitUint8(0xD9);
1196 EmitUint8(0xF8);
1197}
1198
1199
Ian Rogers2c8f6532011-09-02 17:16:34 -07001200void X86Assembler::xchgl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001201 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1202 EmitUint8(0x87);
1203 EmitRegisterOperand(dst, src);
1204}
1205
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001206
Ian Rogers7caad772012-03-30 01:07:54 -07001207void X86Assembler::xchgl(Register reg, const Address& address) {
1208 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1209 EmitUint8(0x87);
1210 EmitOperand(reg, address);
1211}
1212
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001213
Serguei Katkov3b625932016-05-06 10:24:17 +06001214void X86Assembler::cmpb(const Address& address, const Immediate& imm) {
1215 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1216 EmitUint8(0x80);
1217 EmitOperand(7, address);
1218 EmitUint8(imm.value() & 0xFF);
1219}
1220
1221
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001222void X86Assembler::cmpw(const Address& address, const Immediate& imm) {
1223 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1224 EmitUint8(0x66);
1225 EmitComplex(7, address, imm);
1226}
1227
1228
Ian Rogers2c8f6532011-09-02 17:16:34 -07001229void X86Assembler::cmpl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001230 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1231 EmitComplex(7, Operand(reg), imm);
1232}
1233
1234
Ian Rogers2c8f6532011-09-02 17:16:34 -07001235void X86Assembler::cmpl(Register reg0, Register reg1) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001236 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1237 EmitUint8(0x3B);
1238 EmitOperand(reg0, Operand(reg1));
1239}
1240
1241
Ian Rogers2c8f6532011-09-02 17:16:34 -07001242void X86Assembler::cmpl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001243 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1244 EmitUint8(0x3B);
1245 EmitOperand(reg, address);
1246}
1247
1248
Ian Rogers2c8f6532011-09-02 17:16:34 -07001249void X86Assembler::addl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001250 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1251 EmitUint8(0x03);
1252 EmitRegisterOperand(dst, src);
1253}
1254
1255
Ian Rogers2c8f6532011-09-02 17:16:34 -07001256void X86Assembler::addl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001257 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1258 EmitUint8(0x03);
1259 EmitOperand(reg, address);
1260}
1261
1262
Ian Rogers2c8f6532011-09-02 17:16:34 -07001263void X86Assembler::cmpl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001264 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1265 EmitUint8(0x39);
1266 EmitOperand(reg, address);
1267}
1268
1269
Ian Rogers2c8f6532011-09-02 17:16:34 -07001270void X86Assembler::cmpl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001271 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1272 EmitComplex(7, address, imm);
1273}
1274
1275
Ian Rogers2c8f6532011-09-02 17:16:34 -07001276void X86Assembler::testl(Register reg1, Register reg2) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001277 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1278 EmitUint8(0x85);
1279 EmitRegisterOperand(reg1, reg2);
1280}
1281
1282
Nicolas Geoffrayf12feb82014-07-17 18:32:41 +01001283void X86Assembler::testl(Register reg, const Address& address) {
1284 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1285 EmitUint8(0x85);
1286 EmitOperand(reg, address);
1287}
1288
1289
Ian Rogers2c8f6532011-09-02 17:16:34 -07001290void X86Assembler::testl(Register reg, const Immediate& immediate) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001291 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1292 // For registers that have a byte variant (EAX, EBX, ECX, and EDX)
1293 // we only test the byte register to keep the encoding short.
1294 if (immediate.is_uint8() && reg < 4) {
1295 // Use zero-extended 8-bit immediate.
1296 if (reg == EAX) {
1297 EmitUint8(0xA8);
1298 } else {
1299 EmitUint8(0xF6);
1300 EmitUint8(0xC0 + reg);
1301 }
1302 EmitUint8(immediate.value() & 0xFF);
1303 } else if (reg == EAX) {
1304 // Use short form if the destination is EAX.
1305 EmitUint8(0xA9);
1306 EmitImmediate(immediate);
1307 } else {
1308 EmitUint8(0xF7);
1309 EmitOperand(0, Operand(reg));
1310 EmitImmediate(immediate);
1311 }
1312}
1313
1314
Vladimir Marko953437b2016-08-24 08:30:46 +00001315void X86Assembler::testb(const Address& dst, const Immediate& imm) {
1316 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1317 EmitUint8(0xF6);
1318 EmitOperand(EAX, dst);
1319 CHECK(imm.is_int8());
1320 EmitUint8(imm.value() & 0xFF);
1321}
1322
1323
1324void X86Assembler::testl(const Address& dst, const Immediate& imm) {
1325 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1326 EmitUint8(0xF7);
1327 EmitOperand(0, dst);
1328 EmitImmediate(imm);
1329}
1330
1331
Ian Rogers2c8f6532011-09-02 17:16:34 -07001332void X86Assembler::andl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001333 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1334 EmitUint8(0x23);
1335 EmitOperand(dst, Operand(src));
1336}
1337
1338
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001339void X86Assembler::andl(Register reg, const Address& address) {
1340 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1341 EmitUint8(0x23);
1342 EmitOperand(reg, address);
1343}
1344
1345
Ian Rogers2c8f6532011-09-02 17:16:34 -07001346void X86Assembler::andl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001347 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1348 EmitComplex(4, Operand(dst), imm);
1349}
1350
1351
Ian Rogers2c8f6532011-09-02 17:16:34 -07001352void X86Assembler::orl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001353 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1354 EmitUint8(0x0B);
1355 EmitOperand(dst, Operand(src));
1356}
1357
1358
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001359void X86Assembler::orl(Register reg, const Address& address) {
1360 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1361 EmitUint8(0x0B);
1362 EmitOperand(reg, address);
1363}
1364
1365
Ian Rogers2c8f6532011-09-02 17:16:34 -07001366void X86Assembler::orl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001367 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1368 EmitComplex(1, Operand(dst), imm);
1369}
1370
1371
Ian Rogers2c8f6532011-09-02 17:16:34 -07001372void X86Assembler::xorl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001373 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1374 EmitUint8(0x33);
1375 EmitOperand(dst, Operand(src));
1376}
1377
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001378
1379void X86Assembler::xorl(Register reg, const Address& address) {
1380 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1381 EmitUint8(0x33);
1382 EmitOperand(reg, address);
1383}
1384
1385
Nicolas Geoffrayb55f8352014-04-07 15:26:35 +01001386void X86Assembler::xorl(Register dst, const Immediate& imm) {
1387 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1388 EmitComplex(6, Operand(dst), imm);
1389}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001390
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001391
Ian Rogers2c8f6532011-09-02 17:16:34 -07001392void X86Assembler::addl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001393 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1394 EmitComplex(0, Operand(reg), imm);
1395}
1396
1397
Ian Rogers2c8f6532011-09-02 17:16:34 -07001398void X86Assembler::addl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001399 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1400 EmitUint8(0x01);
1401 EmitOperand(reg, address);
1402}
1403
1404
Ian Rogers2c8f6532011-09-02 17:16:34 -07001405void X86Assembler::addl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001406 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1407 EmitComplex(0, address, imm);
1408}
1409
1410
Ian Rogers2c8f6532011-09-02 17:16:34 -07001411void X86Assembler::adcl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001412 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1413 EmitComplex(2, Operand(reg), imm);
1414}
1415
1416
Ian Rogers2c8f6532011-09-02 17:16:34 -07001417void X86Assembler::adcl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001418 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1419 EmitUint8(0x13);
1420 EmitOperand(dst, Operand(src));
1421}
1422
1423
Ian Rogers2c8f6532011-09-02 17:16:34 -07001424void X86Assembler::adcl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001425 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1426 EmitUint8(0x13);
1427 EmitOperand(dst, address);
1428}
1429
1430
Ian Rogers2c8f6532011-09-02 17:16:34 -07001431void X86Assembler::subl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001432 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1433 EmitUint8(0x2B);
1434 EmitOperand(dst, Operand(src));
1435}
1436
1437
Ian Rogers2c8f6532011-09-02 17:16:34 -07001438void X86Assembler::subl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001439 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1440 EmitComplex(5, Operand(reg), imm);
1441}
1442
1443
Ian Rogers2c8f6532011-09-02 17:16:34 -07001444void X86Assembler::subl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001445 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1446 EmitUint8(0x2B);
1447 EmitOperand(reg, address);
1448}
1449
1450
Mark Mendell09ed1a32015-03-25 08:30:06 -04001451void X86Assembler::subl(const Address& address, Register reg) {
1452 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1453 EmitUint8(0x29);
1454 EmitOperand(reg, address);
1455}
1456
1457
Ian Rogers2c8f6532011-09-02 17:16:34 -07001458void X86Assembler::cdq() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001459 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1460 EmitUint8(0x99);
1461}
1462
1463
Ian Rogers2c8f6532011-09-02 17:16:34 -07001464void X86Assembler::idivl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001465 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1466 EmitUint8(0xF7);
1467 EmitUint8(0xF8 | reg);
1468}
1469
1470
Ian Rogers2c8f6532011-09-02 17:16:34 -07001471void X86Assembler::imull(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001472 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1473 EmitUint8(0x0F);
1474 EmitUint8(0xAF);
1475 EmitOperand(dst, Operand(src));
1476}
1477
1478
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04001479void X86Assembler::imull(Register dst, Register src, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001480 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04001481 // See whether imm can be represented as a sign-extended 8bit value.
1482 int32_t v32 = static_cast<int32_t>(imm.value());
1483 if (IsInt<8>(v32)) {
1484 // Sign-extension works.
1485 EmitUint8(0x6B);
1486 EmitOperand(dst, Operand(src));
1487 EmitUint8(static_cast<uint8_t>(v32 & 0xFF));
1488 } else {
1489 // Not representable, use full immediate.
1490 EmitUint8(0x69);
1491 EmitOperand(dst, Operand(src));
1492 EmitImmediate(imm);
1493 }
1494}
1495
1496
1497void X86Assembler::imull(Register reg, const Immediate& imm) {
1498 imull(reg, reg, imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001499}
1500
1501
Ian Rogers2c8f6532011-09-02 17:16:34 -07001502void X86Assembler::imull(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001503 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1504 EmitUint8(0x0F);
1505 EmitUint8(0xAF);
1506 EmitOperand(reg, address);
1507}
1508
1509
Ian Rogers2c8f6532011-09-02 17:16:34 -07001510void X86Assembler::imull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001511 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1512 EmitUint8(0xF7);
1513 EmitOperand(5, Operand(reg));
1514}
1515
1516
Ian Rogers2c8f6532011-09-02 17:16:34 -07001517void X86Assembler::imull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001518 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1519 EmitUint8(0xF7);
1520 EmitOperand(5, address);
1521}
1522
1523
Ian Rogers2c8f6532011-09-02 17:16:34 -07001524void X86Assembler::mull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001525 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1526 EmitUint8(0xF7);
1527 EmitOperand(4, Operand(reg));
1528}
1529
1530
Ian Rogers2c8f6532011-09-02 17:16:34 -07001531void X86Assembler::mull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001532 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1533 EmitUint8(0xF7);
1534 EmitOperand(4, address);
1535}
1536
1537
Ian Rogers2c8f6532011-09-02 17:16:34 -07001538void X86Assembler::sbbl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001539 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1540 EmitUint8(0x1B);
1541 EmitOperand(dst, Operand(src));
1542}
1543
1544
Ian Rogers2c8f6532011-09-02 17:16:34 -07001545void X86Assembler::sbbl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001546 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1547 EmitComplex(3, Operand(reg), imm);
1548}
1549
1550
Ian Rogers2c8f6532011-09-02 17:16:34 -07001551void X86Assembler::sbbl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001552 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1553 EmitUint8(0x1B);
1554 EmitOperand(dst, address);
1555}
1556
1557
Mark Mendell09ed1a32015-03-25 08:30:06 -04001558void X86Assembler::sbbl(const Address& address, Register src) {
1559 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1560 EmitUint8(0x19);
1561 EmitOperand(src, address);
1562}
1563
1564
Ian Rogers2c8f6532011-09-02 17:16:34 -07001565void X86Assembler::incl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001566 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1567 EmitUint8(0x40 + reg);
1568}
1569
1570
Ian Rogers2c8f6532011-09-02 17:16:34 -07001571void X86Assembler::incl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001572 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1573 EmitUint8(0xFF);
1574 EmitOperand(0, address);
1575}
1576
1577
Ian Rogers2c8f6532011-09-02 17:16:34 -07001578void X86Assembler::decl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001579 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1580 EmitUint8(0x48 + reg);
1581}
1582
1583
Ian Rogers2c8f6532011-09-02 17:16:34 -07001584void X86Assembler::decl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001585 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1586 EmitUint8(0xFF);
1587 EmitOperand(1, address);
1588}
1589
1590
Ian Rogers2c8f6532011-09-02 17:16:34 -07001591void X86Assembler::shll(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00001592 EmitGenericShift(4, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001593}
1594
1595
Ian Rogers2c8f6532011-09-02 17:16:34 -07001596void X86Assembler::shll(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00001597 EmitGenericShift(4, Operand(operand), shifter);
1598}
1599
1600
1601void X86Assembler::shll(const Address& address, const Immediate& imm) {
1602 EmitGenericShift(4, address, imm);
1603}
1604
1605
1606void X86Assembler::shll(const Address& address, Register shifter) {
1607 EmitGenericShift(4, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001608}
1609
1610
Ian Rogers2c8f6532011-09-02 17:16:34 -07001611void X86Assembler::shrl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00001612 EmitGenericShift(5, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001613}
1614
1615
Ian Rogers2c8f6532011-09-02 17:16:34 -07001616void X86Assembler::shrl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00001617 EmitGenericShift(5, Operand(operand), shifter);
1618}
1619
1620
1621void X86Assembler::shrl(const Address& address, const Immediate& imm) {
1622 EmitGenericShift(5, address, imm);
1623}
1624
1625
1626void X86Assembler::shrl(const Address& address, Register shifter) {
1627 EmitGenericShift(5, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001628}
1629
1630
Ian Rogers2c8f6532011-09-02 17:16:34 -07001631void X86Assembler::sarl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00001632 EmitGenericShift(7, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001633}
1634
1635
Ian Rogers2c8f6532011-09-02 17:16:34 -07001636void X86Assembler::sarl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00001637 EmitGenericShift(7, Operand(operand), shifter);
1638}
1639
1640
1641void X86Assembler::sarl(const Address& address, const Immediate& imm) {
1642 EmitGenericShift(7, address, imm);
1643}
1644
1645
1646void X86Assembler::sarl(const Address& address, Register shifter) {
1647 EmitGenericShift(7, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001648}
1649
1650
Calin Juravle9aec02f2014-11-18 23:06:35 +00001651void X86Assembler::shld(Register dst, Register src, Register shifter) {
1652 DCHECK_EQ(ECX, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001653 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1654 EmitUint8(0x0F);
1655 EmitUint8(0xA5);
1656 EmitRegisterOperand(src, dst);
1657}
1658
1659
Mark P Mendell73945692015-04-29 14:56:17 +00001660void X86Assembler::shld(Register dst, Register src, const Immediate& imm) {
1661 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1662 EmitUint8(0x0F);
1663 EmitUint8(0xA4);
1664 EmitRegisterOperand(src, dst);
1665 EmitUint8(imm.value() & 0xFF);
1666}
1667
1668
Calin Juravle9aec02f2014-11-18 23:06:35 +00001669void X86Assembler::shrd(Register dst, Register src, Register shifter) {
1670 DCHECK_EQ(ECX, shifter);
1671 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1672 EmitUint8(0x0F);
1673 EmitUint8(0xAD);
1674 EmitRegisterOperand(src, dst);
1675}
1676
1677
Mark P Mendell73945692015-04-29 14:56:17 +00001678void X86Assembler::shrd(Register dst, Register src, const Immediate& imm) {
1679 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1680 EmitUint8(0x0F);
1681 EmitUint8(0xAC);
1682 EmitRegisterOperand(src, dst);
1683 EmitUint8(imm.value() & 0xFF);
1684}
1685
1686
Mark Mendellbcee0922015-09-15 21:45:01 -04001687void X86Assembler::roll(Register reg, const Immediate& imm) {
1688 EmitGenericShift(0, Operand(reg), imm);
1689}
1690
1691
1692void X86Assembler::roll(Register operand, Register shifter) {
1693 EmitGenericShift(0, Operand(operand), shifter);
1694}
1695
1696
1697void X86Assembler::rorl(Register reg, const Immediate& imm) {
1698 EmitGenericShift(1, Operand(reg), imm);
1699}
1700
1701
1702void X86Assembler::rorl(Register operand, Register shifter) {
1703 EmitGenericShift(1, Operand(operand), shifter);
1704}
1705
1706
Ian Rogers2c8f6532011-09-02 17:16:34 -07001707void X86Assembler::negl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001708 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1709 EmitUint8(0xF7);
1710 EmitOperand(3, Operand(reg));
1711}
1712
1713
Ian Rogers2c8f6532011-09-02 17:16:34 -07001714void X86Assembler::notl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001715 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1716 EmitUint8(0xF7);
1717 EmitUint8(0xD0 | reg);
1718}
1719
1720
Ian Rogers2c8f6532011-09-02 17:16:34 -07001721void X86Assembler::enter(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001722 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1723 EmitUint8(0xC8);
1724 CHECK(imm.is_uint16());
1725 EmitUint8(imm.value() & 0xFF);
1726 EmitUint8((imm.value() >> 8) & 0xFF);
1727 EmitUint8(0x00);
1728}
1729
1730
Ian Rogers2c8f6532011-09-02 17:16:34 -07001731void X86Assembler::leave() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001732 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1733 EmitUint8(0xC9);
1734}
1735
1736
Ian Rogers2c8f6532011-09-02 17:16:34 -07001737void X86Assembler::ret() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001738 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1739 EmitUint8(0xC3);
1740}
1741
1742
Ian Rogers2c8f6532011-09-02 17:16:34 -07001743void X86Assembler::ret(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001744 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1745 EmitUint8(0xC2);
1746 CHECK(imm.is_uint16());
1747 EmitUint8(imm.value() & 0xFF);
1748 EmitUint8((imm.value() >> 8) & 0xFF);
1749}
1750
1751
1752
Ian Rogers2c8f6532011-09-02 17:16:34 -07001753void X86Assembler::nop() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001754 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1755 EmitUint8(0x90);
1756}
1757
1758
Ian Rogers2c8f6532011-09-02 17:16:34 -07001759void X86Assembler::int3() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001760 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1761 EmitUint8(0xCC);
1762}
1763
1764
Ian Rogers2c8f6532011-09-02 17:16:34 -07001765void X86Assembler::hlt() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001766 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1767 EmitUint8(0xF4);
1768}
1769
1770
Ian Rogers2c8f6532011-09-02 17:16:34 -07001771void X86Assembler::j(Condition condition, Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001772 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1773 if (label->IsBound()) {
1774 static const int kShortSize = 2;
1775 static const int kLongSize = 6;
1776 int offset = label->Position() - buffer_.Size();
1777 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08001778 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001779 EmitUint8(0x70 + condition);
1780 EmitUint8((offset - kShortSize) & 0xFF);
1781 } else {
1782 EmitUint8(0x0F);
1783 EmitUint8(0x80 + condition);
1784 EmitInt32(offset - kLongSize);
1785 }
1786 } else {
1787 EmitUint8(0x0F);
1788 EmitUint8(0x80 + condition);
1789 EmitLabelLink(label);
1790 }
1791}
1792
1793
Mark Mendell73f455e2015-08-21 09:30:05 -04001794void X86Assembler::j(Condition condition, NearLabel* label) {
1795 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1796 if (label->IsBound()) {
1797 static const int kShortSize = 2;
1798 int offset = label->Position() - buffer_.Size();
1799 CHECK_LE(offset, 0);
1800 CHECK(IsInt<8>(offset - kShortSize));
1801 EmitUint8(0x70 + condition);
1802 EmitUint8((offset - kShortSize) & 0xFF);
1803 } else {
1804 EmitUint8(0x70 + condition);
1805 EmitLabelLink(label);
1806 }
1807}
1808
1809
1810void X86Assembler::jecxz(NearLabel* label) {
1811 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1812 if (label->IsBound()) {
1813 static const int kShortSize = 2;
1814 int offset = label->Position() - buffer_.Size();
1815 CHECK_LE(offset, 0);
1816 CHECK(IsInt<8>(offset - kShortSize));
1817 EmitUint8(0xE3);
1818 EmitUint8((offset - kShortSize) & 0xFF);
1819 } else {
1820 EmitUint8(0xE3);
1821 EmitLabelLink(label);
1822 }
1823}
1824
1825
Ian Rogers2c8f6532011-09-02 17:16:34 -07001826void X86Assembler::jmp(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001827 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1828 EmitUint8(0xFF);
1829 EmitRegisterOperand(4, reg);
1830}
1831
Ian Rogers7caad772012-03-30 01:07:54 -07001832void X86Assembler::jmp(const Address& address) {
1833 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1834 EmitUint8(0xFF);
1835 EmitOperand(4, address);
1836}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001837
Ian Rogers2c8f6532011-09-02 17:16:34 -07001838void X86Assembler::jmp(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001839 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1840 if (label->IsBound()) {
1841 static const int kShortSize = 2;
1842 static const int kLongSize = 5;
1843 int offset = label->Position() - buffer_.Size();
1844 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08001845 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001846 EmitUint8(0xEB);
1847 EmitUint8((offset - kShortSize) & 0xFF);
1848 } else {
1849 EmitUint8(0xE9);
1850 EmitInt32(offset - kLongSize);
1851 }
1852 } else {
1853 EmitUint8(0xE9);
1854 EmitLabelLink(label);
1855 }
1856}
1857
1858
Mark Mendell73f455e2015-08-21 09:30:05 -04001859void X86Assembler::jmp(NearLabel* label) {
1860 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1861 if (label->IsBound()) {
1862 static const int kShortSize = 2;
1863 int offset = label->Position() - buffer_.Size();
1864 CHECK_LE(offset, 0);
1865 CHECK(IsInt<8>(offset - kShortSize));
1866 EmitUint8(0xEB);
1867 EmitUint8((offset - kShortSize) & 0xFF);
1868 } else {
1869 EmitUint8(0xEB);
1870 EmitLabelLink(label);
1871 }
1872}
1873
1874
jessicahandojob03d6402016-09-07 12:16:53 -07001875void X86Assembler::repne_scasb() {
1876 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1877 EmitUint8(0xF2);
1878 EmitUint8(0xAE);
1879}
1880
1881
Andreas Gampe21030dd2015-05-07 14:46:15 -07001882void X86Assembler::repne_scasw() {
1883 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1884 EmitUint8(0x66);
1885 EmitUint8(0xF2);
1886 EmitUint8(0xAF);
1887}
1888
1889
jessicahandojob03d6402016-09-07 12:16:53 -07001890void X86Assembler::repe_cmpsb() {
1891 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1892 EmitUint8(0xF2);
1893 EmitUint8(0xA6);
1894}
1895
1896
agicsaki71311f82015-07-27 11:34:13 -07001897void X86Assembler::repe_cmpsw() {
1898 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1899 EmitUint8(0x66);
1900 EmitUint8(0xF3);
1901 EmitUint8(0xA7);
1902}
1903
1904
agicsaki970abfb2015-07-31 10:31:14 -07001905void X86Assembler::repe_cmpsl() {
1906 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1907 EmitUint8(0xF3);
1908 EmitUint8(0xA7);
1909}
1910
1911
jessicahandojob03d6402016-09-07 12:16:53 -07001912void X86Assembler::rep_movsb() {
1913 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1914 EmitUint8(0xF3);
1915 EmitUint8(0xA4);
1916}
1917
1918
Mark Mendellb9c4bbe2015-07-01 14:26:52 -04001919void X86Assembler::rep_movsw() {
1920 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1921 EmitUint8(0x66);
1922 EmitUint8(0xF3);
1923 EmitUint8(0xA5);
1924}
1925
1926
Ian Rogers2c8f6532011-09-02 17:16:34 -07001927X86Assembler* X86Assembler::lock() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001928 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1929 EmitUint8(0xF0);
Ian Rogers0d666d82011-08-14 16:03:46 -07001930 return this;
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001931}
1932
1933
Ian Rogers2c8f6532011-09-02 17:16:34 -07001934void X86Assembler::cmpxchgl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001935 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1936 EmitUint8(0x0F);
1937 EmitUint8(0xB1);
1938 EmitOperand(reg, address);
1939}
1940
Mark Mendell58d25fd2015-04-03 14:52:31 -04001941
1942void X86Assembler::cmpxchg8b(const Address& address) {
1943 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1944 EmitUint8(0x0F);
1945 EmitUint8(0xC7);
1946 EmitOperand(1, address);
1947}
1948
1949
Elliott Hughes79ab9e32012-03-12 15:41:35 -07001950void X86Assembler::mfence() {
1951 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1952 EmitUint8(0x0F);
1953 EmitUint8(0xAE);
1954 EmitUint8(0xF0);
1955}
1956
Ian Rogers2c8f6532011-09-02 17:16:34 -07001957X86Assembler* X86Assembler::fs() {
Ian Rogersb033c752011-07-20 12:22:35 -07001958 // TODO: fs is a prefix and not an instruction
1959 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1960 EmitUint8(0x64);
Ian Rogers0d666d82011-08-14 16:03:46 -07001961 return this;
Ian Rogersb033c752011-07-20 12:22:35 -07001962}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001963
Ian Rogersbefbd572014-03-06 01:13:39 -08001964X86Assembler* X86Assembler::gs() {
1965 // TODO: fs is a prefix and not an instruction
1966 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1967 EmitUint8(0x65);
1968 return this;
1969}
1970
Ian Rogers2c8f6532011-09-02 17:16:34 -07001971void X86Assembler::AddImmediate(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001972 int value = imm.value();
1973 if (value > 0) {
1974 if (value == 1) {
1975 incl(reg);
1976 } else if (value != 0) {
1977 addl(reg, imm);
1978 }
1979 } else if (value < 0) {
1980 value = -value;
1981 if (value == 1) {
1982 decl(reg);
1983 } else if (value != 0) {
1984 subl(reg, Immediate(value));
1985 }
1986 }
1987}
1988
1989
Roland Levillain647b9ed2014-11-27 12:06:00 +00001990void X86Assembler::LoadLongConstant(XmmRegister dst, int64_t value) {
1991 // TODO: Need to have a code constants table.
1992 pushl(Immediate(High32Bits(value)));
1993 pushl(Immediate(Low32Bits(value)));
1994 movsd(dst, Address(ESP, 0));
1995 addl(ESP, Immediate(2 * sizeof(int32_t)));
1996}
1997
1998
Ian Rogers2c8f6532011-09-02 17:16:34 -07001999void X86Assembler::LoadDoubleConstant(XmmRegister dst, double value) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002000 // TODO: Need to have a code constants table.
2001 int64_t constant = bit_cast<int64_t, double>(value);
Roland Levillain647b9ed2014-11-27 12:06:00 +00002002 LoadLongConstant(dst, constant);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002003}
2004
2005
Ian Rogers2c8f6532011-09-02 17:16:34 -07002006void X86Assembler::Align(int alignment, int offset) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002007 CHECK(IsPowerOfTwo(alignment));
2008 // Emit nop instruction until the real position is aligned.
2009 while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) {
2010 nop();
2011 }
2012}
2013
2014
Ian Rogers2c8f6532011-09-02 17:16:34 -07002015void X86Assembler::Bind(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002016 int bound = buffer_.Size();
2017 CHECK(!label->IsBound()); // Labels can only be bound once.
2018 while (label->IsLinked()) {
2019 int position = label->LinkPosition();
2020 int next = buffer_.Load<int32_t>(position);
2021 buffer_.Store<int32_t>(position, bound - (position + 4));
2022 label->position_ = next;
2023 }
2024 label->BindTo(bound);
2025}
2026
2027
Mark Mendell73f455e2015-08-21 09:30:05 -04002028void X86Assembler::Bind(NearLabel* label) {
2029 int bound = buffer_.Size();
2030 CHECK(!label->IsBound()); // Labels can only be bound once.
2031 while (label->IsLinked()) {
2032 int position = label->LinkPosition();
2033 uint8_t delta = buffer_.Load<uint8_t>(position);
2034 int offset = bound - (position + 1);
2035 CHECK(IsInt<8>(offset));
2036 buffer_.Store<int8_t>(position, offset);
2037 label->position_ = delta != 0u ? label->position_ - delta : 0;
2038 }
2039 label->BindTo(bound);
2040}
2041
2042
Ian Rogers44fb0d02012-03-23 16:46:24 -07002043void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) {
2044 CHECK_GE(reg_or_opcode, 0);
2045 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002046 const int length = operand.length_;
2047 CHECK_GT(length, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002048 // Emit the ModRM byte updated with the given reg value.
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002049 CHECK_EQ(operand.encoding_[0] & 0x38, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002050 EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002051 // Emit the rest of the encoded operand.
2052 for (int i = 1; i < length; i++) {
2053 EmitUint8(operand.encoding_[i]);
2054 }
Mark Mendell0616ae02015-04-17 12:49:27 -04002055 AssemblerFixup* fixup = operand.GetFixup();
2056 if (fixup != nullptr) {
2057 EmitFixup(fixup);
2058 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002059}
2060
2061
Ian Rogers2c8f6532011-09-02 17:16:34 -07002062void X86Assembler::EmitImmediate(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002063 EmitInt32(imm.value());
2064}
2065
2066
Ian Rogers44fb0d02012-03-23 16:46:24 -07002067void X86Assembler::EmitComplex(int reg_or_opcode,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002068 const Operand& operand,
2069 const Immediate& immediate) {
Ian Rogers44fb0d02012-03-23 16:46:24 -07002070 CHECK_GE(reg_or_opcode, 0);
2071 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002072 if (immediate.is_int8()) {
2073 // Use sign-extended 8-bit immediate.
2074 EmitUint8(0x83);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002075 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002076 EmitUint8(immediate.value() & 0xFF);
2077 } else if (operand.IsRegister(EAX)) {
2078 // Use short form if the destination is eax.
Ian Rogers44fb0d02012-03-23 16:46:24 -07002079 EmitUint8(0x05 + (reg_or_opcode << 3));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002080 EmitImmediate(immediate);
2081 } else {
2082 EmitUint8(0x81);
Ian Rogers44fb0d02012-03-23 16:46:24 -07002083 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002084 EmitImmediate(immediate);
2085 }
2086}
2087
2088
Ian Rogers2c8f6532011-09-02 17:16:34 -07002089void X86Assembler::EmitLabel(Label* label, int instruction_size) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002090 if (label->IsBound()) {
2091 int offset = label->Position() - buffer_.Size();
2092 CHECK_LE(offset, 0);
2093 EmitInt32(offset - instruction_size);
2094 } else {
2095 EmitLabelLink(label);
2096 }
2097}
2098
2099
Ian Rogers2c8f6532011-09-02 17:16:34 -07002100void X86Assembler::EmitLabelLink(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002101 CHECK(!label->IsBound());
2102 int position = buffer_.Size();
2103 EmitInt32(label->position_);
2104 label->LinkTo(position);
2105}
2106
2107
Mark Mendell73f455e2015-08-21 09:30:05 -04002108void X86Assembler::EmitLabelLink(NearLabel* label) {
2109 CHECK(!label->IsBound());
2110 int position = buffer_.Size();
2111 if (label->IsLinked()) {
2112 // Save the delta in the byte that we have to play with.
2113 uint32_t delta = position - label->LinkPosition();
2114 CHECK(IsUint<8>(delta));
2115 EmitUint8(delta & 0xFF);
2116 } else {
2117 EmitUint8(0);
2118 }
2119 label->LinkTo(position);
2120}
2121
2122
Ian Rogers44fb0d02012-03-23 16:46:24 -07002123void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00002124 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002125 const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002126 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2127 CHECK(imm.is_int8());
2128 if (imm.value() == 1) {
2129 EmitUint8(0xD1);
Mark P Mendell73945692015-04-29 14:56:17 +00002130 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002131 } else {
2132 EmitUint8(0xC1);
Mark P Mendell73945692015-04-29 14:56:17 +00002133 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002134 EmitUint8(imm.value() & 0xFF);
2135 }
2136}
2137
2138
Ian Rogers44fb0d02012-03-23 16:46:24 -07002139void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00002140 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07002141 Register shifter) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002142 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2143 CHECK_EQ(shifter, ECX);
2144 EmitUint8(0xD3);
Mark P Mendell73945692015-04-29 14:56:17 +00002145 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07002146}
2147
Mark Mendell0616ae02015-04-17 12:49:27 -04002148void X86Assembler::AddConstantArea() {
Vladimir Marko93205e32016-04-13 11:59:46 +01002149 ArrayRef<const int32_t> area = constant_area_.GetBuffer();
Mark Mendell0616ae02015-04-17 12:49:27 -04002150 // Generate the data for the literal area.
2151 for (size_t i = 0, e = area.size(); i < e; i++) {
2152 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2153 EmitInt32(area[i]);
2154 }
2155}
2156
Mark Mendell805b3b52015-09-18 14:10:29 -04002157size_t ConstantArea::AppendInt32(int32_t v) {
2158 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002159 buffer_.push_back(v);
2160 return result;
2161}
2162
Mark Mendell805b3b52015-09-18 14:10:29 -04002163size_t ConstantArea::AddInt32(int32_t v) {
2164 for (size_t i = 0, e = buffer_.size(); i < e; i++) {
2165 if (v == buffer_[i]) {
2166 return i * elem_size_;
2167 }
2168 }
2169
2170 // Didn't match anything.
2171 return AppendInt32(v);
2172}
2173
2174size_t ConstantArea::AddInt64(int64_t v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002175 int32_t v_low = Low32Bits(v);
2176 int32_t v_high = High32Bits(v);
2177 if (buffer_.size() > 1) {
2178 // Ensure we don't pass the end of the buffer.
2179 for (size_t i = 0, e = buffer_.size() - 1; i < e; i++) {
2180 if (v_low == buffer_[i] && v_high == buffer_[i + 1]) {
Mark Mendell805b3b52015-09-18 14:10:29 -04002181 return i * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002182 }
2183 }
2184 }
2185
2186 // Didn't match anything.
Mark Mendell805b3b52015-09-18 14:10:29 -04002187 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002188 buffer_.push_back(v_low);
2189 buffer_.push_back(v_high);
2190 return result;
2191}
2192
Mark Mendell805b3b52015-09-18 14:10:29 -04002193size_t ConstantArea::AddDouble(double v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002194 // Treat the value as a 64-bit integer value.
2195 return AddInt64(bit_cast<int64_t, double>(v));
2196}
2197
Mark Mendell805b3b52015-09-18 14:10:29 -04002198size_t ConstantArea::AddFloat(float v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002199 // Treat the value as a 32-bit integer value.
2200 return AddInt32(bit_cast<int32_t, float>(v));
2201}
2202
Ian Rogers2c8f6532011-09-02 17:16:34 -07002203} // namespace x86
Ian Rogersb033c752011-07-20 12:22:35 -07002204} // namespace art